JPH0324814A - Dc/dc converter - Google Patents

Abstract

PURPOSE:To improve the circuit efficiency by short-circuiting one current terminal of an FET for PWM and a voltage control terminal simultaneously with turning-off of this FET for PWM. CONSTITUTION:A transistor TR Q3 for discharging circuit is connected between the gate and the source of an FET Q1 for PWM as an electric charge discharging circuit, and this TR Q3 for discharging circuit is automatically turned on simultaneously with turning-off of the FET Q1 for PWA to short-circuit the gate and the source of the FET Q1 for PWM by this TR Q3 for discharging circuit m A resistance R having a proper resistance value with respect to the main current is inserted to the main current circuit of a TR Q2 for control. Thus, the loss in the resistance R and the TR Q3 for control is reduced without reducing the turning-off speed of the FET Q1 for PWM and the calorific value is reduced to improve the circuit efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in DC-DC converters. especially,
This invention relates to an improvement in a DC-DC converter with the purpose of having less loss and therefore less heat generation, thereby improving circuit efficiency. [Prior Art] An example of a conventional DC-DC converter will be explained with reference to FIG. 2. In the diagram shown in FIG. 2, E! is the human power voltage applied to the input terminal IN, and E is the output voltage output from the output terminal OUT. Q1 is the P channel M which is the switching means
It is an OS type field effect transistor (hereinafter referred to as PWM FET2), and Q. is a control transistor that controls the on/off of the PWM FETQ in response to the current signal PS, R is a resistor, and the PWM FETQ I
When the power source of the gate signal of Q. is shared with the input power source of the DC-DC converter, the control transistor Q. It functions as a current limiting resistor for the PWM FET Ql and as a discharge circuit resistor for discharging the charge accumulated in the floating capacitance between the gate and source of the PWM FET Ql. Ll
is a smoothing inductance, and cg is a smoothing capacitor, both of which constitute an inverted L-type smoothing circuit SC. D is a flywheel diode. Further, Ov indicates the ground potential, which must be lower than either the input voltage E or the output voltage E0. The operation of the circuit of the conventional DC-DC converter shown in the figure will be briefly explained. When the current signal PS is absent and the control transistor Q is off, the PWM F
Since the gate potential of ETQ+ is the same as the source potential, PWM FETQI is in an off state. Next, control transistor Q. When a pulsed control current signal PS as shown in the figure is supplied to the base of the control transistor Q
, turns on, and the PWM FET. Since the gate potential of Ql drops to tenon Ov, PWM FET Q + turns on. The collector current of the turned-on control transistor Q2 has a value limited by the resistor R. current signal P
S disappears and the control transistor Q. base current is 0
(0), the control transistor Q8 is turned off again, and the gate potential of the PWM FET Q + becomes the same as the source potential again, so the PWM FET
Q + turns off again, PWM FET Q r
When turned off, the charge accumulated in the floating capacitance between the gate and source of the PWM FET QI is discharged through the resistor R. In order to achieve a sufficiently fast turn-off speed, the resistor R is It is necessary to reduce the value of . When the PWM FETQI is on,
Power is supplied to the load side via the PWM FET QI, the inverted L-type smoothing circuit SC, and the output terminal OUT. On this occasion,
The inverse I2 type smoothing circuit SC smoothes the output voltage E0, P
When the WM FET Q+ is off, the energy stored in the smoothing inductance L1 is supplied to the load side via the flywheel diode D, so the output current is not interrupted. [Problem to be solved by the invention] In the DC-DC converter according to the prior art, PWM
If it is possible to increase the switching frequency by increasing the turn-off speed of the FETQ, the frequency of harmonics that inevitably occur will increase, so there are benefits such as the ability to downsize the smoothing circuit. To achieve this,
As mentioned above, the value of the resistor R can be made small, but if the resistor R is made small, in the ON state of the PWM FET Q+, that is, in the ON state of the control transistor Q8,
The current flowing through the resistor R to the collector of the control transistor Q8 increases, and the resistor R and the control transistor Q! This increases the losses in the circuit and reduces the circuit efficiency, that is, the efficiency of the device, and requires a heat dissipation means to dissipate the amount of heat generated by these losses, which has the disadvantage of increasing the size of the device. On the other hand, if the resistance R is increased, the PWM F
The turn-off of the ETQ is delayed, making it difficult to increase the switching frequency, and the smoothing inductance L and smoothing capacitor C become larger. The purpose of the present invention is to eliminate these drawbacks,
DC that can reduce loss in resistor R and control transistor Q8, reduce heat generation, and improve circuit efficiency without reducing the turn-off speed of PWM FET QI
- To provide a DC converter.

[Means to solve the problem]

The purpose of the above is that one current terminal (S) is connected to the input terminal (IN
), the other current terminal (D) is connected to the output terminal (OUT) via the flywheel diode (D3) and the smoothing circuit (SC), and the voltage control terminal (G) is connected to the current control terminal ( It operates in response to the current signal (PS) applied to B), and one main current terminal (E) is connected to the other main current terminal (C) of the control transistor (Q2), which is at ground potential. One end is connected to the input terminal (IN), and the other end is connected to the other main current terminal (C) of the control transistor (Q3).
) and a control transistor main current limiting resistor (R) connected to the PWM converter.
A PWM FE that short-circuits the one current terminal (S) of the PWM FET (Q+) and the voltage control terminal (G) at the same time that the PWM FET (Q2) turns off.
This is accomplished by a DC-DC converter with T-shorting means (DC). However, in this DC-DC converter, as described below, the PWM FET shorting means (DC) may not function satisfactorily.
A PW that maintains the operation of the PWM FET shorting means (DC) while the M FET (Q+) is off.
If the M FET short-circuiting means operation maintaining means (HC) is provided,
An even better DC-DC converter can be realized.

The PWM FET short-circuiting means (DC) has a collector connected to one end on the human power side of the control transistor main current limiting resistor (R), and is configured to limit the main current of the control transistor. a discharge circuit transistor (Q3) whose base is connected to one output side end of the resistor (R) for the discharge circuit, and whose emitter is connected to the voltage control terminal (G) of the PWM FET (Q2); Voltage control terminal (G
), and a reverse bias diode (D3) having a positive terminal connected to the control transistor (Q2) and a negative terminal connected to the other main current terminal (C) of the control transistor (Q2). In addition, the above-mentioned PWM FET short-circuiting means operation maintaining means (H
As an example of C), the positive side of the input terminal (IN) is connected between the input terminal (IN) and the first input terminal of the control transistor main current limiting resistor (R). A backflow blocking diode (D1) connected as a backflow blocking diode (D3)
A capacitor (C1) may be connected between the negative side of the PWM FET (Q+) and the voltage control terminal (G) of the PWM FET (Q+). [Operation] In the conventional DC-DC converter, PW
During the period when the M FET Q + is on, a non-negligible amount of charge is inevitably accumulated in the floating capacitance between the gate and source of the PWM FET Q +. A discharge circuit is provided to discharge this charge when FETQ+ turns off.
In the conventional DC-DC converter, the above-mentioned drawback is caused by the fact that the resistor of the charge discharge circuit between the gate and source and the resistor for limiting the collector current of the control transistor Q are shared. are doing. Therefore, in the DC-DC converter according to the present invention, the charge discharge circuit and the main current circuit of the control transistor Q are separated. That is,
As a discharge circuit for the above charge, FETQ for PWM is used.
A discharge circuit transistor Q is connected between the gate and source of PWM FET Q.r. At the same time as the FET is turned off, the discharge circuit transistor Qs is automatically turned on, and the gate and source of the PWM FET QI are short-circuited using the discharge circuit transistor Q. On the other hand, a resistor R having an appropriate resistance value with respect to the main current is inserted into the main current circuit of the control transistor Q. Next, PWM FET shorting means DC according to the gist of the present invention
The action of this and the action of the PWM FET short-circuiting means operation maintaining means HC will be described in detail with reference to the drawings. B. Function of FET short-circuiting means DC for PWM Referring to FIG. 1b, an example of the PET short-circuiting means DC for PWM is shown. In the figure, E! is the input voltage applied to the input terminal IN, and E0 is the output voltage output from the output terminal OUT. QI is a PWM FET; is a control transistor that controls on/off of the PWM FET Qr in response to the current signal PS, and R is a resistor. Q is a charge discharge circuit transistor that shorts the source and gate of the PWM FET Q, and the PWM FET
When Q+ is turned off, the charge accumulated in the floating capacitance between the gate and source is discharged. D
! is a reverse bias diode that applies a reverse bias voltage to the base of the discharge circuit transistor Q3. Also,
E-C-B are control transistors Q! are one main current terminal, the other main current terminal, and a current control terminal, and S-D-G are respectively connected to the PWM FETQ. One current terminal, the other current terminal, and voltage control terminal.
Next, the operation of this PWM FF and T shorting means DC will be explained. Control transistor Q. is off, the gate potential of PWM FETQI is almost the same as the source potential, so PWM FETQ. is in the off state. When the current signal PS is input to the current control terminal B of the control transistor Q2, the control transistor Q2 is turned on, and the gate potential of the PWM FET Ql becomes almost VQv, so the PWM FBTQr is turned on. ．． Further, the discharge circuit transistor Q, is a reverse bias diode D! Since the control transistor Q2 is reverse biased and turned off, the main current of the control transistor Q2 flows through the resistor R. Control transistor Q. When the current signal PS to the current signal PS becomes O (zero), the control transistor Qg is turned off, and the control transistor Qg is turned off through the reverse current blocking diode D and the resistor R. The current flowing through the discharge circuit transistor Q
, so the discharge circuit transistor Q3
turns on. When the discharge circuit transistor Q3 turns on, the input voltage E! By ゛C discharge circuit transistor Q3
Since current flows into the gate of PWM FETQI through the gate, the gate potential of PWM FETQ increases and PW
M FETQ. will be turned off. FET for PWM
When Q is turned off, the gate of this PWM FET QI is turned off.
The charge accumulated in the stray capacitance between the sources is
The PWM transistor Q. is short-circuited by the discharge circuit transistor Q., which is turned on. It will be rapidly discharged into the low resistance circuit between the source and gate of the cell. B. Operation of PWM FET short-circuiting means operation maintaining means HC Refer to FIG. 1c, which shows an example of PWM FET shorting means operation maintaining means HC1. In the figure, C1 is a capacitor for maintaining PWM FET short-circuit operation, and D. is a backflow blocking diode that prevents the charge of capacitor C from flowing out to the input side. The symbols other than the above are the same as in Figure 1b. Next, this PWM FET short circuit means operation maintaining means HC
The operation will be explained. Following the operation in item A above, when the gate potential of the PWM FET QI further increases, the discharge circuit transistor Q3 increases through the resistor R.
The current flowing into the base of the transistor Q3 decreases, and eventually it becomes impossible to maintain the on state of the discharge circuit transistor Q3, and if the turn-off of the PWM FET QI has not been completed by that time, the turn-off The off-speed will rapidly decrease. The means to prevent this is PW
PWM FETQ.M FET short-circuiting means operation maintaining means HC. As the gate potential of the reverse current blocking diode D rises, the potential of the cathode of the reverse blocking diode D becomes higher than the input voltage E, so that the charge accumulated in the capacitor CI passes through the resistor R to the discharge circuit transistor Q. This will be supplied as the base current. The capacitance value of the capacitor C1 and the resistance R are set so that the product of the capacitance value of the capacitor Cl and the value of the resistor R is larger than the switching period.
The value of transistor Q. for the discharge circuit is set. is maintained in the on state, and the PWM FETQ. The short-circuit operation between the gate and source of the PWM FET QI is maintained to ensure the desired turn-off speed of the PWM FET QI. [Example] Hereinafter, with reference to the drawings, DC-
Let me explain about the DC converter. As explained in the above operation section, the present invention includes (a) DC-
A structure in which a PWM FET shorting means DC is added to the DC converter, and (b) both a PWM FET shorting means DC and a PWM FET shorting means operation maintaining means HC are added to the DC-DC converter according to the prior art. There is a structure that was created. PWM FET in DC-DC converter according to conventional technology
It is clear that a DC-DC converter with only a short-circuiting means DC added functions effectively, but if the conventional DC-DC converter has a PWM FET shorting means DC and a PWM FET shorting means maintaining operation. It is clear that a structure in which both the means HC and the means HC are added is a further improved structure, so in order to avoid redundancy, in this specification, mainly PWM A structure in which both the PWM FET shorting means DC and the PWM FET shorting means operation maintaining means HC are added will be explained. In the diagram shown in FIG. ta, Ei is the input voltage applied to the input terminal IN, and E0 is the output voltage output from the output terminal OUT. Q is a PWM FET, Q8 is a control transistor that controls on/off of the PWM FET Q + in response to a current signal PS, and R is a resistor. By the way, in the DC-DC converter according to the present invention, since the power source of the gate signal of PWM FET Q + and the input power source of the DC-DC converter are shared, the above-mentioned resistor R is used as the above-mentioned control power source. As in the case of the prior art, the transistor Q also functions as a current limiting resistor. DC is the PWM FET shorting means according to the first aspect of the present invention, and the structure in which only the PWM FET shorting means DC is added to the above-mentioned conventional DC-DC converter also has the same characteristics as the conventional technology. Even in a structure in which both the PWM FET shorting means DC and the PWM FET shorting means operation support means HC are added to such a DC-DC converter, these are essential structural elements, and their operations will be explained below. do. Control transistor Q. is off, the PWM F
Since the gate potential of E T Q l is almost the same as the source potential, PWM FET QI is in an off state. When the current signal PS is input to the current control terminal B of the control transistor Q8, the control transistor Q2 turns on and PW
Since the gate potential of the M FETQt becomes 0, the PWM FETQI turns on. Also,
The discharge circuit transistor Q, is connected to the reverse bias diode D. Since the control transistor Q. is reverse biased and turned off, the control transistor Q. The main current flows through resistor R. When the current signal PS to the control transistor Q8 becomes O (zero), the control transistor Q is turned off, and the current flowing to the control transistor Q8 through the reverse blocking diode D and the resistor R is transferred to the discharge circuit. Transistor Q
Since the base current is 3, the discharge circuit transistor Qs
turns on. When the discharge circuit transistor Q is turned on, the input voltage E! As a result, current flows into the gate of PWM FET Q+ through discharge circuit transistor Qs, so the gate potential of PWM FET QI rises and PWM
The F ET Q + will be turned off. PWM
When the PWM FE T Q r is turned off, this PWM FE
TQ. The charge accumulated in the floating capacitance between the gate and source of the discharge circuit transistor Q3, which is turned on, is
PWM transistor Q. short-circuited by Q. It will be rapidly discharged into the low resistance circuit between the source and gate of the cell. HC is a PWM FET shorting means operation maintaining means according to the second aspect of the present invention, and is different from the DC-
DC converter and PWM FET shorting means DC and PWM
This is an essential structural element only in a structure in which both the FET shorting means and the operation maintaining means HC are added, and their operation will be explained below. Following the above operation, PWM FETQ
When the positive gate potential further increases, the current flowing into the base of the discharge circuit transistor Q3 through the resistor R decreases, and finally the discharge circuit transistor Q3 can no longer be maintained in the on state, and by that time the PWM F
If the turn-off of E T Q + is not completed, the turn-off speed will decrease rapidly. The means for preventing this is the PWM FET short circuit means operation maintaining means HC, which is the PWM FET Q. When the gate potential of the reverse current blocking diode D1 rises, the potential of the cathode of the reverse current blocking diode D1 becomes higher than the input voltage E▲, so the charge accumulated in the capacitor C1 passes through the resistor R and increases the base current of the discharge circuit transistor Qs. It will be supplied as. The capacitance value of the capacitor CI and the value of the resistor R are set so that the product of the capacitance value of the capacitor CI and the value of the resistor R is larger than the switching period, and the discharge circuit transistor Qs is turned on. Maintain the condition, PW
Maintain the short-circuit operation between the gate and source of the M FET Q- and ensure the desired turn-off speed of the PWM FET Q+. Hereinafter, PWM
The structure and operation of the structure in which the PWM FET short-circuiting means DC and the PWM FET short-circuiting means operation maintaining means HC are added will be further explained. L. is a smoothing inductance, C8 is a smoothing capacitor, and both of these constitute an inverted L-type smoothing circuit. is the flywheel diode,
This is the same as the structural element of the DC-DC converter according to the prior art. Also, Ov indicates the ground potential,
It is also the same as in the case of the prior art that the potential must be lower than either the input voltage E or the output voltage E0. Next, the operation of the circuit of the DC-DC converter according to the present invention shown in FIG. 1a will be explained. When the control transistor Qt is off, the gate potential of the PWM FET Ql is almost the same as the source potential, so the PWM
The FET Q + is in the off state. When a pulsed control current signal PS is supplied to the base B of the control transistor Q8 as shown in the figure, the control transistor Q8 turns on, and the gate potential of the PWM FET QI drops to V O V. Therefore, PWM FETQI turns on. At this time, the discharge circuit transistor Q3 is a reverse bias diode D! Since the control transistor Q. is reverse biased and turned off, the control transistor Q. The current flowing into the collector of flows through the resistor R. At this time, the capacitor C is charged to a voltage obtained by subtracting the voltage drops across the reverse blocking diode D, the reverse bias diode D8, and the control transistor Qt from the input voltage EI. Current signal PS disappears and control transistor Q. When the current supplied to the base B of the control transistor Q becomes O (zero), the control transistor Q. is turned off, and the backflow blocking diode D,
The current flowing to the collector of the control transistor Q through the resistor R becomes the base current of the discharge circuit transistor Q, so that the discharge circuit transistor Q3 is turned on. When the discharge circuit transistor Q is turned on, current flows into the gate G of the PWM FET QI through the discharge circuit transistor Q3 due to the input voltage Et, so the gate potential of the PWM FET QI rises and the PWM FET Q + becomes It will be turned off. Furthermore, when the gate potential of the PWM FET Q rises, the potential on the cathode side of the reverse blocking diode D1 becomes higher than the input voltage E1, so that the charge accumulated in the capacitor CI passes through the resistor R and goes through the discharge circuit. The capacitance value of the capacitor C1 is set so that the product of the capacitance value of the capacitor C and the resistance value of the resistor R is larger than the switching period. If the resistance value of the resistor R and the resistance value of the resistor R are set, the ON state of the discharge circuit transistor Q3 is maintained, and the PWM FET Q+ is kept in the OFF state.

In this way, (a) PWM FETQ+ turns
When turned off, the gate and source of the PWM FET Q + are short-circuited by the reasonably set period discharge circuit transistor Q3, so that the P'//M FET Q,
The charge stored in the floating capacitance between the gate and source of the device will be quickly released. Also, (b)
Since the resistor R also has the role of determining the base current of the discharge circuit transistor Q,
If the DC current amplification factor tlFE of the control transformer tlFE is large to some extent, the resistance value of the resistor R can be increased, and the control transformer ? The current flowing to the collector when the star Q■ is turned on can be made sufficiently small. [Effects of the Invention] As explained above, the DC-DC converter according to the present invention has many effects listed below. (a) PWM FET (Q3) which is a switching means
For example, the collector is connected to one terminal on the human power side of the control transistor main current limiting resistor (R) between the gate and source of the control transistor main current limiting resistor (R).
), the base is connected to the output side l end of the PWM F
A discharge circuit transistor (Q3) whose emitter is connected to the voltage control terminal (G) of ET (Ql 'J) and P
A reverse bias diode (with a positive direction terminal connected to the voltage control terminal (C3) of the WM FET (Q1) and a negative direction terminal connected to the other main current terminal (C) of the control transistor (Q2) D3) PWM configured with
Since FET shorting means (DC) is provided for PW
When the M FET (Q1) turns off, the discharge circuit transistor (Q2), which constitutes the PWM FET shorting means (DC), turns off.
) is connected, and the above discharge circuit transistor (Q3)
turns on automatically and PWMJIIFET (Q+)
The charge stored in the floating capacitance between the gate and source of the circuit can be discharged to a circuit with an extremely low resistance value. ) and the reverse current blocking diode (DI) connected between the input side l end of the input terminal (IN) and the reverse current blocking diode (D3)
The voltage control terminal (
G) and a capacitor (C+) connected between the . PWM FET short circuit means operation maintenance means (
Since the PWM FET short-circuiting means operation maintaining means (HC) is provided, a capacitor (CI
), the above discharge circuit is maintained for a sufficiently long period of time, and the charge stored in the floating capacitance between the gate and the source of the PWM FET (Q1) is sufficiently discharged.
These effects act synergistically to improve PWM FET (Q
1) It is possible to increase the turn-off speed. (Excerpt) The value of the resistance (R) of the circuit that flows the collector current of the control transistor (Q3) is . Since it is possible to select a large number regardless of the above-mentioned discharge circuit, the loss generated in the DC-DC converter can be reduced, and therefore, the heat dissipation means can be simplified, and the device can be made smaller and lighter. .

(c) Also, since the turn-off speed can be increased, the switching frequency can be increased to a desired value, and the smoothing inductance and smoothing capacitor can be downsized.

[Brief explanation of drawings]

FIG. 1a is a structural diagram of a DC-DC converter according to an embodiment of the present invention. FIG. 1b shows a PWM FET according to the first aspect of the present invention.
It is a diagram for explaining the operation of the short circuit means DC. FIG. IC is a diagram for explaining the operation of the PWM FET short circuit means operation maintaining means IC according to the second aspect of the present invention. FIG. 2 is a structural diagram of a DC-DC converter according to the prior art. E1...Human voltage, E. ...Output voltage, Q. ...PWM FET (P channel MOS
・Control transistor, ・PWM FET short-circuiting means, ・Discharge circuit transistor, ・Reverse bias diode, resistor, ・PWM FET short-circuit means operation maintenance means, ・Capacitor, ・Backflow blocking diode , ・Smoothing circuit, ・Smoothing inductance, ・Smoothing capacitor, ・Flywheel diode, Q1 DC ・ Q1 D1 R ・ ・ HC ・ C1 ・ D1 ・ SC ・ 1.1 ・ C1 D1 IN ・ ・ OUT ・ Ov ・ ・S ・ ・ ・ D ・ ・ ・ G ・ ・ ・ PS ・ ・ E ・ ・ ・ C ・ ・ ・ ・ B ・ ・ ・ ・Input terminal, ・Output terminal, ・Ground potential, One current terminal of PWM FET, PWM The other current terminal of the FET for PWM, the i-pressure m terminal of the FET for PWM, ・Current signal,

Claims (1)

[Claims] [1] One current terminal (S) is connected to an input terminal (IN), and the other current terminal (D) is connected to a flywheel diode (D_3) and a smoothing circuit (SC). Output terminal (
OUT), the voltage control terminal (G) operates in response to a current signal (PS) applied to the current control terminal (B), and one main current terminal (E) is set to ground potential. A PWM FET (Q_1) connected to the other main current terminal (C) of the control transistor (Q_2),
One end is connected to the input terminal (IN), and the other end is connected to the other main current terminal (C) of the control transistor (Q_2).
In a DC-DC converter having a control transistor and a main current limiting resistor (R) connected to a control transistor, at the same time when the PWM FET (Q_1) is turned off, the one current terminal of the PWM FET (Q_1) is turned off. (S)
and the voltage control terminal (G) are short-circuited.
A DC-DC converter characterized by having T-shorting means (DC). [2] One current terminal (S) is connected to the input terminal (IN), and the other current terminal (D) is connected to the output terminal (S) via the flywheel diode (D_3) and the smoothing circuit (SC).
OUT), the voltage control terminal (G) operates in response to a current signal (PS) applied to the current control terminal (B), and one main current terminal (E) is set to ground potential. A PWM FET (Q_1) connected to the other main current terminal (C) of the control transistor (Q_2),
One end is connected to the input terminal (IN), and the other end is connected to the other main current terminal (C) of the control transistor (Q_2).
In a DC-DC converter having a control transistor and a main current limiting resistor (R) connected to a control transistor, at the same time when the PWM FET (Q_1) is turned off, the one current terminal of the PWM FET (Q_1) is turned off. (S)
and the voltage control terminal (G) are short-circuited.
T shorting means (DC); and P which maintains the operation of the PWM FET shorting means (DC) while the PWM FET (Q_1) is off.
A DC-DC converter comprising a WM FET short circuit means and an operation maintaining means (HC). [3] The PWM FET shorting means (DC) has a collector connected to one end of the input side of the control transistor main current limiting resistor (R), and has a collector connected to one end of the input side of the control transistor main current limiting resistor (R). A discharge circuit transistor (Q_3) whose base is connected to one output side terminal and whose emitter is connected to the voltage control terminal (G) of the PWM FET (Q_1).
), a positive terminal is connected to the voltage control terminal (G) of the PWM FET (Q_1), and the control transistor (Q_1) is connected to the voltage control terminal (G) of the PWM FET (Q_1).
The DC-DC converter according to claim 1 or 2, comprising a reverse bias diode (D_2) whose negative direction terminal is connected to the other main current terminal (C) of 2). . [4] The PWM FET short circuit means operation maintaining means (HC
) is a reverse current blocking diode connected between the input terminal (IN) and one end of the input side of the control transistor main current limiting resistor (R) with the positive side of the input terminal (IN) as the positive side; (D_1) and the backflow blocking diode (D_
1) and a capacitor (C_1) connected between the negative side of the DC-D and the voltage control terminal (G) of the PWM FET (Q_1).
C converter.