JPH03124260A - Dc-dc converter - Google Patents

Abstract

PURPOSE:To reduce the power loss of a DC-DC converter by using a field-effect transistor of the conductivity type opposite to that of a field effect transistor (p-channel FET) for PWM. CONSTITUTION:A field effect transistor(FET) Q4 is an N-channel FET, the conductivity type of which is opposite to that of a P-channel field effect transistor Q1 for PWM. The FET Q4 is cut off when the FET Q1 for PWM conducts to energize a load through a smoothing circuit SC. When the Q1 is cut off, on the other hand, the FET Q4 conducts to supply the lead with the energy stored in a smoothing inductance L1. The resistance of the FET Q4 is smaller than that of a flywheel diode. According to this method, the power loss of a DC-DC converter can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to improvements in DC-DC converters.

In particular, the present invention relates to improvements in DC-DC converters that aim to have less loss and therefore less heat, thereby improving circuit efficiency.

[Conventional technology]

An example of a conventional D(, -DC converter) will be described with reference to FIG.

Referring to FIG. 2, E8 is the input voltage applied to the input terminal IN, and Eo is the output voltage output from the output terminal OUT. Ql is a P-channel field effect transistor (hereinafter PW) which is the switching means of the DC-DC converter.
It is called M FET. ), C2 is a control transistor that controls on/off of the PWM FET Q in response to the current signal PS, R is a resistor, and C2 is a control transistor that controls the on/off of the PWM FET Q in response to the current signal PS.
When the gate signal Q power supply of TQ is shared with the input power supply of the DC-DC converter, the above control transistor Q
2 as the current limiting resistor, and the above PWM FET.
It functions as a discharge circuit resistor to discharge the charge accumulated in the floating capacitance between the gate and source of Q. L is a smoothing inductance, C2 is a smoothing capacitor, and both constitute an inverted smoothing circuit SC. D is a flywheel diode. Further, 0■ indicates the ground potential, which must be lower than either the input voltage E or the output voltage E0.

The operation of the conventional DC-DC converter circuit shown in the figure will be briefly described. When the current signal PS is absent and the control transistor Q2 is off, the PWM F
Since the gate potential of ETQ is the same as the source potential,
FETQ for PWM.

is in the off state. Next, when a pulsed control current signal PS is supplied to the base of the control transistor Q2 as shown in the figure, the control transistor Q2 is turned on and the PWM F
Since the gate potential of E T Q I drops to so 0, the PWM FET Q turns on. The collector current of the turned-on control transistor Q2 has a value limited by the resistor R. When the current signal PS disappears and the base current of the control transistor Q2 returns to 0 (zero), the control transistor Q2 is turned off again and the PWM FET QI
The gate potential of is again the same as the source potential, so
The PWM FETQr is turned off again. PWM
When the PWM FETQ turns on, the charge accumulated in the floating capacitance between the gate and source of the PWM FETQ is discharged through the resistor R, achieving a sufficiently fast turn-off speed. In order to achieve this, it is necessary to reduce the value of the resistor R.

When the PWM FETQI is on, the power is
It is supplied to the load side via the M FET Q + , the inverse smoothing circuit SC, and the output terminal OUT.

At this time, the inverse smoothing circuit SC smoothes the output voltage E0. When the PWM FETQ is off, the energy stored in the smoothing inductance L1 is
Since the output current is supplied to the load side via the flywheel diode D5, the output current is not interrupted.

[Problem to be solved by the invention]

In the D(, -DC converter according to the prior art), during the ON period of the above PWM FETQ, the smoothing circuit SC
When the energy stored in the inductance constituting the PWM FET QI is supplied to the load during the OFF period of the PWM FET QI, the loss generated in the flywheel diode D5, which serves as the current-carrying path, is an amount that cannot be ignored, and the DC -D
There are drawbacks that greatly reduce the efficiency of the C converter.

Also, the loss in the current limiting resistor R is similar to the loss in the flywheel diode D5.
This significantly reduces the efficiency of the DC converter. However, this current limiting resistor R is simply a control transistor Q.
In addition to the function of limiting the collector current of 2, the above P
When the WM FETQ is turned off, this PWM FE
It also has the function of configuring a discharge circuit for the charges accumulated in the floating capacitance between the gate and source of the TQ. Therefore, in the conventional DC-DC converter, if the resistance value is simply increased for the purpose of reducing the loss in the current limiting resistor R, the discharge of charge between the gate and source will be delayed, and the turn-off speed will be reduced. becomes slow, making it difficult to increase the switching frequency of the above-mentioned PWM FET QI, and the smoothing inductance L.

Another disadvantage is that the smoothing capacitor C2 becomes large in size.

The purpose of the present invention is to eliminate these drawbacks,
The first purpose is to provide a DC-DC that has the same function as the flywheel diode D5, but has circuit elements with lower loss, generates less heat, and can improve circuit efficiency.
The purpose is to provide a converter. In addition to the first purpose, the second purpose is to reduce the turn-off speed of the PWM FET QI without reducing the turn-off speed of the PWM FET QI.
It is an object of the present invention to provide a DC-DC converter that can reduce loss in current limiting resistor R and control transistor Q2, reduce heat generation, and improve circuit efficiency.

[Means to solve the problem]

The first purpose of the above is: a. One current terminal (S1) is connected to the input terminal (IN), and the other current terminal (D1) is connected to the output terminal (OUT) via the smoothing circuit (SC). voltage control terminal (G
1) is the current signal (p) applied to the current control terminal (B).
A PWM FET (
Q1) and B. A control transistor main current limiter whose one end is connected to the input terminal (IN) and whose other end is connected to the other main current terminal (C) of the control transistor (G2). The voltage control terminal (G4) is connected to the voltage control terminal (G1) of the PWM FET (Q+), one current terminal (S4) is set to ground potential, and the other The current terminal (D4) is connected to the other current terminal (D1) of the PWM FET (Q1), and the current terminal (D4) is connected to the other current terminal (D1) of the PWM FET (Q1).
This is achieved using a D(, -DC converter) having a FET (G4) having a conductive polarity that becomes non-conductive or conductive in response to conduction or non-conduction in 1).

The second object is achieved by adding a PWM FET shorting means (DC) having the following configuration to the DC-DC converter according to claim (1).

The added PWM FET shorting means (DC) has its collector connected to the input terminal (IN), its base connected to one end of the output side of the control transistor main current limiting resistor (R), and the PWM FET (DC) Q1) voltage control terminal (Gl)
A discharge circuit transistor whose emitter is connected to (
Q3) and the voltage control terminal (G
1), the positive direction terminal is connected to the control transistor (Q
It consists of a reverse bias diode (D2) whose negative direction terminal is connected to the other main current terminal (C) of 2), and P
At the same time as the WM FET (Q1) turns off, the PWM FET (Q1) turns off.
It has a function of short-circuiting the one current terminal (S+) of the ET (Q1) and the voltage control terminal (Gl>) (Claim [2]).

However, in the DC-DC converter according to claim [2], as described below, the PWM FET shorting means (
DC) may not function satisfactorily, so in addition to the above, a PWM FET (DC) that maintains the operation of the PWM1 FET shorting means (DC) while the PWM FET (Q1) is off is added. F
If the ET shorting means operation maintaining means (HC) is provided, an even better DC-DC converter can be realized (Claim [3]
]).

[Function] In the conventional technology, PWM FET (1 conductivity type (P
When channel FET) Ql is turned off, the polarity of the voltage generated across the smoothing inductance L+ is in the forward direction of the flywheel diode D5, so the flywheel diode D5 conducts current and is accumulated in the smoothing inductance L. However, in the present invention, this flywheel diode D
, a field effect transistor Q4 having a conductivity polarity opposite to that of the PWM FET (FET with single conductivity polarity (P channel)) Ql is used instead.

The operation of this opposite conductive polarity FETQ will be explained below with reference to the drawings.

2 In the diagram shown in Figure 1a, Ql is PWM of 1 conductivity polarity (P channel)
It is a switching element of the main current circuit of the DC-DC converter, and when it is turned on, the smoothing circuit S
Energy is supplied to the load via C, and at this time, energy is accumulated in the smoothing inductance L that constitutes the smoothing circuit SC. Q4 is a FET according to the first aspect of the present invention, and has conductivity (N channel) opposite to that of the PWM FETQ.

This FETQ is off when the PWM FETQ + is on and supplying energy to the load via the smoothing circuit SC, but it is on when the PWM FETQ is off. , operates to supply the energy stored in the smoothing inductance L+ to the load. This operation is exactly the same as that of the flywheel diode D5. However, the difference is that the resistance of this FET Q is smaller than the resistance of the flywheel diode D, and the power loss is lower than when the flywheel diode D is used.

Thus, the first object of the present invention is achieved based on the property that the power loss of the FET is smaller than the power loss of the diode.

Next, the operation of the FET shorting means DC for PWM according to the second aspect of the present invention will be explained with reference to the drawings.

See Figure 1c. The figure shows an example of the PWM FET shorting means DC.

In the figure, Q3 is a charge discharge circuit transistor that short-circuits the source SI and gate G of the PWM FET Q , has the function of discharging when turned off. D2 is a reverse bias diode that applies a reverse bias voltage to the base of the discharge circuit transistor Q3.

When the control transistor Q2 turns on, the PWM FET
The gate potential of Q+ falls, and PWM FET Q is turned on. At this time, the discharge circuit transistor Q is reverse biased by the reverse bias diode D2 and is in an off state.

When the control transistor Qz turns off, the current that had been flowing to the control transistor Q2 through the resistor R becomes the base current of the discharge circuit transistor Q3, so the discharge circuit transistor Q3 turns on and the FET
A discharge circuit transistor Q3 is connected between the gate and source of Q.
shorted by. Therefore, FETQ for PWM
A current is rapidly supplied to the gate of + through the discharge circuit transistor Q3, and the gate potential of the PWM FET Q rapidly rises, causing the PWM FET QI
tries to turn off rapidly. At this time, PWM FETQ
The factor that inhibits the turn-off operation of FETQ is the charge accumulated in the floating capacitance between the gate and source of FETQ, but the gate and source of PWM FETQI
When the potential between the sources starts to change, at the same time, the charge accumulated in the above floating capacitor is also rapidly discharged via the discharge circuit transistor Q3, and the above PWM F
The factors inhibiting the turn-off operation of E T Q + are reduced, and as a result, the PWM FE
The turn-off time of TQ is shortened.

In this way, a reduction in switching speed can be avoided due to the charge accumulated in the floating capacitance between the gate and source of the FET, and the second object of the present invention is achieved.

Thirdly, the operation of the PWM FET shorting means operation maintaining means HC according to the third aspect of the present invention will be explained with reference to the drawings.

Referring to FIG. 1d, an example of the PWM FET short-circuiting means operation maintaining means HC is shown. In the figure, C3 is a capacitor for maintaining short-circuit operation of the PWM FET, and D is a reverse current blocking diode that prevents the charge of the capacitor C3 from flowing out to the input terminal. Reference numerals other than those mentioned above are the same as in FIG. 1c.

When the gate potential of the PWM FET Q further rises following the operation of the PWM FET short-circuiting means DC described above, the current flowing into the heath of the discharge circuit transistor Q3 through the resistor R decreases and finally discharges. It becomes impossible to maintain the on state of the circuit transistor Q3, and by that time the PWM FET
If the turn-off of Q+ is not completed, the turn-off speed will rapidly deplete. A means for preventing this is the PWM FET shorting means operation maintaining means HC.

When the gate potential of the PWM FET Q rises, the potential on the cathode side of the reverse blocking diode D3 becomes higher than the input voltage E, so the charge accumulated in the capacitor C3 passes through the resistor R to the discharge circuit transistor. It will be supplied as the base current of Q3. Capacitor C
If the capacitance value of the capacitor C1 and the value of the resistor R are set so that the product of the capacitance value of the capacitor C1 and the value of the resistor R is larger than the switching period, the discharge circuit transistor Q3 can be turned on. The state can be maintained and the FE for PWM
Maintain short-circuit operation between the gate and source of TQ, and PWM
The desired turn-off speed of the FET QI can be ensured.

In this way, the operation of the discharge circuit transistor Q3 can be maintained for a sufficiently long time, and the purpose is to avoid a reduction in switching speed due to the charge accumulated in the floating capacitance between the gate and source of the FET. The FET shorting means DC for PWM according to the second aspect of the present invention described above
The second object of the present invention can be more fully achieved.

〔Example〕

Hereinafter, DC-DC converters according to two embodiments of the present invention will be described with reference to the drawings.

11 DC-DCC Comparator Referring to FIG. 1a, E is the input voltage applied to the input terminal IN, and Eo is the output voltage output from the output terminal OUT. Q is a single conductivity polarity (P channel) PWM FET, Q2 is a control transistor that controls on/off of the PWM FET Q + in response to the current signal PS, and R is a resistor. be. SC is a smoothing circuit, which is composed of an inductance I and a capacitor C2. G4 has opposite conductivity (
N channel) FET. Further, E-C-B is one main current terminal and one of the control transistor Q2, respectively.
This is the other main current terminal/current control terminal.

Sl ・D, ・G, are PWM FET Q +
One current terminal, the other current terminal, and voltage control terminal. In addition, S4, D4, and G4 have opposite conductivity (N
One current terminal, the other current terminal, and the voltage control terminal of FETQ (channel).

Next, the operation of this circuit will be explained.

A current signal P is applied to the current control terminal B of the control transistor Q2.
When S is input, control transistor Q2 turns on,
Is it the gate potential of PWM FET QI with 1 conductivity polarity (P channel)? Since it becomes 0■, this FETQ is turned on. On the other hand, the gate of the opposite conductivity polarity (N channel) FETQ is connected to the above f7+1i polarity (Pf+channel) (DPW
M FETQ.

Since it is connected to the gate of No. 9 and the same potential is applied thereto, the above-mentioned opposite conductivity (N channel) FET G4 remains off.

When the current signal PS to the control transistor Q2 becomes O (zero), the control transistor Q2 is turned off, and the gate potential of the above-mentioned 1-conductivity (P channel) PWM FET Q rises to the input potential, and the source Since the potential is the same as the potential, this 1! The polarity (P-channel) FETQ is turned off. At this time, opposite conductivity (N channel) F E T
Since the gate potential of G4 also rises to the input potential and becomes +E with respect to the source potential, this opposite conductivity polarity (N channel) FET G4 is turned on and Ll-Load-〇a L+
A current conducting path is formed, and the energy stored in the above inductance I is supplied to the load.

In this opposite conductivity (N channel) FET G4, the current signal PS is inputted to the control transistor Q2.
This transistor Q2 turns on, and the above-mentioned one-conductivity polarity (P
When the PWM FBT Q1 of the channel) is turned on, it is turned off.

0 The resistance in the ON state between the drain and source of the opposite conductivity polarity (N-channel) FET G4 is about 17rnΩ, so for example, D V, which is overwhelmingly smaller than the voltage drop of 0.5 sq. of the conventional flywheel diode, and can greatly contribute to improving the efficiency of the DC-DC converter.

The DC-DC converter according to claim 2 of the present invention has PW
D according to claim 1, wherein an M FET shorting means DC is added.
The DC-DC converter according to claim 3 of the present invention is a PWM FET shorting means DC
2. The DC, -DC converter according to claim 1, further comprising: and a PWM FET shorting means operation maintaining means HC.

As already explained in the operation section above, the DC-DC has a configuration in which only the PWM FET shorting means DC is added.
It is clear that the converter also works effectively, but P
Since it is clear that the configuration in which both the WM F'ET shorting means DC and the PWM FET shorting means operation maintaining means HC are added is a further improved configuration, redundancy will be avoided in this specification. Therefore, a configuration in which both the PWM FET shorting means DC and the PWM F'ET shorting means operation maintaining means HC according to claim 3 are added will be described.

In the diagram with reference to FIG. 1b, E8 is the input voltage applied to the input terminal IN, and Eo is the output voltage output from the output terminal OUT. Ql is F for PWM with single conductivity polarity (P channel)
ET, and G2 is the PWM F in response to the current signal PS.
This is a control transistor that controls on/off of ETQ, and R is a resistor. Q is a charge discharge circuit transistor that shorts the source and gate of the PWM FET QI, and when the PWM FET QI is turned off,
Discharges the charge accumulated in the floating capacitance between the gate and source. D2 is a reverse bias diode that applies a reverse bias voltage to the base of the discharge circuit transistor Q3. C3 is a capacitor for maintaining the operation of the PWM FET shorting means, and D3 is a reverse current blocking diode that prevents the charge of the capacitor C4 from flowing out to the input side.

Q4 is an opposite conductivity (N channel) FET according to the first aspect of the present invention, and has a function of making it non-conductive and conductive in response to the conduction and non-conduction of the PWM FET. SC is a smoothing circuit composed of an inductance L and a capacitor C2. Also, OV indicates the ground potential, but the input voltage E! It is the same as in the case of the prior art that the potential must be lower than either of the output voltage E0 and the output voltage E0.

Next, the operation of this circuit will be explained. However, since the operation of the opposite conductive polarity FETQ was explained in detail in the first embodiment, the explanation will be omitted to avoid redundancy.

When the control transistor Q2 is off, the PWM FE
Since the gate potential of TQ is almost the same as the source potential, the PWM FETQI is in an off state. When a pulsed control current signal PS is supplied to the base B of the control transistor Q2 as shown in the figure, the control transistor Q2 is turned on and the PWM FET
Since the gate potential of Q+ drops to 0V, PWM
The F ET Q + is turned on. At this time, the discharge circuit transistor Q3 is reverse biased by the reverse bias diode D2 and is in an off state, so the current flowing to the collector of the control transistor Q2 is caused by the resistor R.
flowing through. At this time, the capacitors C and l are charged to a voltage obtained by subtracting the voltage drop across the reverse current blocking diode D3, the reverse bias diode D2, and the control transistor Q2 from the input voltage E1.

When the current signal PS disappears and the current supplied to the base B of the control transistor Q2 becomes 0 (zero), the control transistor Q2 turns off and the reverse current blocking diode D3
The current flowing to the collector of the control transistor Q2 through the resistor R becomes the base current of the discharge circuit transistor Q3, so that the discharge circuit transistor Q3 is turned on.

When the discharge circuit transistor Q3 turns on, the input voltage E
, PWM through the discharge circuit transistor Q3
Since current flows into the gate G of the PWM FETQ, the gate potential of the PWM FETQ rises and the PWM
FETQ will be turned off.

Furthermore, when the gate potential of the PWM FETQ rises, the potential on the cathode side of the backflow blocking diode D3 becomes higher than the input voltage E8, so the charge accumulated in the capacitor C3 passes through the resistor R to the discharge circuit. The capacitance value of the capacitor C3 is set so that the product of the capacitance value of the capacitor C3 and the resistance value of the resistor R is larger than the switching period. If the resistance value of the resistor R is set, the discharge circuit transistor Q3 is maintained in the on state, and the PWM FET Q + is kept in the off state.

In this way, (a) PWM FETQ turns
When turned off, the gate and source of the PWM FET QI are short-circuited by the discharge circuit transistor Q for a reasonably set period, so the gate and source of the PWM FET QI are short-circuited.
The charge stored in the floating capacitance between the sources is quickly released. (b) Since the resistor R also has the role of determining the base current of the discharge circuit transistor Q3, if the DC current amplification factor hFE of the discharge circuit transistor Q3 is large to some extent, the resistance value of the resistor R should also be increased. Therefore, the current flowing to the collector when the control transistor Q2 is turned on can be made sufficiently small.

〔Effect of the invention〕

As explained above, the DC-DC converter according to the present invention has many effects listed below.

(a) One current terminal (S4) of the opposite conductivity polarity FET (Q4) inserted in place of the flywheel diode in the prior art is set to the ground potential, and the other current terminal (D4) is set to the one conductivity polarity (P Channel) PWM F
It is connected to the other current terminal (D1) of ET (Ql), and the voltage control terminal (G4) is connected to the above PWM FET (
This opposite conductivity FET (Q1) is connected to the voltage control terminal (G1) of the PWM FE described above.
When T(Q1) turns on, it turns off, and the above PW
It has the function of turning on when the M FET (Q1) turns off, and the voltage drop across the opposite conductivity FET (G4) is smaller than the voltage drop across the diode, at least in such a circuit. Therefore, compared to the flywheel diode in the prior art, D
(-The power loss of the DC converter can be overwhelmingly reduced, which has a remarkable effect on improving the efficiency of the DC-DC converter, and at the same time, it is possible to simplify the heat dissipation means,
The device can be made smaller and lighter.

(b) PWM FET (Q1) which is a switching means
As an example, an input terminal (IN) is connected between the gate and source of
The collector is connected to the control terminal, the base is connected to one end of the output side of the main current limiting resistor (R), and the emitter is connected to the voltage control terminal (G1) of the PWM FET (Q1). The positive direction terminal is connected to the voltage control terminal (G1) of the discharge circuit transistor (G3) and the PWM FET (Q1), and the negative direction terminal is connected to the other main current terminal (C) of the control transistor (G2). Reverse bias diode (D2
) PWM FET shorting means (DC
), when the PWM FET (Q1) is turned off, the discharge circuit transistor (G3) constituting the PWM FET shorting means (DC) is connected, and the discharge circuit transistor (G3) is turned off. Turn on automatically and press P
The charge stored in the floating capacitance between the gate and source of the WM FET (Q1) can be discharged to a circuit with an extremely low resistance value.
A reverse current blocking diode (D3) is connected between the control transistor (N) and one input side terminal of the main current limiting resistor (R), with the positive side of the input terminal (IN) being the positive side. Diode (D3)
PWM FET short-circuiting means operation maintaining means (
HC), the capacitor (G3
), the above-mentioned discharge circuit is maintained for a sufficiently long period of time, the charge stored in the floating capacitance between the gate and source of the PWM FET (Ql) is sufficiently discharged, and these effects are synergistically In effect, the PWM FET
It becomes possible to increase the turn-off speed of (Q1).

(c) Since the value of the resistance (R) of the circuit through which the collector current of the control transistor (G2) flows can be selected to be large regardless of the above-mentioned discharge circuit, the loss generated in the DC-DC converter can be reduced; Therefore, the heat dissipation means can be simplified, and the device can be made smaller and lighter.

(d) Furthermore, since the turn-off speed can be increased, the switching frequency can be increased to a desired value, and the smoothing inductance and smoothing capacitor can be downsized.

[Brief explanation of the drawing]

FIG. 1a is a block diagram of a DC-DC converter according to a first embodiment of the present invention. FIG. 1b is a block diagram of a DC-DC converter according to a second embodiment of the present invention. FIG. 1C shows a PWM FET according to the second aspect of the present invention.
It is a diagram for explaining the operation of the short-circuiting means DC. FIG. 1d shows a PWM FET according to the third aspect of the present invention.
It is a diagram for explaining the operation of the short-circuiting means operation maintaining means HC. FIG. 2 is a block diagram of a DC-DC converter according to the prior art. E! ...Input voltage, Eo ...Output voltage, Q, ...PWM FET (P-channel field effect transistor), G2, DC, G3, D2, R, HC, C3, D3, SC, L,・ C2・ G4 ・ D, ・ ・ IN ・ ・ OUT ・ 0■ ・ ・ S, ・ ・ Dl ・ ・ GI ・ ・ ・Control transistor, ・PWM FET short circuit means, ・Discharge circuit transistor, ・Reverse bias Diode, resistor, ・PWM FET short-circuit means operation maintenance means, ・Capacitor, ・Backflow blocking diode, ・Smoothing circuit, ・Smoothing inductance, ・Smoothing capacitor, ・Opposite conductivity polarity FET (N-channel field effect transistor),・Flywheel diode, ・Input terminal, ・Output terminal, ・Ground potential, ・One current terminal of PWM FET, ・The other current terminal of PWM FET, ・Voltage control terminal of PWM FET, 1 S4 ・・One current terminal of the opposite conductivity polarity FET, D
4...The other current terminal of the opposite conductivity polarity FET, G4
・・・Voltage control terminal of opposite conductivity FET, ps...
・Current signal, E... One main current terminal of the control transistor, C.
...The other main current terminal of the control transistor, B...
Current control terminal for control transistor.

Claims (1)

[Claims] [1] One current terminal (S_1) is connected to the input terminal (IN), and the other current terminal (D_1) is connected to the smoothing circuit (SC).
), the voltage control terminal (G_1) operates in response to a current signal (PS) applied to the current control terminal (B), and one main current terminal (E)
is the control transistor (Q_
PWM connected to the other main current terminal (C) of 2)
one end is connected to the input terminal (IN), and the other end is connected to the other main current terminal (Q_2) of the control transistor (Q_2).
C) and the voltage control terminal (G) of the PWM FET (Q_1).
A voltage control terminal (G_4) is connected to _1), one current terminal (S_4) is set to ground potential, and the other current terminal (D_4) is connected to the other current terminal (D_1) of the PWM FET (Q_1). connected to the PWM FET (
A DC-DC converter comprising an FET (Q_4) having a conductive polarity that becomes non-conductive or conductive in response to conduction or non-conduction of Q_1). [2] The collector is connected to the input terminal (IN), the base is connected to one end of the output side of the control transistor main current limiting resistor (R), and the PWM FET (Q_1
), a discharge circuit transistor (Q_3) whose emitter is connected to the voltage control terminal (G_1) of the PWM FET (Q_1), and a positive direction terminal connected to the voltage control terminal (G_1) of the PWM FET (Q_1), and the control transistor It consists of a reverse bias diode (D_2) whose negative direction terminal is connected to the other main current terminal (C) of (Q_2), and the PW
A PWM FE that short-circuits the one current terminal (S_1) of the PWM FET (Q_1) and the voltage control terminal (G_1) at the same time that the M FET (Q_1) turns off.
Claim 1 characterized in that it has T-shorting means (DC).
The DC-DC converter described. [3] The collector is connected to the input terminal (IN), the base is connected to one output side end of the control transistor main current limiting resistor (R), and the PWM FET (Q_1
), a discharge circuit transistor (Q_3) whose emitter is connected to the voltage control terminal (G_1) of the PWM FET (Q_1), and a positive direction terminal connected to the voltage control terminal (G_1) of the PWM FET (Q_1), and the control transistor It consists of a reverse bias diode (D_2) whose negative direction terminal is connected to the other main current terminal (C) of (Q_2), and the PW
A PWM FE that short-circuits the one current terminal (S_1) of the PWM FET (Q_1) and the voltage control terminal (G_1) at the same time that the M FET (Q_1) turns off.
A T-shorting means (DC) is connected between the input terminal (IN) and one input side end of the control transistor main current limiting resistor (R) with the positive side of the input terminal (IN) being positive. a backflow blocking diode (D_3), and a negative side of the backflow blocking diode (D_3) and the PWM FET (Q
It consists of a capacitor (C_3) connected between the voltage control terminal (G_1) of the PWM FET (
The DC-DC according to claim 1, further comprising PWM FET shorting means operation maintaining means (HC) for maintaining the operation of the PWM FET shorting means (DC) during a period when Q_1) is off. converter.