JPH0223068Y2 - - Google Patents
Info
- Publication number
- JPH0223068Y2 JPH0223068Y2 JP1982127079U JP12707982U JPH0223068Y2 JP H0223068 Y2 JPH0223068 Y2 JP H0223068Y2 JP 1982127079 U JP1982127079 U JP 1982127079U JP 12707982 U JP12707982 U JP 12707982U JP H0223068 Y2 JPH0223068 Y2 JP H0223068Y2
- Authority
- JP
- Japan
- Prior art keywords
- charging
- secondary battery
- fet
- circuit
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007599 discharging Methods 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 1
Landscapes
- Stand-By Power Supply Arrangements (AREA)
Description
【考案の詳細な説明】
この考案は、簡単な回路構成で理想的な特性が
得られるようにした電子スイツチを用いた機器に
おけるバツクアツプ用バツテリの充電回路に関す
る。[Detailed Description of the Invention] This invention relates to a charging circuit for a backup battery in a device using an electronic switch, which allows ideal characteristics to be obtained with a simple circuit configuration.
第１図は従来の充放電回路の簡単な回路構成の
場合の一例を示す回路図である。この第１図にお
いて、図示しない電源は逆流阻止用のダイオード
Ｄ１を介して負荷Ｌに接続されているとともに、
ダイオートＤ１のカソード側は抵抗Ｒ１とダイオ
ードＤ２との並列回路を介して２次電池Ｂの正極
に接続されている。 FIG. 1 is a circuit diagram showing an example of a simple circuit configuration of a conventional charging/discharging circuit. In FIG. 1, a power supply (not shown) is connected to a load L via a backflow blocking diode D1, and
The cathode side of the diode D1 is connected to the positive electrode of the secondary battery B via a parallel circuit of a resistor R1 and a diode D2.
この２次電池Ｂを充電する場合には、電源から
ダイオードＤ１抵抗Ｒ１を通して微小電流が２次
電池Ｂに流れ、この２次電池Ｂを充電する。この
ため充電時には抵抗Ｒ１を通して充電電流を流す
ので、ダイオードＤ１のアノードに加える電圧に
よつて充電電流が変動してしまう。 When charging this secondary battery B, a minute current flows from the power source to the secondary battery B through the diode D1 and the resistor R1, and this secondary battery B is charged. Therefore, during charging, a charging current is passed through the resistor R1, so that the charging current varies depending on the voltage applied to the anode of the diode D1.
また、２次電池Ｂの放電時には、２次電池Ｂよ
りダイオードＤ２を通して低インピーダンスで負
荷Ｌへ放電する。しかし、この場合、ダイオード
Ｄ２にはVFなる順方向電圧降下が常に存在する
ため、２次電池Ｂの電圧VBは必要とする電圧Ｖ
よりVFだけ高い必要がある。（即ち、VB＝Ｖ＋
VF）。 Furthermore, when the secondary battery B is discharged, the secondary battery B discharges to the load L with low impedance through the diode D2. However, in this case, since there is always a forward voltage drop V F in diode D2, the voltage V B of secondary battery B is equal to the required voltage V
It needs to be higher by V F than that. (i.e., V B =V+
VF ).
この考案は、上記の点に鑑みてなされたもの
で、電源と２次電池との間にFET（電界効果トラ
ンジスタ）を接続することにより、２次電池にと
つて理想的な充電状態を得るとともに、充電時の
ロスを最少にすることのできる充放電回路を提供
することを目的とする。 This idea was made in view of the above points, and by connecting an FET (field effect transistor) between the power supply and the secondary battery, it is possible to obtain the ideal state of charge for the secondary battery. An object of the present invention is to provide a charging/discharging circuit that can minimize loss during charging.
以下、この考案の充放電回路の実施例について
図面に基づき説明する。 Hereinafter, embodiments of the charging/discharging circuit of this invention will be described based on the drawings.
第２図はその一実施例の構成を示す。この第２
図において、第１図と同一部分には同一符号を付
してその説明を省略し、第２図とは異なる部分の
みについて述べる。 FIG. 2 shows the configuration of one embodiment. This second
In the figure, parts that are the same as those in FIG. 1 are given the same reference numerals, and their explanation will be omitted, and only the parts that are different from FIG. 2 will be described.
この第２図を第１図と比較しても明らかなよう
に、第２図では、第１図における抵抗Ｒ１とダイ
オートＤ２の並列回路に変えてFETQ１が接続さ
れている。即ち、FETQ１のドレインをダイオー
トＤ１のカソードと負荷Ｌに接続し、FETQ１の
ゲートとソースを接続して２次電池Ｂの正極に接
続されている。その他の構成は第１図と同様であ
る。 As is clear from comparing FIG. 2 with FIG. 1, in FIG. 2, FET Q1 is connected instead of the parallel circuit of resistor R1 and diode D2 in FIG. 1. That is, the drain of FETQ1 is connected to the cathode of diode D1 and the load L, and the gate and source of FETQ1 are connected to the positive electrode of secondary battery B. The other configurations are the same as in FIG. 1.
このような回路構成とすることにより、FETQ
１のソースドレイン電圧対ドレイン電流の特性は
第３図のようになる、この第３図において、実線
ａの特性は電源から２次電池Ｂに流れる充電電流
を示し、破線ｂは２次電池Ｂの放電時の放電電流
を示す。この放電電流はFETQ１のソース・ドレ
イン間の抵抗によつて決まる逆方向のインピーダ
ンスにより電流が小さくなつていることを示す。 With this circuit configuration, FETQ
The characteristics of the source-drain voltage versus drain current of No. 1 are shown in Figure 3. In Figure 3, the solid line a indicates the charging current flowing from the power supply to the secondary battery B, and the broken line b represents the charging current flowing from the power source to the secondary battery B. This shows the discharge current during discharge. This discharge current indicates that the current is reduced due to the reverse impedance determined by the resistance between the source and drain of FETQ1.
このように、２次電池Ｂに充電するには、
FETQ１のドレイン・ソース間の抵抗が∞とな
り、充電電流は放電電流より高く、第３図のよう
に定電流特性を示すので、充電時には定電流源と
なり、理想的な充電を行うことができる。 In this way, to charge secondary battery B,
The resistance between the drain and source of FETQ1 is ∞, the charging current is higher than the discharging current, and it exhibits constant current characteristics as shown in Figure 3, so it becomes a constant current source during charging and can perform ideal charging.
以上のように、この考案の充放電回路によれ
ば、電源側に逆流阻止手段を介して負荷とFET
のドレインを接続し、２次電池側にFETのソー
スとゲートを接続することにより、充電時に定電
流源となるようにして電源より２次電池に充電電
流を流すようにしたので、理想的な充電を行うこ
とができる。 As described above, according to the charge/discharge circuit of this invention, the load and FET are connected to the power supply side via the reverse current blocking means.
By connecting the drain of the FET and connecting the source and gate of the FET to the secondary battery side, it becomes a constant current source during charging, allowing charging current to flow from the power supply to the secondary battery, making it ideal. Can be charged.
又、放電時には、FETのドレイン・ソース間
の抵抗による電圧の低下で放電するので、ほとん
ど損失のない状態で放電を行うことができる。 Further, during discharging, the discharge occurs due to a voltage drop due to the resistance between the drain and source of the FET, so discharging can be performed with almost no loss.
従つて、理想的なバツテリバツクアツプを極く
簡単な回路で実現できるものである。 Therefore, an ideal battery backup can be realized with an extremely simple circuit.
第１図は従来の充放電回路の回路図、第２図は
この考案の充放電回路の一実施例の回路図、第３
図はこの考案の充放電回路におけるFETのソー
ス・ドレイン電圧対ドレイン電流の特性を示す図
である。
Ｄ１……ダイオート、Ｌ……負荷、Ｂ……２次
電池、Ｑ１……FET。
Figure 1 is a circuit diagram of a conventional charging/discharging circuit, Figure 2 is a circuit diagram of an embodiment of the charging/discharging circuit of this invention, and Figure 3 is a circuit diagram of an embodiment of the charging/discharging circuit of this invention.
The figure shows the characteristics of the source-drain voltage versus drain current of the FET in the charge-discharge circuit of this invention. D1...Diauto, L...Load, B...Secondary battery, Q1...FET.
Claims (1)
に接続するとともに負荷に接続し、このFETの
ゲートとソースを２次電池の正極に接続してなる
充放電回路。 A charging/discharging circuit in which the drain of the FET is connected to the power supply via a reverse current blocking means and to the load, and the gate and source of this FET are connected to the positive electrode of a secondary battery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12707982U JPS5930643U (en) | 1982-08-23 | 1982-08-23 | charge/discharge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12707982U JPS5930643U (en) | 1982-08-23 | 1982-08-23 | charge/discharge circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5930643U JPS5930643U (en) | 1984-02-25 |
| JPH0223068Y2 true JPH0223068Y2 (en) | 1990-06-22 |
Family
ID=30288745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12707982U Granted JPS5930643U (en) | 1982-08-23 | 1982-08-23 | charge/discharge circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5930643U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19645944A1 (en) * | 1996-11-07 | 1998-05-14 | Bosch Gmbh Robert | Control unit for an electrical system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5723123A (en) * | 1980-07-16 | 1982-02-06 | Fujitsu Ltd | Semiconductor device having volatile memory |
-
1982
- 1982-08-23 JP JP12707982U patent/JPS5930643U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5723123A (en) * | 1980-07-16 | 1982-02-06 | Fujitsu Ltd | Semiconductor device having volatile memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5930643U (en) | 1984-02-25 |
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