JPH03248076A - Cfar circuit - Google Patents

Abstract

PURPOSE:To achieve a higher freedom by controlling the number of averaging cells and guard cells in substance by an external control with a simple circuit. CONSTITUTION:First, selectors 32c and 31c output zeroes under control of a Constant False Alarm Rate (CFAR) control circuit 35 and data a0, a1... and aM are supplied to a terminal I of an adder 30. The data are added up and an initial value A(0)=a0+a1+...+aM is taken out at a terminal II to be stored into RAMs 32a and 31a. When the data A(0) arrives at the terminal I, a data aM+1 at the terminal II and a data a0 at the terminal III, a sector 30d selects the data arriving at the terminal II under control of the circuit 35. On the other hand, a selector 30e selects the data arriving at the terminal I under control of the circuit 35 and a selector 20f performs an adding operation in which no output of an adder 30c is selected and a subtracting operation of the selectors 30d and 30f at different timings using only one adder 30c.

Description

[Detailed Description of the Invention] [Summary] CF for detecting only targets with a low probability of false alarm while keeping the false alarm probability constant for signals obtained from pulse radar
AR (Constant False Alars)
Regarding the ate) circuit, the purpose is to increase the degree of freedom of control by substantially controlling the number of averaging cells and guard cells externally with a simple circuit configuration, and to substantially control the number of averaging cells and guard cells by externally. A first data delay section that outputs a delayed signal by the number (M) of averaging cells adds the input data and the immediately preceding output data, and subtracts the output data of the first data delay section. an adder that substantially obtains the sum data of one averaging cell; a data holding section that holds the immediately preceding output data; and an adder that sequentially stores the output data of the data holding section and substantially averages the other averaging cell. a data storage unit that obtains data of the sum of the cells; and a second data delay unit that substantially delays the output data of the first data delay unit by the number (L) of guard cells to obtain substantially the output data of the test cell. and a control means for arbitrarily variably controlling the above-mentioned M and L.

[Industrial application field]

The present invention relates to a CFAR circuit (IJ, hereinafter referred to as CFAR) for detecting only a target with a low probability of false alarm while keeping the false alarm probability of a signal obtained from a pulse radar constant.

A pulse radar emits a pulse as shown in FIG. 4, for example, and determines the position of a target by receiving the reflected wave. Here, the radar signal from pulse radar 1 is MT I (
Moving Target Indicator)
2, the zero doara signal (echo from a target moving in the vertical direction or echo from the ground) is canceled and becomes a non-zero doaara signal, which is an echo from a target moving in a direction other than the vertical direction. FFT (
Fast Fourier 1transfor meal) Fourier transform is performed by Doppler filter 3 and the frequency FO"F
It is divided into N parts, taken out, and supplied to CFAR4o to 4N. CFAR4o to 4N are equipped with HfB and are used to detect the target from among many reflected waves from targets, mountains, clouds, rain, forests, etc.
The target is determined by the target determining circuit 5 based on the detection results of R4o to 4N, and the target is tracked by the target tracking device 6. The CFAR used in such a system generally has a configuration combining a shift register and a large number of adders, as will be described later, but it is desirable to have a simple circuit configuration.

[Conventional technology]

For example, if reflected waves from clouds and targets are obtained as radar signals as shown in Fig. 5, CFAR4o
In ~4N, in order to detect only the target, a threshold value called a threshold is reset one after another according to the incoming reflected waves, and if the reflected wave level is above the threshold value, this is the target, and if it is below the threshold value, this is the clutter. , regarded as noise (interfering signals other than the target). In other words, CFAR is the false alarm probability (probability of doing the opposite to the above) Pfa
This is to find a threshold value with constant.

CFAR is, for example, r T NTR0[1UCTION
TORADAflSYSTEMS) (Mc GRA
W-HILL BOOK COMPANY, 1961)
P, 392-395.

Figure 6 shows an example of a conventional CFAR (Loo-Ce11A
FIG.

The figure shows CFAR in one frequency bank.

As shown in the figure, CFAR roughly consists of a log conversion circuit 9,
Shift register group 10. Arithmetic unit 11. Comparator 12
It is composed of. The shift register section 10 is composed of M averaging cells 13+, 132, and a test cell 14, including the averaging cells 13+, 13z and the test cell 1.
4 are guard cells 19+ and 192. Here, when radar signals as shown in FIG. 5 enter the shift register unit 10 in time series, the averaging cell 131°1
32 outputs are added by adders 151 and 152, inputs A and B are selected by selector 16, averaged by averaging circuit 17, and output of averaging circuit 17 is added from the output of test cell 14 by subtracter 18. It is subtracted and compared by the comparator 12 with the identification value T determined by the false alarm probability pta.

For example, for a reflected wave that has a gentle level change in the direction of the distance MR (R+, Rz, . . . is the minimum unit of distance R, and is called a range bin) like a party, the output level of the test cell 14 in the range bin RT+ By comparing the calculation result with the average value of the output level of the averaging cell 131, 132 before and after the range bin R1 and the fixed value T, the cloud level becomes substantially less than the threshold level T1, as shown in FIG. . On the other hand, for a reflected wave that has a sharp level change in the direction of distance R, such as a target, the output level of the test cell 14 in the range bin Rw+ and the averaging cell 13+ in the front and back of the range bin R1,
By comparing the calculation result with the average value of the output levels of 132 and the fixed value T, the target level becomes substantially equal to or higher than the threshold level 1, as shown in FIG. In this way CFA
The results of the level comparisons in R4o to 4N are supplied to the target determination circuit 5, where reflected waves having a threshold level or higher are determined to be targets, and the target tracking device i6 tracks the target.

The addition operation of the conventional CFAR in FIG. 6 will be explained. The data to be judged (tested) sequentially enters the shift register unit 10, and from L pieces after the data to be judged (data in the test cell 14) currently, the data A of the saw machine, Data B from L pieces before (L+M) pieces
Find the average value of the noise from . Here, a-1-H'''a-[-1,84~a-1,ao, a
It is assumed that data from + to aL-8141 to 814M is stored in the shift register section 10. Here, a-t
□~a-L-1 is data of averaged cell 13+, a-L
"' a-1 is the data of the guard cell 191, ao is the data of the test cell 14, a1 to a are the guard cell 192
data, a[+1 to a[+H averaging cell 132 data. Therefore, the output A of adder 151, adder 15
The output B of 2 is A=Σ a-L-1 m=1 B=Σ a[+.

It is l. The selector 16 controls a control circuit (not shown) to select from three modes: ■ Max (A, B) = Cm = M, ■ Min (A, B) = Cm = M, ■ A + B = Cm = 2M. ), but generally mode ① is selected. In the present invention, modes (1) and (2) are not particularly relevant, so their explanation will be omitted. Selector 1 shown in Figure 6
The average value of the noise is obtained by multiplying the output of No. 6 by C in the averaging circuit 17.

Therefore, from the belief @ao to be determined, the false alarm probability Pf
Subtract the fixed values T and M determined by a (aO-T-M)
, if this is greater than or equal to z, it is determined that there is a signal, and if it is less than zero, it is determined that there is no signal. Such operations are sequentially performed while flowing data to the shift register section 10.

(Problem to be Solved by the Invention) The conventional circuit shown in FIG. 6 is actually configured with a large number of adders 20+, 202, . . . as shown in FIG. 7, and averaging cells 13+, 132, etc. The number M increases in proportion to the number M, and there is a problem that the scale of the hardware increases.Also, in order to detect targets more optimally in environments where targets and clutter occur, it is necessary to increase the length of the shift register section. Although it is necessary to set them optimally, in the conventional example, the lengths (M and L) of the averaging cells 131, 132 and guard cells 191, 192 of the shift register section 10 are fixed,
Also, there is a limit to its length, so i, 1JIl
] The problem was that there was little freedom. Furthermore, the averaging cell 131.132 and the guard cell 19+, M of 192,
When the value of L is changed and used, there is a problem that some adders are not used, and the circuit is wasted.

An object of the present invention is to provide a CFAR that has a simple circuit configuration and can substantially control the number of averaging cells and guard cells externally 11111 to increase the degree of freedom of control.

(Means for solving one problem) FIG. 1 shows a diagram of the principle of the present invention. In the figure, reference numeral 40 denotes a first data delay unit, which delays input data substantially by the number (M) of averaging cells on one side and outputs the delayed data. 41 is an adder,
Add the input data and the output data immediately before it, and
The output data of the first data delay unit 40 is subtracted to obtain data (A) that is substantially the sum of one averaging cell. A data holding unit 42 holds the immediately previous output data of the adder 41. Reference numeral 43 denotes a data storage section which sequentially stores the output data of the data holding section 42 to obtain data (B) which is essentially the sum of the other averaging cells. 44 is a second data delay section;
The output data of the first data delay unit 40 is delayed by substantially the number (L) of guard cells to obtain substantially the output data of the test cell.

45 is a control means M of the first data delay section 4o.

L of the second data delay section 44 is arbitrarily variably controlled. In the present invention, in the adder 41, aOra+, a2 .
・The input data that comes in in the order of ``H+1'', aM, a, aH, 2 is Δ(0)=ao+a.

+-+aM,A (1)=a+ +a2+-+aH,1
゜A(2)=82+83+-+a,-+7)ll
Ii[” outputs the 482nd order and essentially outputs the data of the sum of one averaging cell (A
).

[Effect]

The adder 41 calculates data that is substantially the sum of one averaging cell, the data storage 43 substantially obtains the data that is the sum of the other averaging cell, and the data is sent to the second data delay unit 44. to essentially obtain the output data of the test cell. In this way, it is not necessary to configure a combination of shift registers and a large number of adders as in the past, and the hardware scale can be reduced.

Furthermore, since the values of M and L can be varied by the 1lJal1 means 45, optimal target detection can be performed in accordance with the target and clutter generation environment, and control freedom can be increased.

(Embodiment) Fig. 2 shows a block diagram of an embodiment of the present invention, in which the same components as in Fig. 6 are given the same numbers.In Fig. 2, 30 is an adder, for example The configuration is shown in FIG. 3(A) or (B). 31 is a delay circuit, and RAM 31a
, 31b and a selector 31C, it substantially obtains a delay of M averaging cells and supplies it to the adder 30, while substantially obtains the output signal of the test cell and supplies it to the subtracter 1.
8. 32 is a delay circuit, RAM3
It is composed of 2a, 32b and a selector 32c,
As described later, zero is first supplied to the adder 30, and then adders A(0) (initial value), A(1), A(2), etc.
is supplied to the adder 30, while the adder B is obtained. Adder 30. The delay circuits 31 and 32 are substantially the same as the shift register section 10.32 shown in FIG. It has the same function as adders 151 and 152. 33 is a selector circuit,
It is composed of an adder 33a, a comparator 33b, and a selector 33C, and has substantially the same function as the selector 16 shown in FIG. Reference numeral 34 denotes an averaging circuit, which is composed of a multiplier 34a and a RAM 34b, and has substantially the same function as the averaging circuit 17 shown in FIG. 35 is a 111E1 circuit, as described later, RA
M31a.

31 b, 32a, 32b, 34b, selector 31c,
32c, 33c, and comparator 33b, respectively.

Here, adder 30. Delay circuits 31 and 32 essentially determine the sum (A+B) of the outputs of the two averaging cells.

for example, a,,,an-1,·,a,,am-1,·,a,.

Assume that data aO→ is sequentially output from the log conversion circuit 9 and sequentially supplied to the adder 30 and the delay circuit 31 in the direction of the arrow. Here, it is assumed that aO is not particularly related to the data aO of the test cell 14 explained in FIG. 6 above. First, the selector 32C131c outputs zero under the control of the control circuit 35, and thereby the data ao, al, . . .
M is supplied and added, taken out from the terminal and stored in RAM32a, 31a initially (IIA(0)=ao+a
1+...+8M are stored. In this case, Fig. 3 (A
), the adder 30a performs an addition operation, and the added value is taken out by directly passing through the subtracter 30b.

Next, when data a, +1 is supplied to the adder 30, 1
1 control circuit 35 selector 32cLtR
The RAM 31 a is switched to output the initial value A(0) stored in the AM 32 a, and at the same time, under timing control from the control circuit 35, the RAM 31 a outputs data aa among the data stored therein. Further, the selector 31c is switched to output data aO from the RAM 31a. As a result, as shown in FIG. 3(A), data A(0)=a is input to terminal A of the adder 30a.
data aH+1 is supplied to one terminal A of M, and data a0 is supplied to one terminal of subtractor 30b.
Data A(1) is obtained from the terminal by subtraction in ” a
l + 82+”'+ aH,1 is obtained and RAM3
Data A(1) is stored in 2a.

Similarly, when data aH+2 is next supplied to the adder 30, the selector 32C selects the data A(
1), and at the same time, under timing control from the error control circuit 35, the RAM 31 a
outputs data a1 out of the data sequentially stored here, and selector 31c outputs output data a1 of RAM 31a. As a result, data A(1)=a++a2+・+a is supplied to terminal A of the adder 30a, data a is supplied to terminal H+1A, and data 42a is supplied to terminal one of the subtracter 30b, and data is supplied from the terminal operator. A(2)=a
2 +83+...+8842 is obtained. By repeating such operations, the adder 30 outputs A(0)=a
o +a+ +---+aMA(1) -a+ +az
+-+aH,IA(2) ” Eli + a2 +
”+aH+2 data is output. Therefore, the algorithm is: (i) Find (0) as the initial value, (ii) Next, A(n) = A (n-1) + a-a
Find (n-1).

This algorithm essentially calculates the sum of the averaged cells on the H side.

Returning to FIG. 2, the data output from terminal 1 of the adder 30 (substantially the data A explained in FIG. 6)
is stored in the RAM 32a and then supplied to the RAM 32b, thereby substantially obtaining the data B described in FIG. 6 from the RAM 32b. On the other hand, at timing 1fjtll from the control circuit 35, the RAM 31b outputs data that substantially corresponds to the output of the test cell 14 explained in FIG. 6 among the data stored therein.

In this way, adder 30. The operations of the delay circuits 31 and 32 are substantially the same as those of the shift register section 10 and the adders 151 and 152 shown in FIG. Multiple adders 20I as shown.

202,... can be omitted, and the simple Bardo (
M+n) Can be configured with 1a.

Addition data A output from adder 30 and RAM 32
The added data B output from the adder 33a is added by the adder 33a, and as mentioned above, in the present invention, only the mode ①, that is, the case of data (A+B), is added, so the control circuit 35
Also, the selector 33c selects the output of the adder 33a.

The data (A+B) is multiplied by the coefficient set in the RAM 34b in the multiplier 34a of the averaging circuit 34, that is, the C7 coefficient is calculated. The output of the averaging circuit 34 and R
AM31b output (essentially test cell output data)
is supplied to the subtracter 18, and after that, the comparator 12 obtains a combination of signal presence and signal absence by the operation exactly the same as that explained in FIG.

In the present invention, R is controlled by the timing control of the control circuit 35.
Predetermined data among the data stored in the AMs 31a and 31b can be output, that is, the delay time substantially corresponding to the number M of averaging cells and the number of guard cells can be appropriately set. Therefore, when performing target detection more optimally in an environment where clutter or the like occurs, the lengths (M and M) of the averaging cell and the guard cell can be varied, so that the lengths are fixed and The degree of freedom in control is increased compared to the conventional example, which had a limit on its length, and there is no need for wasted circuitry as in the conventional example.

In this case, in FIG. 5, if there are, for example, two targets at different locations in the range bin R+ + R2m... in one frequency bank, one target to be determined enters the test cell 14, while the other target may enter the averaging cell.

In this case, one target to be determined is affected by the other target, and the threshold level of the target to be determined becomes higher than necessary, and the target to be determined may not be detected correctly. In such a case, in the present invention, it is detected that the predicted position data of the other target obtained by the target tracking device corresponds to the averaging cell, and the corresponding cell in the averaging cells is detected based on this predicted position data. is set to a blank state so that this corresponding cell is not added.

As a result, the threshold level of the target to be determined is lowered, and the target to be determined can be reliably detected.

In the present invention, it is possible to virtually designate a cell to be ranked among the averaging cells by controlling lllllj times 135, so that even when two targets exist, targets can be detected without any problem.

Note that the adder 30 shown in FIG. 2 may have the configuration shown in FIG. 3(B). Similar to the embodiment shown in FIG. 3(A),
Data A (0) to terminal A, data a to terminal A, data a to one terminal. The case where H◆1 is present will be explained. Selector 30d is vIII
The selector 30e selects the data coming into terminal A from the road side 35 from the road side 5, while the selector 30e selects the data coming into terminal A under control from the control circuit 35, and
The selector 30f does not select the output of the adder 30c. As a result, data A (
0) and data aH+1 are added. In other words, ao+
8++...+aM+aH41. Next, the selector 30d selects the output data of the sign inverter 30a, the selector 30e selects the output data of the selector 30f, and the selector 30f selects the output data of the adder 30C. As a result, the data (a
o +8+ +-+aM+aH+1 ) to data aO
is subtracted, and data A (1) is sent via selector 30f.
= a+ + 82 + ・” + aH,1 is extracted. In other words, the circuit shown in FIG. 3(B) performs the addition and subtraction operations of the circuit shown in FIG. 3(A) at separate timings. This is performed by the adder 30C, and the addition and subtraction operations are performed at 1/2 each of the circuit operations shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, a circuit can be configured without using shift registers or a large number of adders as in the conventional example, and simple hardware is required.

In addition, the number of averaging cells and guard cells can be varied.
1W, it is possible to detect the optimum target according to the environment in which targets and clutter occur, and the degree of freedom in control can be increased compared to the conventional example.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a specific configuration diagram of an adder, and FIG. 4 is a diagram explaining a general target tracking system. Figure 5 is C
A diagram explaining the general operation of FAR, Figure 6 is a diagram explaining the general operation of FAR.
FIG. 7, which is a block diagram of an example of the FAR, is a specific block diagram of a part of the circuit shown in FIG. In the figure, 9 is a log conversion circuit, 12 is a comparator, 13+, 132 are averaging cells, 14 are test cells, 15+, 15z, 20+, 202 adders, 18 in the conventional example is a reducer, 19+, 192 is a guard cell, 30.30a, 30c, 33a are adders, 30b is a subtracter, 30d to 30f, 31c, 32c, 33c are selectors, 300 is a sign inverter, 31.32 is a delay circuit, 31a, 31b, 32a , 32b, 34b are RA1; 34 is an averaging circuit; 348 is a multiplier; 35 is a control circuit; 40 is a first data delay section; 41 is an adder; 42 is a data holding section; 43 is a data storage section; The second data delay section 45 indicates υ38 means. A diagram of the principles of the present invention.A diagram to explain a general target tracking system.A diagram to explain the general operation of a CFAR.A diagram of the configuration of an example of a conventional CFAR.

Claims (1)

[Scope of Claims] A first data delay unit (40) that delays input data substantially by the number (M) of averaging cells on one side and outputs the same; an adder (41) that adds and subtracts the output data of the first data delay section (40) to obtain substantially the sum data (A) of one averaging cell; 41), and a data holding unit (42) that holds the immediately previous output data; and a data holding unit (42) that sequentially stores the output data of the data holding unit (42) and substantially stores the data (B) of the sum of the other averaging cell. a data storage unit (43) to obtain data, and second data to substantially obtain output data of the test cell by substantially delaying the output data of the first data delay unit (40) by the number (L) of guard cells. a delay section (44), a control means for arbitrarily variably controlling M of the first data delay section (40) and L of the second data delay section (44);
45), and in the adder (41), a_0, a_1, a_2
..., the input data coming in in the order of a_M, a_M_+_1, a_M_+_2, A(0)=a_0+a_
1+...+a_M, A(1)=a_1+a_2+...
・+a_M_+_1, A(2)=a_2+a_3+...
- A CFAR circuit characterized in that it is configured to sequentially output data (A) of the sum of one averaging cell by sequentially outputting data (A) in the order of +a_M_+_2, .