JPH03247122A - Variable quantizer and video/picture encoder - Google Patents

Abstract

PURPOSE:To realize high speed processing with the addition of a simple circuit by providing a function converting a negative number into a positive number to a fixed quantizer in a variable quantizer receiving a data in 2's complement expression. CONSTITUTION:A signal transformed by a discrete cosine transformation device 103 for every block is inputted to a fixed quantizer A202, a fixed quantizer B203 and a delay buffer 205 through an input 201. A signal inputted from the input 201 is expressed in 12-bit 2's complement notation. The signal is quantized by the fixed quantizer A202 in a step size of 8. The signal is quantized by the fixed quantizer B203 in a step size of 32. The result of quantization of the fixed quantizers A202, B203 is inputted to a quantization decision device 204, rearranged in a block, subjected zigzag scanning and the code generation quantity in the case of Huffman coding is obtained from a Huffman code quantity table 211.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal or image signal encoder and a quantizer used therein.

[Prior art] In conventional variable quantizers, the output of the variable quantization step quantizer is variable-length encoded to obtain the amount of generated code, and the quantization step is controlled according to the result. . The control method is D-4 of the 1989 Institute of Electronics, Information and Communication Engineers Autumn National Conference.
5, the output of the quantizer with variable quantization step is variable-length coded to obtain the generated code amount, which is repeated 2-3 times, and the quantization step is controlled according to the result. Ta.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, due to the delay time caused by repeating 2-3 times of variable-length encoding the output of the variable quantization step quantizer to obtain the generated code amount. , which has the problem of not being able to perform high-speed processing. The present invention is intended to solve these problems, and its purpose is to realize high-speed processing by adding a simple circuit.

[Means for Solving the Problems] (1) The variable quantizer of the present invention includes at least one quantization step variable quantizer, at least two fixed quantizers, and a quantizer from the output of the fixed quantizer. The variable quantizer has a quantization decider that controls the quantization step of the variable step quantizer, and inputs data expressed in two's complement. It is characterized by having a conversion function.

(2) The variable quantizer of the present invention sets the quantization steps of the at least two fixed quantizers described in (1) to different values by a power of 2, so that the lower bits of the input data are It is characterized by being realized by throwing it away.

(3) The video/image encoder of the present invention is characterized by having the variable quantizer described in (1) or (2).

[Embodiment 1] FIG. 1 shows a variable quantizer 104 of the present invention in a CCITT, 5
It is a block diagram when applied to a px64 kbPs (p=1-30) video encoder (H, 261 CODEC) for TV telephone/conference, which is being standardized in GXV (transmission system and device).

The signal flow in diagram N1 will be explained below. Video signal is CIF
(common intermediate format), and is divided into macroblocks consisting of 8 lines x 8 pixel blocks, 4 blocks of luminance signals, and 2 blocks of color difference signals, a total of 6 blocks. Prediction is usually done between frames, so
Encoding control 102 connects switch 109 and switch 110 to the lower side as shown in FIG.

A video signal is input from a video signal input 101 for each macroblock. First, it is input to the motion compensation predictor 107, which selects the signal of the macroblock with the minimum prediction error from the already recorded signal one frame before (motion vector detection), and outputs the signal of that macroblock. . After this signal passes through a loop filter 108, the difference between it and the video input signal is taken. The difference signal between this video input signal and the macroblock indicated by the motion vector of one frame before is converted by a discrete cosine transformer 103 for each block. Then, the variable quantizer 104 performs quantization and Huffman encoding, and the encoded result 112 is output. The quantization characteristic of the variable quantizer 104 is adaptively set to match the transmission rate of the transmission path. This method will be described in detail in the description of FIG. The quantized signal is dequantized by an inverse quantizer 105 and subjected to inverse discrete cosine transform by an inverse discrete cosine transformer 106, and then the signal of the block indicated by the motion vector is converted into a signal passed through a loop filter 108. The sum is added and recorded in the motion compensation predictor 107. on the other hand,
At the first frame or at a scene change, prediction is performed within the frame, so the switches 109 and 110 are connected to the upper side by the encoding control 102. That is, the signal inputted from the video signal input 101 is directly converted by the discrete cosine transformer 103. and,
The signal is quantized by a variable quantizer 104 and further subjected to Huffman encoding, and is output as an encoding result 112. The quantized signal is dequantized by an inverse quantizer 105, subjected to inverse discrete cosine transform by an inverse discrete cosine transformer 106, and then recorded in a motion compensation predictor 107.

FIG. 2 is a diagram showing details of the variable quantizer (variable quantizer 104 in FIG. 1) of the present invention.

First, the characteristics of this variable quantizer will be explained.

A discrete cosine transformed signal is input for each block,
After being quantized and zigzag scanned in the numerical order (1-64) in FIG. 5, it is Huffman encoded. Figure 4 1
The th value corresponds to the DC component of the block signal before discrete cosine transformation, so it is subjected to fixed quantization in quantization step 8. The 2nd to 64th values correspond to the AC components of the block signal before the discrete cosine transform, so the quantization step is an even value between 2 and 62, and is variable for each macroblock. Control to match the transmission rate. The characteristics of this variable quantizer are as shown in FIG. 6, taking into account the dead zone. To determine the optimal quantization step with a variable quantizer, first quantize with two quantization steps, measure the amount of generated code, and then use the constant a from Equation 1.
, find b.

(Generated code IF) = ax log (1 quantization step size) + b: Equation 1 Then, the optimum quantization step size is determined from the generated code amount that matches the transmission path.

The signal flow in FIG. 2 will be explained below. The signal transformed by the discrete cosine transformer 103 (Fig. 1) for each block is
The signal is input through an input 201 to a fixed quantizer A202, a fixed quantizer B2O3, and a delay buffer 205.

The signal input from the input 201 is expressed as a 12-bit two's complement number. The fixed quantizer A202 performs quantization with a step size of 8. This is QUANT=
It corresponds to 4. The fixed quantizer B2O3 performs quantization with a step size of 32. This is QUANT in Figure 6
=16. The quantization results of the fixed quantizer A202 and the fixed quantizer B2O3 are input to the quantization determiner 204, rearranged within the block, and zigzag scanned, respectively, as shown in FIG. Then, using the 2nd to 64th values in FIG. 5, the amount of codes generated during Huffman encoding is determined from the Huffman code amount table 211. The Huffman code amount table 211 is designed so that the generated code amount after Huffman encoding is determined by the absolute value of the input data, and the generated code amount does not depend on the code of the input data. This operation is performed for six blocks in the macroblock, and constants a and b are obtained from Equation 1. The optimum quantization step size is then determined by specifying the amount of generated code that matches the transmission path. This is outputted from the quantization index 208 and also outputted as the quantization step size 212 to the variable quantizer C206. After one macroblock is written, the signal input to the delay buffer 205 waits for the quantization step size 212 to be input to the variable quantizer 0206, and then input to the variable quantizer 0206. The variable quantizer 0206 quantizes the first data in FIG. 5 with a quantization step size of 8, and quantizes the second to 64th data in FIG. 5 with a quantization step size of 212. The quantization result is
The signal is output to the Huffman encoder 214, and is returned to line-by-line scanning and output from the output 209 to the inverse quantizer. In the Huffman encoder 214, the first data in FIG. 5 is passed through as is, and the second to 64th data in FIG. 5 are Huffman encoded and output as the encoding result 207.

FIG. 3 is a diagram showing the configuration of the fixed quantizer A202 of the present invention. The input data 301 is expressed as a 12-bit two's complement number, and if the input data 301 is positive, (MSB
=O), 1 is added to obtain 12 and set data 302.

The reason why 1 is added is to match the quantization characteristics shown in FIG. If the input data 301 is negative (MSB=1
), input data 301 is inverted bit by bit and 2 is added to it to obtain 12-bit data 302. 6 The reason why 2 is added to the inverted data is to add 1 and change the sign of negative input data 301. This is for inverting and also for adding 1 to match the quantization characteristics shown in FIG. Next, the 12-bit data 302 is divided into three bits on the LSB side and two upper bits on the MSB side.
In terms of bits, it is assumed to be 8-bit data 303 as shown in FIG. This is because the quantization step size is 8, so LS
It is shown that a quantizer can be constructed by discarding the 3 bits on the B side. The MSB of the 8-bit data 303 is set to 0 because the sign bit has no meaning in this system.

FIG. 4 is a diagram showing the configuration of the fixed quantizer B2O3 of the present invention. The input data 401 is expressed as a 12-bit two's complement number, and if the input data 401 is positive, (MSB
=O) and 1 is added to obtain 12-bit data 402.

The reason why 1 is added is to match the quantization characteristics shown in FIG. If the input data 401 is negative (MSB=1
), input data 401 is inverted bit by bit, and 2 is added to obtain 12-bit data 402. The reason why 2 is added to the inverted data is to invert the sign of the negative input data 401 by adding 1, and to match the quantization characteristics shown in FIG. 6 by adding 1. Next, the 12-bit data 402 is converted into 8-bit data 403 as shown in FIG. 4, ignoring the 5 bits on the LSB side and the 1 bit on the MSB side. This is because the quantization step size is 32, so L
It is shown that a quantizer can be constructed by discarding 5 bits on the SB side. MSB side 2 of 8-bit data 403
The reason why the bit is set to O is because the sign bit has no meaning in this method.

Note that the circuit for input data 301 to 12 bit data 302 in FIG. 3 and the input data 401 to 12 bit data in FIG.
Since the circuits up to bit data 402 have the same configuration, they can be shared.

[Embodiment 2] The configuration of the variable quantizer 104 in the video encoder (FIG. 1) of Embodiment 1 is changed to the configuration shown in FIG. 7. Second
Compared to the figure, a fixed quantizer D701 is added and the quantization decider 204 is changed to a quantization decider 702, but the other things are the same.

The signal input from the input 201 is expressed as a 12-bit two's complement number. The fixed quantizer A202 performs quantization with a step size of 8. This is QUANT=
It corresponds to 4. The fixed quantizer B2O3 performs quantization with a step size of 32. This is QUANT in Figure 6
=16. The fixed quantizer D701 performs quantization with a step size of 16. This is the QUA in Figure 6.
It corresponds to NT=8. The quantization results of the fixed quantizer A202, fixed quantizer B2O3, and fixed quantizer D701 are input to the quantization determiner 702, rearranged within the block, and zigzag scanned, respectively, as shown in FIG. The amount of code generated when the 2nd to 64th values in FIG. 5 are Huffman encoded is determined from the Huffman code amount table 211. This operation is performed for 6 blocks in the macroblock, and from Equation 1, constants a and b
seek. In the case of Example 2, there are three measurement points, so
Although the optimum value of the quantization step size can be determined with higher accuracy than in the first embodiment, the calculation time increases.

The obtained optimal quantization step size is output from the quantization index 208, and the subsequent operations are the same as described in the first embodiment.

FIG. 8 is a diagram showing the configuration of the fixed quantizer D701 of the present invention. Input data 801 is expressed as a 12-bit two's complement number, and if input data 801 is positive, (MSB
=O) and 1 is added to obtain 12-bit data 802.

The reason why 1 is added is to match the quantization characteristics shown in FIG. If the input data 801 is negative (MSB=1
), the input data 801 is inverted bit by bit and 2 is added to it to obtain 12-bit data 802.The reason why 2 is added to the 0-inverted data is to add 1 and change the sign of the negative input data 801. This is for inverting and also for adding 1 to match the quantization characteristics shown in FIG. Next, the 12-bit data 802 is converted into 8-bit data 803 as shown in FIG. 8 by ignoring the 4 bits on the LSB side and the 1 bit on the MSB side. This is because the quantization step size is 16, so L
It is shown that a quantizer can be constructed by discarding the 4 bits on the SB side. The MSB of 8-bit data 803 is set to 0.
This is because the sign bit has no meaning in this method.

Note that the circuit for input data 301 to 12 bit data 302 in FIG. 3 and the input data 401 to 12 bit data in FIG.
Circuit up to bit data 402 and input data 8 in Figure 8
Since the circuits from 01 to 12-bit data 802 have the same configuration, they can be shared.

[Effects of the Invention] As described above, according to the present invention, when data expressed in two's complement is quantized with a fixed quantization step size, this can be achieved by discarding the LSB side bits without a division operation. , it has the effect of realizing high-speed processing with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the video/image encoder of the present invention. FIG. 2 is a block diagram showing an embodiment of the variable quantizer of the present invention. FIG. 3 is a diagram showing a fixed quantizer of the present invention. FIG. 4 is a diagram showing a fixed quantizer of the present invention. FIG. 5 is a diagram for explaining zigzag scanning. FIG. 6 is a diagram for explaining quantization characteristics. FIG. 7 is a block diagram showing an embodiment of the variable quantizer of the present invention. FIG. 8 is a diagram showing a fixed quantizer of the present invention. 101...Video signal input 102...Encoding control 103...Discrete cosine transformer 104...Variable quantizer 105...Inverse quantizer 106...Inverse discrete cosine transformer 107 and 108・ 109 ・ 110 ・ 111 ・ 112 ・ 201 ・ 202 ・ 203 ・ 204 ・ 205 ・ 206 ・ 207 ・ 208 ・ 209 ・ 211 ・ 212 ・ 214 ・ 301 ・ 302 ・ ・Motion compensation predictor・Loop filter・Switch・switch/ Quantization index, encoding result, input, fixed quantizer A, fixed quantizer B, quantization decider, delay buffer, variable quantizer C, encoding result, quantization index, to inverse quantizer Output, Huffman code amount table, quantization step size, Huffman encoder, input data, 12 bit data 03 01 02 03 01 02 01 02 03, 8 bit data, input data, 12 bit data, 8 bit data, fixed quantum Converter D ・Quantization decider ・Input data ・12 bit data, 8 bit data or more

Claims (3)

[Claims] (1) at least one quantization step variable quantizer, at least two fixed quantizers, and a quantization decision that controls the quantization step of the quantization step variable quantizer from the output of the fixed quantizer; 1. A variable quantizer having a fixed quantizer and inputting data expressed in two's complement, characterized in that the fixed quantizer is provided with a function of converting a negative number into a positive number. (2) The quantization step of the at least two fixed quantizers according to claim 1 is characterized in that each set is set to a different value by a power of 2, and is realized by discarding lower bits of the input data. The variable quantizer according to claim 1, characterized in that: (3) A video/image encoder comprising the variable quantizer according to claim 1 or 2.