JPH03245772A - Charge protective circuit for capacitor - Google Patents

Abstract

PURPOSE:To prevent the damage of a circuit by setting a time limit longer than a time required for satisfying predetermined conditions after provision of a charge command, and giving first and second switches with path open signals when the required conditions are not satisfied upon elapse of this set time limit. CONSTITUTION:In case of charging a capacitor 4 through a current limiting resistance 3, the time to be elapsed before the voltage of this capacitor 4 reaches the preset value can be estimated as the time constant determined by the resistance value of a current limiting resistance 3 and the capacity of the capacitor 4. Accordingly, if one sets the time limit longer than this time with a timer 22 in advance and this timer 22 operates before the capacitor voltage 4 reaches the specified value after issue of a charge command, charging operation is stopped based on a judgment that there is an abnormality in the circuit, whereby the circuit can be protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of sedentary use] This invention relates to a protection circuit when charging a capacitor.

[Conventional technology]

FIG. 2 is a circuit diagram showing a first conventional example for preventing rush current when charging a capacitor.

The voltage source inverter 5 that inputs DC power from the DC bus 2 and converts it into AC power is equipped with a large capacity capacitor 4 on its DC input side.
When operating the motor, the capacitor 4 must be charged first.

When the full voltage is applied to the capacitor 4 in a no-voltage state to charge it, excessive charging occurs! X current may flow and damage the equipment. Therefore, as shown in Figure 2,
While the second contacts 18A and 18B are open, the first contact 1
When 7A and 17B are closed, the charging current to the capacitor 4 will flow from the DC bus 2 through the current limiting resistor 3, so the current limiting resistor 3 suppresses the charging current from becoming excessive. Thereafter, the second contacts 18A and 18B are closed to complete charging of the capacitor 4.

That is, as shown in FIG. 2, when the charging command contact 10 that commands the start of charging is closed, the voltage detector 11 and the comparator 12 detect that the voltage of the capacitor 4 has not reached a predetermined level. , this comparator 12
The AND element 15 outputs a logic H signal based on the logic H signal from the inverting element 14 connected to the output side of the charge command contact 10 and the logic H signal from the charging command contact 10. As a result, the first contactor 17 is excited and the first contacts 17A and 17B are closed.

The voltage of the capacitor 4 gradually increases in value according to a time constant determined by its capacitance and the resistance value of the current limiting resistor 3. When the predetermined condition that this capacitor voltage reaches a preset value is achieved, the output of the comparator 12 is inverted, and the output of the AND element 15 changes from the previous logic H signal to a logic low signal. The first contactor 17
is de-energized, but at the same time, the output of the AND element 16 becomes a logic H signal and the second contactor 18 is energized.

As a result, the second contacts 18A and 18B are closed to short-circuit the current limiting resistor 3, and the full voltage of the DC bus 2 is applied to the capacitor 4. Charging of capacitor 4 can be completed.

FIG. 3 is a circuit diagram showing a second conventional example for preventing rush current when charging a capacitor.

The second conventional circuit shown in FIG. 3 has a charging command contact 10.
When the current is closed, the timer 13 starts operating at the same time as the charged current starts flowing through the Iti current resistance 3, and when a predetermined condition is achieved, that is, the time set by the timer 13 has elapsed, the second contactor is activated. The difference from the first conventional example already described in FIG. 2 is that numeral 18 is energized and the current limiting resistor 3 is short-circuited, and since the rest is the same as FIG. 2, the explanation thereof will be omitted.

[Problem to be solved by the invention]

As mentioned above, when charging the capacitor 4, first the voltage of the DC bus 2 is applied through the current limiting resistor 3 to suppress the inrush of excessive charging current, but if this continues, the charging is completed. Therefore, given conditions,
For example, if conditions such as the capacitor voltage has risen to a predetermined value or a certain period of time has passed since the charging command was issued, the full voltage is applied to the capacitor 4 (that is, the current limiting resistor 3 is shorted). Make it fully charged.

However, if the capacitor 4 is short-circuited, the voltage source inverter 5 that is the load is short-circuited, or the voltage of the DC bus 2 is reduced, the predetermined condition is not achieved. In the first conventional example shown in the figure, since the predetermined voltage is not detected by the comparator 12, a large current continues to flow through the current limiting resistor 3 and the first contacts 17A, 17B. 3 and the wiring could be burnt out.

In addition, in the case of the second conventional example shown in FIG. 3, even if the circuit has the above-mentioned abnormality, the current limiting resistor 3 is short-circuited after a predetermined time has elapsed, so that the short-circuit accident does not spread to the DC bus 2. There were some inconveniences, such as getting stuck.

SUMMARY OF THE INVENTION An object of the present invention is to prevent damage to the circuit due to failure of charging of the capacitor due to short-circuiting of the capacitor or load, or drop in DC power supply voltage.

[Means to solve the problem]

In order to achieve the above object, the charging protection circuit of the present invention includes a first switch that connects a capacitor to a DC power source via a current-limiting resistor in response to a charging command, and a predetermined switch after closing the first switch. In a capacitor charging circuit comprising a condition achievement detection means for detecting that a condition has been achieved, and a second switch that short-circuits the current limiting resistor using this condition achievement signal, from the time when the charging command is issued until the predetermined condition is achieved. a time limit means for setting a time limit longer than the required time; and protection for providing an open circuit signal to the first switch and the second switch when the predetermined condition is not achieved at the time when the time limit set by the time limit means has elapsed. The means shall be provided.

[Effect]

In this invention, when a capacitor is charged through a current-limiting resistor, the time until the capacitor voltage reaches a preset value is predicted by a time constant determined by the resistance value of the current-limiting resistor and the capacitor capacity. Since this is possible, set a timer longer than this time, and if this timer operates before the capacitor voltage reaches the predetermined value after the charging command is issued, it will be determined that there is an abnormality in the circuit and charging will start. By stopping the process, the circuit is protected.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, when a charging command is issued, the capacitor 4 is connected to the DC bus 2 via the current limiting resistor 3 to start charging, and when the capacitor voltage rises to a predetermined value, the capacitor 4 is connected to the DC bus 2 via the current limiting resistor 3 and starts charging. The charging method is short-circuited. Therefore,
The DC bus 2, current limiting resistor 3, capacitor 4, voltage source inverter 5, charging command contact 10, voltage detection @ 11, comparator 12, inverting element 14, AND elements 15 and 16, and the first Contactor 17 and its contacts 17A, 17
B, as well as the second contactor 18 and its contacts 18A, 18B
Since the names, uses, and functions of the circuit are the same as those used in the first conventional circuit described in FIG. 2, the explanation thereof will be omitted.

In the present invention, the AND elements 21 and 24, the timer 22
Also, a flip-flop 23 is added. The operation of this added circuit is as follows.

That is, at the time when the charging command contact 10 is closed and the charging command is issued, the voltage of the capacitor 4 is almost zero, so the output of the comparator 12 is a logic I signal. Therefore, since the inverting element 14 outputs a logic H signal, the AND element 21 receives the logic H signal from the inverting element 14 and the logic H signal from the charging command contact 10, and the timer 22
However, since the time limit set by the timer 22 has not yet been reached, the AND element 24 outputs a logic H signal via the flip-flop 23. As a result, the first contactor 17 is energized via the AND element 15, and the second contactor 18 remains unenergized via the AND element 16. Therefore, the capacitor 4 is connected to the current limiting resistor 3. This increases the voltage while limiting the charging current.

If there is no abnormality in the circuit, the voltage of the capacitor 4 increases steadily and reaches a predetermined voltage, the comparator 12 operates, the second contactor 18 is energized, the current limiting resistor 3 is shorted, and charging is completed. do.

However, if there is an abnormality in the circuit and the capacitor voltage does not rise to a predetermined value even after the time set by the timer 22 has elapsed, the output of the flip-flop 23 is inverted by the output of the timer 22, and the logical product Since the output of the element 24 becomes a logic signal, both the first contactor 17 and the second contactor 18 become non-wJ magnetic, and the charging operation of the capacitor 4 is stopped.

〔Effect of the invention〕

According to this invention, when charging a capacitor, the capacitor voltage is increased according to a curve determined by the time constant of the circuit.
The circuit is configured so that if the time exceeds a predetermined value, a timer set up for backup operates and the charging operation is stopped, so it is possible that there is an abnormality in the charging circuit and the charging time becomes longer. Also, it is possible to prevent the current limiting resistor and the wiring from burning out.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a first conventional example for preventing inrush current when charging a capacitor, and Fig. 3 is a circuit diagram showing a first conventional example for preventing inrush current when charging a capacitor. FIG. 7 is a circuit diagram showing a second conventional example for preventing inrush current. 2... DC bus, 3... Current limiting resistor, 4... Capacitor, 5... Voltage type inverter, 10... Charging command contact, 11... Voltage detector, 12... Comparator , 13.22... timer, 14... inversion element, 15
．． 16.21.24...Logic product element, 17...1st
Contactor, 17A, 17B...first contact, 18...second contactor, 18A, 18B...second contact, 23...
Furinobuf 1 Illustrated drawing

Claims (1)

[Claims] 1) A first switch that connects the capacitor to a DC power source via a current limiting resistor in response to a charging command, a condition achievement detection means that detects that a predetermined condition has been achieved after the first switch is closed, and a second switch that short-circuits the current limiting resistor in response to a condition achievement signal; A protection device for charging a capacitor, comprising: a protection device that provides an open circuit signal to the first switch and the second switch when the predetermined condition is not achieved after a time limit set by the time limit device has elapsed. Open circuit.