JPH03245258A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To decrease the conflict states among processors and to improve the processing efficiency in a multiprocessor system by separating the processors from each other for execution of the acquisition and return of the memory blocks and keeping a memory block in a pool at all times. CONSTITUTION:When an acquiring side processor 1 serves as a medium between processors and (n) pieces of memory blocks 32 are needed, the head of a chain of the blocks 32 is obtained based on the queue control information stored in a queue control information store area 31. Thus (n) pieces of chains are traced. When the NULL pointers are not set to any one of blocks 32, one of those acquired blocks 32 can be left as it is. Thus (n) pieces of blocks 32 are secured for application of th4e processor 1. Then the chain head serves as the (n + 1) memory block counted from the precedent head, and the queue control information is updated in the area 31.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for managing a pool of memory blocks existing in inter-processor shared memory in a multiprocessor system. The present invention relates to the management of empty blocks when memory blocks are used as communication media between processors.

〔overview〕

In a multiprocessor system having a shared memory between two processors, the present invention provides a processor that acquires a memory block and a processor that returns it separately, uses these two processors as a window, and uses at least one memory block in a pool. By ensuring that blocks always exist, contention between processors is reduced and processing efficiency is improved.

[Conventional technology]

Conventionally, in this type of multiprocessor system, when two processors use a memory block that exists between processors, exclusive control of the shared memory is performed by hardware to avoid contention between the processors for a single memory block. Or, one processor performed block management and the other processor used memory blocks under that management.

[Problem to be solved by the invention]

The above-mentioned conventional management of inter-processor shared memory block booleans has the following problems and cannot make a multiprocessor system function effectively.

1. When implementing exclusive control with hardware, if one processor occupies the shared memory and the other processor attempts to access the shared memory, the hardware stops its operation and waits until the other processor attempts to access the shared memory. This requires a circuit that slows down the processing speed by the amount of time and stops the hardware while the other processor is accessing the shared memory.

2. If one processor manages a shared memory block pool and the other processor operates under its management, the processor managing the shared memory block pool will have to perform management processing, resulting in a heavy load. Processors operating under management experience latency when acquiring and returning shared memory block pools, reducing processing efficiency.

The present invention solves these problems, and aims to provide a system that can prevent a decrease in processing speed and an increase in load, and improve processing efficiency.

[Means to solve the problem]

The present invention provides a multiprocessor system in which a plurality of processors have a shared memory.
A pool containing a chain of subdivided memory blocks, and a queue control information storage area for storing queue control information consisting of pointers pointing to the beginning and end of this pool are provided.
The acquiring processor includes an acquiring processor that is only permitted to acquire the memory block from the pool, and a returning processor that is only permitted to return the memory block to the pool, and the acquiring processor is configured to acquire the memory block. comprising means for acquiring an arbitrary number of the memory blocks from the pool when a condition for leaving at least one of the memory blocks in the pool later is satisfied;
The return processor is characterized in that it includes means for asynchronously returning an arbitrary number of the memory blocks to the pool.

[Effect]

An acquisition side processor and a return side processor are provided as two windows, and a plurality of processors selects and accesses either of these two windows.

When the acquiring processor satisfies the condition to leave at least one memory block in the pool after acquiring the memory block, it acquires any number of memory blocks from the pool, and the returning processor asynchronously returns any number of memory blocks to the pool. .

Having at least one memory block in the pool at all times reduces contention between processors, eliminates wait times, increases processing speed, improves processing efficiency, and simplifies hardware configuration. be able to.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention has a shared memory 3 for a plurality of processors, and this shared memory 3 includes a pool 30 in which N subdivided memory blocks 32 are chained together.
A queue control information storage area 31 is provided to store queue control information consisting of pointers pointing to the beginning and end of the pool 3.
The acquiring processor 1 is only allowed to acquire the memory block 32 from the pool 30, and the returning processor 2 is only allowed to return the memory block 32 to the pool 30.
The acquiring processor 1 includes a memory block 3.
2 includes means for acquiring an arbitrary number of memory blocks 32 from the pool 30 when a condition for leaving at least one memory block 32 in the pool 30 after acquisition is satisfied; 32 to the pool 30.

The shared memory 3 is connected to the acquiring processor 1 and the returning processor 2 via a bus 4, and can be accessed asynchronously. A plurality of memory blocks 32 are chained to form a pool 30, and the queue control information in the queue control information storage area 31 is composed of pointers pointing to the beginning and end of the chain. A NULL pointer is set, meaning that it points to nothing.

Next, the operation of the embodiment of the present invention configured as described above will be explained.

When the acquiring processor 1 needs n memory blocks 32 as a medium for inter-processor communication, first the head of the chain of memory blocks 32 is determined from the queue control information in the queue control information storage area 31, and then the chain n
Take care of yourself. If the NUI pointer is set in the memory block 32 before completing n memory blocks 32, or if the NUI pointer is set in the n-th memory block 32,
[If the ILL pointer is set, the condition that at least one memory block 32 remains in the pool 30 after acquiring the memory block 32 is not satisfied, so the operation to acquire the memory block 32 ends abnormally.

If the N ULL pointer is not set in any of the n memory blocks 32, at least one memory block 32 is set after the memory block 32 is acquired.
Therefore, n memory blocks 32 are reserved for use by the acquiring processor 1.

After the reservation, the head of the chain becomes the (n+1)th memory block from the previous head, so the queue control information in the queue control information storage area 31 is updated. In this way, the acquisition operation ends.

FIG. 2 is a diagram showing the state after memory block acquisition in the case of n=2 in the embodiment of the present invention. Information is set in the memory block 32 secured by the acquiring processor 1 and passed to the returning processor 2, which is then transferred to the memory block 3 of the pool 30.
The case of returning the item in 2 will be explained.

First, the n memory blocks 32 to be returned are chained. A NULL pointer is set in the memory block 32 at the rear. Next, as shown in FIG. 3, n memory blocks 32 return the queue control information pointer in the queue control information storage area 31 that pointed to the tail of the pool 30.
Update to point to the end of the chain. Furthermore, the fourth
A memory block 32 at the rear of the pool 30 as shown in the figure.
The state where the NULL pointer is set is changed to point to the beginning of the chain of n memory blocks 32.

The state shown in FIG. 4 is the same as the state shown in FIG. 1, although the way the chains are connected is different. In this way, the return operation is completed.

〔Effect of the invention〕

As explained above, according to the present invention, a processor that acquires a memory block and a processor that returns a memory block are separated,
By always having at least one memory block in the pool, the following effects can be achieved.

1. The acquiring processor only needs to update the pointer pointing to the beginning of the pool of queue control information, and the returning processor only needs to update the pointer pointing to the tail of the pool and the tail of the queue control information. The portions of shared memory that each processor updates can be completely separated, eliminating contention between processors.

2. The configuration is simplified because no hardware exclusive control circuit is used as a method for avoiding contention.

3. System performance is not degraded because there is no part of the hardware that performs synchronization or exclusive control.

The memory block on the arbitrary side can be acquired with 0 4,- actions.

5. Waiting for acquisition does not occur unless there is a shortage of memory blocks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a diagram showing the state of the pool after memory block acquisition in the case of n=2 in the embodiment of the present invention. FIG. 3 is a diagram showing a transient state of the operation of returning a memory block to the pool in the embodiment of the present invention. FIG. 4 is a diagram showing the state after the memory block is returned to the pool in the embodiment of the present invention. 1... Acquiring side processor, 2... Returning side processor, 3... Shared memory, 4... Bus, 30... Punobe 31... Queue control information storage area, 32... Memory block .

Claims (1)

[Claims] 1. In a multiprocessor system having a shared memory among a plurality of processors, the shared memory includes a pool in which N subdivided memory blocks are chained together, and a pointer pointing to the beginning and end of this pool. a queue control information storage area for storing queue control information, an acquiring processor that is only permitted to acquire the memory block from the pool, and a return processor that is only permitted to return the memory block to the pool. a side processor, the acquiring side processor includes means for acquiring an arbitrary number of the memory blocks from the pool when a condition that at least one of the memory blocks can remain in the pool after acquiring the memory block is satisfied; The multiprocessor system is characterized in that the returning processor includes means for asynchronously returning any number of the memory blocks to the pool.