JPH03241936A - Integration type digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To shorten the clock lock time and to prevent a bit slip of a data by setting a load of a frequency divider counter independently of a carry or borrow output of an up-down counter before a U point synchronization is established. CONSTITUTION:An up-down counter 2 counts up or counts down a clock R8K in response to a lag or a lead of the phase and generates a carry or a borrow signal in response to n-times up-count or down-count of a prescribed value. Moreover, when a selector means 4 generates a carry and is still in the up-count state, a borrow signal is generated and when the state is still in down-count state, the load value in a frequency divider counter 5 is selected smaller or larger than the prescribed value. Then a frequency divider control means 3 sets a load to the frequency divider counter 5 in response to lead or lag of the phase detected independently of the carry or borrow output of the up-down counter 2 before the input of an external U point synchronization establishing signal. Thus, bit slip is prevented.

Description

[Detailed Description of the Invention] [Summary] Regarding an integral type digital phase synchronization circuit, an integral type digital phase synchronization circuit that can shorten clock acquisition time and prevent data bit slips due to delays in synchronization acquisition. For the purpose of providing a circuit, the master clock is frequency-divided by a predetermined frequency to generate a transmission clock, and the phase lead/lag between the frequency division clock T8 of the transmission clock and the frequency division clock R8 of the receiving ront is detected. , a carry or a borrow is generated in response to the clock R8 counting up or down n times in accordance with the lead or lag of the phase, and when the up-counting state continues or the down-counting state continues. , U point synchronization is performed in an integral type digital phase synchronization circuit of a network termination device that creates a transmission clock at point T in synchronization with a reception clock from point U by setting the frequency division value of a frequency division counter to be smaller or larger than a predetermined value. Before establishment, it is configured by setting the load value of the frequency division counter regardless of the carry or borrow output of the up/down counter.

[Industrial application field]

The present invention relates to an integral-type digital phase-locked circuit, and more particularly to an integral-type digital phase-locked circuit with shortened pull-in time.

FIG. 3 shows a schematic configuration of an ISDN subscriber system.

As shown in Figure 3, the ISDN basic service subscriber system includes a subscriber line termination device (hereinafter abbreviated as LT) that terminates the line at the ISDN exchange in the central telephone office, and a subscriber line termination device (hereinafter abbreviated as LT) that terminates the line at the subscriber's premises. Network termination equipment (hereinafter abbreviated as NTI)
and terminal equipment (hereinafter abbreviated as TE) (TE 1-TEn)
It is composed of.

Here, the interface between LT and NT1 is defined as point U, NT
The interface between I and TE is called the T point. At point U, bidirectional transmission is performed using a two-wire metallic cable.

There are various transmission methods for the U point, but for example, the method currently standardized in North America is an echo canceller method using a 28IQ code of 80 kbps. I
Since the SDN is a completely synchronous network, the NTI extracts timing from the received signal from the LT, and synchronizes with this to create transmission timing to the LT and transmission timing to the TE.

On the other hand, the transmission method at point T is the 192kbps AMI code standardized by CCITT, from TE to NT1.
Separate 2g metallic cables are used for both the NTI and TE directions.

FIG. 4 shows a schematic configuration of the NTI.

As shown in FIG. 4, the NTI is composed of a U-point transceiver 101 that transmits and receives the U-point, a 7-point transceiver 102 that transmits and receives the T-point, and a controller 103 that controls their operations. .

The U-point transceiver I01 extracts timing from the received signal to create a clock synchronized with the received signal. Then, using the T point lock that we have created, 7
The point transceiver 102 creates a transmission signal at point T.

However, the received signal at point U has jitter due to the equalization process of subscriber line noise and line loss, and as a result, the timing-extracted clock also has jitter.

In timing extraction at point U, it is necessary to have sufficient tracking characteristics in order to ensure the performance of waveform equalization and reproduction. That is, if there is jitter in the human input signal itself, jitter will occur in the recovered clock accordingly, and depending on the noise level of the subscriber line, this may reach about 10% of one cycle of the 80 kHz clock.

On the other hand, with respect to the transmission timing at point T, it is necessary to suppress the polar fluctuation in order to ensure the reception characteristics of the TE. Therefore, CCITT specifies that the absolute amount of jitter of 50 cells or more is 5% or less of one cycle of a 192 kHz clock.

In this way, the jitter at point T is smaller than the jitter at point U, so when creating the transmission clock at point T from the recovered clock at point U, a means to compress the jitter is required. A commonly used method is to create a transmission clock at point T with jitter compressed while following the recovered clock at point U by using an integral type digital phase synchronization circuit.

In such an integral type digital phase locked circuit,
It is desired that the clock retraction time be short.

[Conventional technology]

Figure 5 shows a conventional integral type digital phase-locked circuit, in which 80k) (80k) extracted from the received signal at point U is shown.
An integral type digital phase synchronization circuit is shown that regenerates a 192 kHz T-point transmission clock synchronized with the z clock. In the figure, 11 and 12 are frequency division counters,
13 is a flip-flop, 14 is an up/down counter, 15 is a differential circuit (d/dt), 16.17 is an AND circuit, 18 is an OR circuit, 19 is a selector, 20 is a frequency division counter, and 21 is a master clock generator. be.

The frequency division counter 20 normally includes a mask clock generator 2.
The 15.36 MHz mask clock of 1 is rotated by 8 (one cycle) to create a 192 kHz transmission clock.
When using a 56-decimal counter, A=176)
This can be achieved by loading.

The frequency division counter 11 divides this 192 kHz clock by 2.
Divide the frequency by 4 to create an 8k)tz clock T8k.

On the other hand, the 80kHz clock extracted from the received signal is IO-divided by the frequency division counter 12, and the 8kHz clock R8
Create K. This 8kHz clock R8 is synchronized with the received signal and has jitter.

The flip-flop 13 compares the phases of the clock T8 and the clock R8.

6 and 7 are diagrams showing the relationship between the clock phase and the flip-flop output, and FIG. 6 shows the relationship between the clock phase and the flip-flop output.
8K is advanced by clock R8, and the seventh
The figure shows a case where clock 78K is delayed by clock R8.

In other words, clock R8K is used as data, and clock T8K is used as data.
When the flip-flop 13 is operated using the clock T8 as the clock, if the output Q is "O" as shown in FIG. 6, the clock T8 is ahead in phase by the clock R8. If the output Q is "1", the clock 78 is delayed in phase by the clock R8.

The up/down counter 14 counts down when the phase of the clock 78 is ahead, that is, when the output Q of the flip-flop 13 is "O". If the down count continues n times, the amplifier down counter 14 outputs borrow BR, and the output Q of the flip-flop 13 is °0', the output of the AND circuit 16 is °1''.
Therefore, A-1 is selected as the output of the selector 19, and this becomes the load value of the frequency division counter 20.

In this case, the differentiating circuit 15 detects the rising edge of the clock R8, generates a pulse for one cycle of the 192 kHz transmission clock, and controls the opening of the AND circuits 16 and 17 during this period. There is.

When the frequency division counter 20 is loaded with A-1, the period of the frequency division counter 20 becomes longer by one clock, and therefore the frequency division counter 20, which is a frequency division counter by 80, performs a frequency division by 81 operation. As a result, the phase of the 192k)tz output clock generated from the frequency division counter 20 is delayed.

When such a state in which the phase of lock T8 is advanced continuously occurs, the frequency division period of the frequency division counter 20 is controlled, the phase of the clock T8 is delayed, and the phases of the clock 78 and the clock R8 gradually approach each other.

On the other hand, when the phase of the clock 78 is delayed, that is, when the output Q of the flip-flop 13 is "1",
The up/down counter 14 counts the amps. Up count continues n times ~ Up down counter 1
4 outputs carry CO, and flip-flop 1
If the Q output from 3 is 1', the AND circuit 17
The output becomes “1”, and the output of the selector 19 becomes A+
1 is selected and becomes the load value of the frequency division counter 20.

In this state, the cycle of the frequency division counter 20 is shortened by one clock, and therefore the frequency division counter 20, which is a frequency division counter by 80, performs a frequency division by 79 operation.

As a result, 192kHz generated from the frequency division counter 20
The phase of the output clock will advance.

When such a phase delay state of the long clock T8 occurs continuously, the frequency dividing period of the frequency dividing counter 20 is controlled, the phase of the clock 78 advances, and the phases of the clock T8 and the clock R8 gradually approach each other.

In addition, when the amplifier down counter 14 is not outputting borrow BR or carry CO, the AND circuit 16
．． Since both outputs of 17 are "0," OR circuit 1
The output of 8 becomes 1', A is selected as the output of the selector 19, and the frequency division counter 20 performs a frequency division period of 80.

That is, the frequency division counter 20 performs a frequency division operation of 80 under normal conditions, performs a frequency division operation of 81 when the phase lead state continues, and performs a frequency division operation of 79 when the phase lag state continues. .

FIG. 8 shows the state transition of the up/down counter, and exemplifies the case where the up/down counter 14 operates from 1 to 9.

As shown in FIG. 8, the up/down counter 14 performs up-counting and down-counting with 5 as the center, outputs a borrow when the count value reaches 1, and when the count value further downcounts, the count value returns to 5. . Further, when the count value reaches 9, a carry is output, and when the count value is further counted up, the count value returns to 5.

By the way, jitter occurs in the created 192 kHz clock when phase control is performed and the 8I frequency division operation or 79 frequency division cycle is performed, and at this time, due to the change in the clock cycle, Appears as jitter. On the other hand, although the received clock originally has jitter, phase control is not performed unless a phase lead state or a phase lag state is continuously detected based on the operation of the up/down counter 14.

In other words, even if the phase lead state and phase delay state are frequently switched due to jitter in the clock R8,
No phase control is performed following this.

Therefore, it is possible to obtain an output clock that is phase synchronized with an input clock having jitter and suppresses jitter.

By using the integral type digital phase synchronization circuit in this manner, it is possible to perform clock regeneration that has a jitter suppressing effect.

[Problem to be solved by the invention]

In an integral type digital phase synchronization circuit, fine phase control is not performed when the phases are substantially matched, so that it has a jitter suppression effect.

However, there is a problem in that the lead-in time from a state where the phases do not match sufficiently, that is, an initial state, to a state where the phases match is long. This is because the frequency of phase control is low because the up/down counter is used to perform the integral operation.

For example, in the previous example, the time required to move from the state where the phases are most out of phase to the state where the phases match is determined as follows.

Assume now that there is a phase lag, and the phase difference=125 μs/2=62.5 μs.

If phase control is performed by five consecutive phase delay detections, the phase control interval will be 125 μs x 5 = Ei 25 μs. If the phase shift due to the frequency deviation of the oscillator during this period is +50 ppm, then 625 μs x 50 ppm = 31.25 ns, and the amount of phase fluctuation due to one control is one cycle of 15.36 MHz, so 1/15.36 MHz = 65.1 ns. . As is clear from the above calculation, the phases approach each other by 65.1-31.25=33.85 ns every 625 μs. As a result, it takes 625, czsX (62,5 μs/33.85 n5) until the phases completely match.
= approximately 1.1 sec is required.

If the integral characteristic by the up-down counter is not provided, phase control is performed every 8 kHz, that is, every 125 μs, so the time to draw in the same phase difference as in the above case would be about 132 ms.

According to the 2BIQ method standardized in North America, the time required to equalize point U is 150 m in the case of a warm start.
It is within 5. Therefore, in the above case, synchronization of the subscriber lines is established within 150 m5, and communication is possible at point U. However, if the clock pull-in time is longer than this,
After becoming communicable at point U, 0 point reception 80k
Since a phase shift occurs between Hz and T-point transmission 192 k) tz, there is a possibility that the received data from U-point causes a bit slip during T-point transmission.

That is, in the integral type digital phase synchronization circuit, a jitter suppression effect can be expected, but since the pull-in time is long, there is a problem that a bit slip may occur after the establishment of #A between the U points.

The present invention aims to solve the problems of the prior art, and is capable of shortening the clock acquisition time in an integral type digital phase synchronized circuit, and therefore, in the zero-point transceiver of the network termination device (NT1). , U
The purpose of the present invention is to provide an integral type digital phase-locked circuit that can prevent data bit slips due to delays in synchronization when creating a T-point transmission clock synchronized with a clock extracted from a T-point reception signal. There is.

[Means for Solving the Problems] As shown in FIG. 1, the present invention has a frequency division counter 5, a phase detection means 1, an up/down counter 2, and a selector means 4. , a frequency division control means 3 is provided in an integral type digital phase synchronization circuit in an ISDNO network terminating device NTI which generates a transmission clock at point T in synchronization with a reception clock extracted from a reception signal from point U.

Here, the frequency division counter 5 divides the frequency of the master clock by a predetermined value loaded to generate a transmission clock, and the phase detection means generates a clock T obtained by dividing the frequency of the transmission clock.
The phase lead/lag between the received clock R8 and the clock R8 obtained by dividing the reception clock is detected. Further, the up/down counter 2 counts up or down the clock R8K according to the lead or lag of the phase, and generates a carry or a borrow depending on the predetermined value of n amplifier counts or down counts. The selector means 4 is
When a carry occurs and the count is still up, or a borrow occurs and the count is still down, the load value in the frequency dividing counter 5 is selected to be smaller or larger than a predetermined value. Then, the frequency division control means 3 controls the load value in the frequency division counter 5 according to the lead or lag of the phase detected regardless of the carry or borrow output of the up/down counter 2 before receiving the U point synchronization establishment signal from the outside. Configure settings.

[Effect]

In the integral type digital phase-locked circuit, the acquisition time is sacrificed in order to achieve jitter suppression, and as a result, a 7-point transmission clock synchronized with the received signal from point U is created at the 0-point transceiver as described above. When used to transmit data from point U, there is a possibility that a bit slip may occur when data received from point U is transmitted to point T.

However, it is necessary to suppress output fluctuation at point T only when point T is in operation. Generally, after synchronization with point U has been established, point T responds to a request to start transmission from the TE.
When the sequence INFO2 indicating a response from the network is sent from NT1, it becomes active, and until then there is no NTI transmission signal.From this, the suppression of transmission jitter at point T is equivalent to the suppression of transmission jitter at point U. This can be done after synchronization is established.

Therefore, in the integral type digital phase synchronization circuit for clock generation in the 0-point transceiver, the integral characteristic is eliminated and the phase control frequency is increased to shorten the pull-in time until synchronization at the U point is established. After U-point synchronization is established, an integral operation is performed to suppress jitter. That is, by switching the integral characteristic by establishing synchronization of the U point, it is possible to reduce the pull-in time and suppress jitter to the extent necessary for practical use.

This switching of the integral characteristic may be performed using the U-point synchronization establishment signal, but the same effect can also be expected by using a signal equivalent to this, such as the operation of the act bit during maintenance monitoring channel focus. Furthermore, the same effect can be expected even if a timer for a certain period of time from the start of training at point U is used to eliminate the integral characteristic without actually using a signal indicating the establishment of synchronization.

〔Example〕

FIG. 2 shows one embodiment of the present invention.
The same parts as in the figure are indicated by the same numbers, and 22 and 23 are OR circuits.

When the U point synchronization is established, the OR circuits 22 and 23 receive the U point synchronization establishment signal '0'' from the synchronization establishment detection circuit (not shown).
However, since "work" is given before synchronization is established, each output becomes "1".

Therefore, regardless of the borrow or carry output state of the up/down counter 14, the output clock T8 of the frequency division counter 11 is set to the output clock R8 of the frequency division counter 12.
AND circuit 1 every 8kHz, depending on the phase state of
6.17 outputs '1'.

Therefore, phase control is performed by continuously applying A+1 or A-1 from the selector 19 to the dividing counter 20 every 8 kHz without performing an integral operation, so that the integral type digital phase synchronized circuit can be quickly pulled in. It will be done.

After the synchronization of the U point is established, since the U point synchronization establishment signal 101 is given, the OR circuits 22 and 23 output the borrow or carry output of the up/down counter 14 as they are, and therefore the integral type digital phase The synchronous circuit operates with integral characteristics in the same manner as the conventional circuit when the U point is out of synchronization.

In this way, in the present invention, whether or not to perform the integral operation is switched by establishing the synchronization of the U point, so that it is possible to simultaneously shorten the pull-in time and suppress jitter.

[Effects of the Invention] As explained above, according to the present invention, ISDN NT1
In the integral type digital phase-locked circuit provided in the U-point transceiver, the integration operation is switched based on the establishment of synchronization at the U point, so the clock acquisition time can be shortened, and the U-point transceiver can Bit slips can be prevented from occurring in T-point transmission of point-received signals. In addition, since the shifter can be suppressed during communication, transmission characteristics can be improved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the schematic configuration of the subscriber system of 1SDN, and Fig. 4 is a diagram showing the schematic configuration of the subscriber system of 1SDN. A diagram showing a schematic configuration,
Fig. 5 shows a conventional integral type digital phase synchronization circuit, Figs. 6 and 7 show the relationship between the clock phase and the flip-flop output, and Fig. 8 shows the state transition of an up-down counter. It is a diagram. 1 is a phase detection means, 2 is an up/down counter, 3 is a frequency division control means, 4 is a selector means, and 5 is a frequency division counter. Figure 3 Diagram showing the schematic configuration of NTI Figure 4 Telephone office

Claims (1)

[Claims] A frequency division counter (5) that generates a transmission clock by dividing a master clock by a predetermined value loaded, and a clock (T8K) obtained by dividing the transmission clock and a reception clock. A phase detection means (1) for detecting a phase lead or lag with respect to the clock (R8K), and a clock (R8K) up-counted or down-counted n times to a predetermined value according to the phase lead or lag. Or an up/down counter (2) that generates a carry or borrow depending on the down count.
When the carry occurs and the count is still up, or when the borrow occurs and the count is still down,
selector means (4) for setting the load value in the frequency dividing counter (5) to be smaller or larger than a predetermined value; In the integral type digital phase synchronization circuit in the ISDN network termination device (NT1) to be created, before inputting the U point synchronization establishment signal from the outside, the detected An integral type digital phase synchronization circuit characterized in that it is provided with a frequency division control means (3) for setting a load value in the frequency division counter (5) according to a phase advance or lag.