JPH03241590A - Gallium arsenide semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a Y-decoder part by providing a column selection line which crosses across plural memory cell arrays and extends in a prescribed direction as against the Y-decoder part and transmitting a decoder output to bit lines. CONSTITUTION:The column selection line 5 which crosses across the memory cell arrays 1a-1d and extends in the prescribed direction from the Y-decoder 4 is provided. Then, the bit lines 2a-2d of respective arrays 1a-1d are respective ly connected with the selection line 5 and the Y-decoder output is transmitted to respective bit lines 2a-2d. Consequently, the Y-decoder part can be reduced without the need of provided the Y-decoders for two pairs of memory cell arrays and the drawing distance of a wiring group connected to the Y-decoder part becomes short, whereby the increase of a chip area can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a gallium arsenide semiconductor integrated circuit device in which a memory circuit is mounted on a gallium arsenide semiconductor substrate, and particularly relates to an improvement in an address selection method in the memory circuit. be.

[Conventional technology]

FIG. 4 shows, for example, IEICE Technical Research Report νo1.
8B, No. 354. ED, 88. P, No. 10 of 107
1 shows the configuration of a memory cell array of the gallium arsenide semiconductor memory shown in the figure. The above memory is a memory with a x4 configuration, that is, information can be accessed at four addresses at the same time.

Here, the semiconductor memory is composed of four memory function blocks (hereinafter referred to as I10), and each I1
0 is a memory cell array formed on a gallium arsenide semiconductor substrate, and an input/output function section (11) formed around the memory cell array.
0 part), as well as bit lines and word lines.

In the figure, 1a to 1d are memory cell arrays of l10-1 to l10-4, 2a to 2d are focus lines of l10-1 to l10-4, and 3a
-3d are word lines of l10-1 to l10-4. Also, 4a
is the Y decoder section for l10-1.2, and 4b is -I10-
The Y decoder section for 3.4 consists of a Y decoder that selects the bit line of the memory cell array corresponding to Ilo, and a Y decoder selection signal wiring group for transmitting the signal for bit line selection. ing.

Memory cell selection within each Ilo is based on bit lines 2a to 2.
d and word lines 3a to 3d. At this time, a group of Y decoder selection signals consisting of exactly the same signals is applied to the Y decoders 4a and 4b for l10-1.2 and l10-3.4 via the above wiring group.

By the way, in each memory cell array 1a to 1d of I10,
The reason why the bit lines 2a to 2d are set shorter than the word lines 3a to 3d is as follows.

In general, a gallium arsenide semiconductor MESFET has a larger source/drain current in the subthreshold region and a higher temperature dependence than a silicon semiconductor MO3FET. Therefore, when a memory cell array is constructed using MESFETs, leakage current flows from the focus line 10 toward the cell ground through the path 14 shown in FIG. Since the signal amplitude of the bit line is approximately 0.2 to 0.6 V, and the signal amplitude of the storage node of the memory cell 9 is approximately 0°0 to 0.6 V, the leakage current is The state shown in the figure, that is, the bit line 10 is High"
level, and reaches its maximum level when the storage node 11 of the memory cell 9 connected via the access transistor 13 is at the "'Low" level.

Therefore, the total leakage current flowing from the bit line 10 toward the cell ground is the “High” or “Low” level of the data held in the memory cell 9 connected to the bit line 10.
This change in the total leakage current directly affects the "High" level of the bit line 10.

Furthermore, since the bit line is usually connected to an amplifier with high sensing ability, variations in the high level of the bit line lead to variations in access time.Especially, during high temperature operation, the above leakage current increases dramatically. In order to
This not only degrades access time but also causes read operation failure.

Therefore, in the conventional example described above, one measure against such current leakage is to reduce the number of memory cells connected to one bit line, that is, to shorten the bit line, thereby reducing the total leakage current from the bit line. is suppressed.

Further, in GaAsRAM, it is difficult to maintain uniformity of device characteristics over a wide area, so in addition to reducing the chip area, it is desirable to shorten the diagonal distance of the chip as much as possible. For this reason, in the above conventional example, as the number of columns (bit lines) increases, the chip shape becomes extremely elongated by placing Y decoders between ■10 and 1.2 and between l10 and 3.4. It prevents that.

[Problem to be solved by the invention]

A conventional gallium arsenide semiconductor memory is configured as described above, and in order to shorten the diagonal distance of the chip, the Y decoder selection signal wiring group is arranged as l10-1゜2 and Ilo-3,4.
In this case, Y
The routing distance of the decoder selection signal wiring group becomes longer, that is, the routing distance of the wiring group between the Y decoder sections 4a and 4b, and the routing distance of the wiring group from the outside to both Y decoder sections 4a and 4b becomes necessary. The chip area will increase. As a result, in gallium arsenide semiconductors, it is difficult to obtain uniform device characteristics over a wide area, resulting in a significant decrease in yield.

This invention was made to solve the above-mentioned problems, and has a memory circuit that can prevent an increase in chip area by shortening the routing distance of the selection signal wiring group of the first Y lever. The object is to obtain a gallium arsenide semiconductor integrated circuit device.

[Means for Solving the Problems] A gallium arsenide semiconductor integrated circuit device according to the present invention has a memory circuit including a column extending in a predetermined direction with respect to a portion of a Y lever across one or more memory cell arrays. A selection line is provided, and the decoder output of the first Y lever is simultaneously transmitted to the bit lines located in the predetermined direction via the column selection line.

[Effect]

In this invention, the gallium arsenide semiconductor memory (memory circuit) is configured such that two or more bit lines located in the same direction with respect to the Y decoder section are simultaneously selected by the decoder output of one Y decoder section. Therefore, the number of Y decoders that generate the same bit line selection signal can be reduced. As a result, the routing distance of the Y decoder selection signal wiring group connected to the Y decoder section is shortened, and an increase in chip area can be suppressed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining a gallium arsenide semiconductor integrated circuit device according to a first embodiment of the present invention, and shows the configuration of a memory cell array of a gallium arsenide semiconductor memory. In the figure, the same reference numerals as in FIG. 4 indicate the same or corresponding parts, and 4 is a Y decoder section disposed around the chip;
Reference numeral 5 denotes a column selection line extending across the plurality of memory cell arrays 1a to IC to the right side of the paper with respect to the Y decoder section 4.
The bit lines 2a to 2d located in the same direction as the Y decoder section 4 are connected to the bit lines 2a to 2d. As a result, the bit lines 2a to 2d of each memory cell array 1a to 1d are simultaneously selected by the decoder output of one Y decoder section 4. Note that the information signal for bit line selection to the Y decoder section 4 is supplied from the Y decoder selection signal line section as in the conventional case.

Next, the effects will be explained.

When a bit line selection signal is input from the Y decoder selection signal wiring group to the Y decoder section 4, the Y decoder selection signal is input to a predetermined column selection line 5.
A decoder output, ie a selection signal, is transmitted. At this time, the bit lines 2a to 2d of l10-1 to l10-4 connected to this column selection line 5 are simultaneously selected. In this way, all I10 bit lines are selected simultaneously by one Y decoder section 4.

In this way, in this embodiment, a plurality of memory cell arrays 1
A column selection line 5 is provided which extends rightward in the paper plane with respect to the Y decoder section 4 across the IC, and the decoder output of the Y decoder section 4 is located in the above direction via the column selection line 5. 2d, the number of Y decoder sections 4 that generate the same bit line selection signal can be reduced (in other words, the conventional two Y decoder sections can be reduced to one). As a result, the routing distance of the Y decoder selection signal wiring group connected to the Y decoder section 4 can be shortened, and an increase in chip area can be suppressed.

In the above embodiment, the Y decoder section 4 is arranged at the periphery of the chip, but it may also be arranged at the center of the chip, for example between the memory cell arrays. FIG. 2 shows a second embodiment with such a configuration, in which the Y decoder section 4 is arranged between the memory cell arrays 1b and lc, and the other configurations are the same as in the first embodiment. They are the same, and in this case also the same effects as in the embodiment are achieved.

Further, in each of the above embodiments, a memory having a ×4 configuration in which the memory cell array has an I10 configuration in which each memory cell array has an input/output section has been described, but the memory configuration is not limited to this.

FIG. 3 shows a ×1 configuration as a third embodiment of the present invention.

In other words, it shows a memory configured to access information for each address.
The memory cell arrays 22a to 22d are divided bit lines divided for each memory cell array 11d. Also, Y is provided around the chip as in the first embodiment.
A decoder section 4 is arranged, and one column selection line 5 is arranged so as to be connectable to each of the divided bit lines 22a to 22d located in the same direction with respect to the decoder section 4. It is set up. Here, the column selection line 5 and each divided bit line 22a to 22d are further explained.
A Z decoder section 7 is provided for connection with the Z decoder section 7.

In the memory having this configuration, the divided bit lines 22a to 22d and the word lines 33a to 33d are selected, and addresses at the same position are set for each memory cell array lla to lid. In addition, the Z decoder section 7
When receiving a signal from the main data line 8, it outputs a data signal to the first to sixth data signals IJ16a to IJ6d to select memory cell arrays Ila to lid. As a result, one address of a predetermined memory cell array is designated.

In this case, as in each of the above embodiments, one Y decoder section 4
Since the bit lines 22a to 22d located in the same direction with respect to the decoder section 4 can be selected by the decoder output, the number of Y decoder sections that generate the same column selection signal can be reduced, and the Y decoder The routing distance of the selection signal wiring group can be shortened, and an increase in chip area can be suppressed.

〔Effect of the invention〕

As described above, according to the gallium arsenide semiconductor integrated circuit device according to the present invention, a column selection line is provided that extends in a predetermined direction with respect to the Y decoder section across one or more memory cell arrays, and Since the decoder outputs of the Y decoders are simultaneously transmitted to the bit lines located in the predetermined direction via the column selection lines, it is possible to reduce the number of Y decoders that generate the same bit line selection signals. This has the effect that the routing distance of the wiring group connected to the Y decoder section is shortened, and an increase in chip area can be prevented.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a memory cell array for explaining a gallium arsenide semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a memory cell array for explaining a second embodiment of the device of the present invention. FIG. 3 is a configuration diagram of a memory cell array for explaining the third embodiment of the present invention, FIG. 4 is a configuration diagram showing a memory cell array of a conventional gallium arsenide semiconductor memory, and FIG. FIG. 3 is a circuit diagram showing a path of leakage current from a bit line. ■A to 1d are memory cell arrays of l10-1 to 4, 2a
~2d are bit lines of l10-1~4, 3a~3d are l1
0-1 to 4 word lines, 4 is a Y decoder section, 5 is a column selection line, lla to lid are first to fourth memory cell arrays, 22a to 22d are first to fourth divided bit lines, 33
a to 33d are the first to fourth word lines, 6a to 6d are the first
˜4th data line, 7 is a Z decoder, and 8 is a main data line. Note that the same reference numerals in the figures indicate the same or equivalent parts. Earthquake 1 diagram

Claims (1)

[Claims] (1) A memory circuit is mounted on a gallium arsenide semiconductor substrate,
In a gallium arsenide semiconductor integrated circuit device in which the memory circuit has a plurality of memory cell arrays and a Y-decoder section for selecting bit lines thereof, the Y-decoder section includes a plurality of Y-decoder sections extending in a predetermined direction with respect to the Y-decoder section. A gallium arsenide semiconductor integrated circuit device comprising a column selection line, and a decoder output is simultaneously transmitted to each bit line located in a predetermined direction with respect to the Y decoder section via the column selection line. .