JPH0323930B2 - - Google Patents
Info
- Publication number
- JPH0323930B2 JPH0323930B2 JP59165903A JP16590384A JPH0323930B2 JP H0323930 B2 JPH0323930 B2 JP H0323930B2 JP 59165903 A JP59165903 A JP 59165903A JP 16590384 A JP16590384 A JP 16590384A JP H0323930 B2 JPH0323930 B2 JP H0323930B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- power
- sequence
- signal
- alarm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
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- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、電算機システム等に使用する電源の
制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control system for a power supply used in a computer system or the like.
電算機システム等において使用する電源は、一
般に複数の電源ユニツトを含み、これらを電源制
御装置によつて、一定のシーケンスに従つて、投
入および切断するよう制御している。 2. Description of the Related Art Power supplies used in computer systems and the like generally include a plurality of power supply units, which are controlled to be turned on and off according to a certain sequence by a power supply control device.
しかし、電源ユニツトのアラーム発生時におけ
る電源の切断には、特別の考慮を要することがあ
る。 However, special consideration may be required when turning off the power when an alarm occurs in the power supply unit.
［従来の技術］
第２図は、電算機システム等に使用する電源装
置の機能ブロツク図である。[Prior Art] FIG. 2 is a functional block diagram of a power supply device used in a computer system or the like.
図において、PWR１，PWR２，PWR３，
PWR４は電源ユニツト、UPCは電源制御装置を
示す。 In the figure, PWR1, PWR2, PWR3,
PWR4 indicates the power supply unit, and UPC indicates the power control device.
電源制御装置UPCは、各電源ユニツトPWR
１，PWR２，PWR３，PWR４の電源投入およ
び切断を、予め定めたシーケンスに基づいて行う
よう制御する。 The power control device UPC controls each power supply unit PWR.
1. Control the power on and off of PWR2, PWR3, and PWR4 based on a predetermined sequence.
従来の電源システムにおいては、電源ユニツト
PWR１，PWR２，PWR３，PWR４のいずれか
から、低電圧、過電圧、過電流等のアラームが発
生すると、電源制御装置UPC（以下単にUPCと言
う）は、そのアラーム信号を検出して、各電源ユ
ニツトPWR１，PWR２，PWR３，PWR４に対
して、通常の電源切断時と同じくシーケンスに従
つて切断信号を送出する。 In a conventional power system, the power supply unit
When an alarm such as low voltage, overvoltage, or overcurrent occurs from any of PWR1, PWR2, PWR3, or PWR4, the power supply control device UPC (hereinafter simply referred to as UPC) detects the alarm signal and controls each power supply unit. A disconnection signal is sent to PWR1, PWR2, PWR3, and PWR4 according to the same sequence as when the power is disconnected normally.
第３図は、そのシーケンスを示したタイム・チ
ヤートである。電源の投入時には、PUCから各
電源ユニツトへ、電源ユニツトPWR１→PWR２
→PWR３→PWR４→投入完了信号、というケー
シンスで投入指示信号が送出される。 FIG. 3 is a time chart showing the sequence. When the power is turned on, the power supply unit PWR1→PWR2 is sent from the PUC to each power supply unit.
→ PWR3 → PWR4 → Closing completion signal A closing instruction signal is sent in the casing.
電源切断時には、これと逆に、投入完了信号断
→PWR４断→PWR３断→PWR２断→PWR１
断、というシーケンスで切断指示信号が送出され
る。 When the power is turned off, the power-on completion signal is turned off → PWR4 is turned off → PWR3 is turned off → PWR2 is turned off → PWR1
A disconnection instruction signal is sent in this sequence.
電源ユニツトPWR２からアラームが上がると、
PUCは、通常の電源切断時と同一のシーケンス
で各電源ユニツトPWR１，PWR２，PWR３，
PWR４に切断指示信号を送出する。 When an alarm goes off from power supply unit PWR2,
The PUC switches each power supply unit PWR1, PWR2, PWR3,
Sends a disconnection instruction signal to PWR4.
［発明が解決しようとする問題点］
従来の電源制御方式においては、電源ユニツト
からのアラームの発生の場合であつても、通常の
切断の際と同一のシーケンスに従つて各電源ユニ
ツトを切断するよう制御する。[Problems to be Solved by the Invention] In the conventional power supply control system, even if an alarm occurs from a power supply unit, each power supply unit is disconnected according to the same sequence as for normal disconnection. control like this.
ところが、低電圧或いは過電圧の電圧アラーム
の発生時には、第３図に示すように、電源シーケ
ンスが長い時間に亘つて逆転することがあつて、
このときには、負荷である論理素子等を劣化また
は破壊することがあつた。 However, when a low voltage or overvoltage alarm occurs, the power supply sequence may be reversed for a long time, as shown in Figure 3.
At this time, logic elements and the like that are loads may be deteriorated or destroyed.
［問題点を解決するための手段］
上記問題点は、複数の電源ユニツトの電源投
入・切断を、予め定められたシーケンスに従つて
制御するシーケンス制御回路、複数の電源ユニツ
トの発するアラーム信号を検出するアラーム検出
回路、ならびにアラーム信号検出回路がアラーム
信号を検出したとき前記電源ユニツトに一斉に切
断信号を送出する切断信号一斉送出回路とを備
え、前記電源ユニツトのアラームが発生したと
き、総ての電源ユニツトに対して一斉に切断信号
を送出するよう構成した本発明な電源制御方式に
よつて解決される。[Means for solving the problem] The above problem is caused by a sequence control circuit that controls power on/off of multiple power supply units according to a predetermined sequence, and a sequence control circuit that detects alarm signals emitted by multiple power supply units. and a disconnection signal simultaneous transmission circuit that transmits a disconnection signal to the power supply units all at once when the alarm signal detection circuit detects an alarm signal. This problem is solved by the power supply control method of the present invention, which is configured to send a disconnection signal to all power supply units all at once.
［作用］
即ち、電源制御装置UPCは、電源ユニツトの
アラーム発生時には、総ての電源ユニツトに一斉
に切断信号を送出して、電源シーケンスの逆転を
最小限に抑えるものである。[Function] That is, when an alarm occurs in a power supply unit, the power supply control device UPC sends out a disconnection signal to all power supply units at the same time, thereby minimizing the reversal of the power supply sequence.
［実施例］
以下第１図に示す実施例により、本発明の要旨
を具体的に説明する。[Example] The gist of the present invention will be specifically explained below with reference to an example shown in FIG.
第１図ａは、本発明の一実施例の電源投入・切
断シーケンスを示すタイム・チヤートである。 FIG. 1a is a time chart showing the power on/off sequence of one embodiment of the present invention.
通常の電源投入および切断の場合は、第３図の
従来の電源制御方式と同じく、電源の投入時に
は、UPCから各電源ユニツトへ、電源ユニツト
PWR１→PWR２→PWR３→PWR４→投入完了
信号、というシーケンスで投入指示信号が送出さ
れ、電源切断時には、これと逆に、投入完了信号
断→PWR４断→PWR３断→PWR２断→PWR１
断、というシーケンスで切断指示信号が送出され
る。 In the case of normal power-on and power-off, as with the conventional power control method shown in Figure 3, when the power is turned on, the power is sent from the UPC to each power supply unit.
A closing instruction signal is sent in the sequence of PWR1 → PWR2 → PWR3 → PWR4 → Closing completion signal, and when the power is turned off, the sequence is reversed: Closing completion signal disconnected → PWR4 disconnected → PWR3 disconnected → PWR2 disconnected → PWR1
A disconnection instruction signal is sent in this sequence.
つぎに、例えば電源ユニツトPWR２にアラー
ムが発生した場合には、UPCは各電源ユニツト
PWR１，PWR２，PWR３，PWR４に対して、
一斉に切断指示信号を送出する。 Next, for example, if an alarm occurs in power supply unit PWR2, the UPC will
For PWR1, PWR2, PWR3, PWR4,
Send a disconnection instruction signal all at once.
このようにして、図に示すように電源シーケン
スの逆転時間を最小限に抑えるものである。 In this way, the power sequence reversal time is minimized as shown.
第１図ｂは、本発明による電源制御をリレーに
よるシーケンス回路で実現した一実施例の回路図
である。 FIG. 1b is a circuit diagram of an embodiment in which the power supply control according to the present invention is realized by a sequence circuit using relays.
図において、Ｋ１，Ｋ２，Ｋ３，Ｋ４，Koは
リレーの接点であつて、Ｋ１，Ｋ２，Ｋ３，Ｋ４
は、電源投入の際にはシーケンスに従つて順次閉
じられ、通常の切断時には逆のシーケンスに従つ
て順次開かれる。 In the figure, K1, K2, K3, K4, and Ko are the contacts of the relay.
are sequentially closed according to the sequence when the power is turned on, and are sequentially opened according to the reverse sequence during normal disconnection.
その出力信号は、それぞれ電源ユニツトPWR
１，PWR２，PWR３，PWR４への投入信号１，
２，３，４となる。 Its output signal is connected to the power supply unit PWR, respectively.
1, input signal to PWR2, PWR3, PWR4 1,
2, 3, 4.
リレー接点Koは、常時閉じられており、アラ
ーム発生の際に開かれる。その出力信号COMは
全電源ユニツトへの共通切断信号となる。 Relay contact Ko is normally closed and opens when an alarm occurs. Its output signal COM becomes a common disconnection signal to all power supply units.
第１図ｃは、同じく、これを論理回路で実現し
た実施例の回路図である。 Similarly, FIG. 1c is a circuit diagram of an embodiment in which this is implemented using a logic circuit.
図において、Ｇ１，Ｇ２，Ｇ３，Ｇ４はAND
ゲートであり、各ANDゲートＧ１，Ｇ２，Ｇ３，
Ｇ４には、それぞれシーケンスを持たされた投入
信号１，２，３，４とアラーム発生時“０”とな
る信号とが入力され、この出力はそれぞれ投入・
切断信号１，２，３，４となつて、各電源ユニツ
トPWR１，PWR２，PWR３，PWR４へ送出さ
れる。 In the figure, G1, G2, G3, G4 are AND
gate, each AND gate G1, G2, G3,
Input signals 1, 2, 3, and 4 each having a sequence and a signal that becomes "0" when an alarm occurs are input to G4, and this output is
The disconnection signals 1, 2, 3, and 4 are sent to each power supply unit PWR1, PWR2, PWR3, and PWR4.
これらの投入・切断信号は、投入時“１”、切
断時“０”の信号である。 These closing/cutting signals are "1" when closing and "0" when disconnecting.
［発明の効果］
以上説明のように本発明によつて、電圧アラー
ムの際に発生する可能性のあるシーケンスの逆転
を最小限の時間に抑え、負荷の回路素子の劣化お
よび破壊を防止する効果を有するものである。[Effects of the Invention] As explained above, the present invention has the effect of minimizing the sequence reversal that may occur in the event of a voltage alarm, and preventing deterioration and destruction of load circuit elements. It has the following.
第１図ａは本発明による投入・切断のシーケン
スを示すタイム・チヤート、第１図ｂは本発明の
一実施例のリレーによる要部回路図、第１図ｃは
本発明の一実施例の論理素子による要部回路図、
第２図は電源システムの機能ブロツク図、第３図
は従来の投入・切断シーケンスを示すタイム・チ
ヤートである。
図において、UPCは電源制御装置、PWR１，
PWR２，PWR３，PWR４は電源ユニツト、Ｋ
１，Ｋ２，Ｋ３，Ｋ４，Koはリレー接点、Ｇ１，
Ｇ２，Ｇ３，Ｇ４はANDゲート、をそれぞれ示
す。
FIG. 1a is a time chart showing the sequence of closing and disconnecting according to the present invention, FIG. 1b is a circuit diagram of a main part of a relay according to an embodiment of the present invention, and FIG. 1c is a diagram showing a main part of a relay according to an embodiment of the present invention. Main circuit diagram with logic elements,
FIG. 2 is a functional block diagram of the power supply system, and FIG. 3 is a time chart showing a conventional turn-on/turn-off sequence. In the figure, UPC is the power control device, PWR1,
PWR2, PWR3, PWR4 are power supply units, K
1, K2, K3, K4, Ko are relay contacts, G1,
G2, G3, and G4 indicate AND gates, respectively.
Claims (1)
および状態の監視を行う電源制御装置において、 前記複数の電源ユニツトの電源投入・切断を予
め定められたシーケンスに従つて制御するシーケ
ンス制御回路と、 前記複数の電源ユニツトの発する、電源の異常
を示すアラーム信号を検出するアラーム検出回路
と、 前記アラーム信号検出回路がアラーム信号を検
出したとき前記電源ユニツトに一斉に切断信号を
送出する切断信号一斉送出回路とを備え、 前記電源ユニツトのアラームが発生したときに
は、前記予め定められた切断のシーケンスに拘ら
ず全ての電源ユニツトに対して一斉に切断信号を
送出するよう構成したことを特徴とする電源制御
方式。[Scope of Claims] 1. A power supply control device that controls power-on and power-off of a plurality of power supply units and monitors their states, the power supply control device controlling power-on and power-off of the plurality of power supply units according to a predetermined sequence. a sequence control circuit; an alarm detection circuit that detects an alarm signal indicating an abnormality in the power supply issued by the plurality of power supply units; and when the alarm signal detection circuit detects an alarm signal, sends a disconnection signal to the power supply units all at once. and a circuit for simultaneously sending out a disconnection signal to all the power supply units, and when an alarm occurs in the power supply unit, the disconnection signal is transmitted to all the power supply units at once, regardless of the predetermined disconnection sequence. Characteristic power control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59165903A JPS6143318A (en) | 1984-08-08 | 1984-08-08 | Power supply control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59165903A JPS6143318A (en) | 1984-08-08 | 1984-08-08 | Power supply control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6143318A JPS6143318A (en) | 1986-03-01 |
| JPH0323930B2 true JPH0323930B2 (en) | 1991-04-02 |
Family
ID=15821182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59165903A Granted JPS6143318A (en) | 1984-08-08 | 1984-08-08 | Power supply control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6143318A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0783539B2 (en) * | 1988-03-09 | 1995-09-06 | 沖電気工業株式会社 | Power control method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5585923A (en) * | 1978-12-25 | 1980-06-28 | Toshiba Corp | Automatic power supply interrupter |
| JPS57106919A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Emergency power source breaking system of electronic computer system |
| JPS599727A (en) * | 1982-07-07 | 1984-01-19 | Toshiba Corp | Alarm output device |
-
1984
- 1984-08-08 JP JP59165903A patent/JPS6143318A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5585923A (en) * | 1978-12-25 | 1980-06-28 | Toshiba Corp | Automatic power supply interrupter |
| JPS57106919A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Emergency power source breaking system of electronic computer system |
| JPS599727A (en) * | 1982-07-07 | 1984-01-19 | Toshiba Corp | Alarm output device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6143318A (en) | 1986-03-01 |
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