JPH03236265A - Ic package and manufacture thereof - Google Patents

Ic package and manufacture thereof

Info

Publication number
JPH03236265A
JPH03236265A JP3316290A JP3316290A JPH03236265A JP H03236265 A JPH03236265 A JP H03236265A JP 3316290 A JP3316290 A JP 3316290A JP 3316290 A JP3316290 A JP 3316290A JP H03236265 A JPH03236265 A JP H03236265A
Authority
JP
Japan
Prior art keywords
insulator
package
thin plate
frame
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3316290A
Other languages
Japanese (ja)
Inventor
Katsuhiko Hayashi
克彦 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP3316290A priority Critical patent/JPH03236265A/en
Publication of JPH03236265A publication Critical patent/JPH03236265A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To reduce the thickness of the title package by providing a framelike insulator integrated with the periphery of a thin platelike insulator be mounted with an IC chip and having a conductive layer to be conducted to an electrode pad on the chip. CONSTITUTION:A thin platelike insulator 11 to place an IC chip 13 and a framelike insulator 12 integrated at the periphery of the insulator 11 are formed, for example, of ceramics. A plurality of conductive layers 16 are formed on the periphery of an IC chip placing surface of the insulator 11, a conductive layer 20 is formed in a through hole 19, a conductive layer 21 is further formed from the bottom to the side face, a conductive layer 17 is formed from the surface of the insulator 12 to the side face, and they are conducted. Here, when the thickness of the insulator 11 is d and the entire thickness of the insulators 11, 12 is D, if the insulators 11, 12 are so set as to satisfy the relation of d<=0.5mm or d/D<=0.5 and D<=1.5mm, a most desirable effect is obtained.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、薄型化を図る丁Cパッケージ及びその製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a thin C package and a method for manufacturing the same.

(従来の技術) ICパッケージとして第9図及び第10図に示したよう
な構造のものが知られている。1はICチップ3を搭載
すべき平板状の第1の絶縁体、2は第1の絶縁体1とそ
の周辺部で一体化された枠状の第2の絶縁体でこれら第
1及び第2の絶縁体は例えばセラミック又は樹脂等によ
って構成されている。第1の絶縁体1のICチップ搭載
面の周囲には複数の例えば6個のポンディングパッドを
有する導電層6が端面に向かって形成されると共に、第
2の絶縁体2の表面及び端面には前記導電層6と導通ず
るように同様な導電層7か形成されている。TOチップ
3上に設けられている電極パッド4はボンディングワイ
ヤ5を介して導電層6と導通されており、よって電極パ
ッド4は導電層7と導通されている。このような構造の
ICパッケージは一般にリードレス・セラミックチップ
・キャリア(L CC)として扱かわれて普及している
。チップ搭載後第2の絶縁体2の凹部には樹脂8がモー
ルドされて、又は金属キャップ セラミックキャップ等
が設けられて、ICチップ3は外部雰囲気から保護され
ている。
(Prior Art) IC packages having structures as shown in FIGS. 9 and 10 are known. 1 is a flat plate-shaped first insulator on which an IC chip 3 is to be mounted, and 2 is a frame-shaped second insulator that is integrated with the first insulator 1 at its periphery. The insulator is made of, for example, ceramic or resin. A conductive layer 6 having a plurality of, for example, six, bonding pads is formed around the IC chip mounting surface of the first insulator 1 toward the end surface, and on the surface and end surface of the second insulator 2. A similar conductive layer 7 is formed so as to be electrically conductive with the conductive layer 6. The electrode pads 4 provided on the TO chip 3 are electrically connected to the conductive layer 6 via the bonding wires 5, and therefore the electrode pads 4 are electrically connected to the conductive layer 7. An IC package having such a structure is generally used as a leadless ceramic chip carrier (LCC) and is widely used. After the chip is mounted, a resin 8 is molded into the recessed portion of the second insulator 2, or a metal cap, a ceramic cap, or the like is provided to protect the IC chip 3 from the external atmosphere.

このような構造のICパッケージは従来次のような方法
で製造されている。第11図はそのうちの第1の製造方
法を示すもので、先ず下金型9A内にセラミックグリー
ンシート10を配置し、続いて上金型9Bを下金型9A
に下降することによりグリーンシート10をプレスして
凹状構造を得る。次にメツキ処理を施こして導電層6,
7を形成すればICパッケージが完成する。
An IC package having such a structure has conventionally been manufactured by the following method. FIG. 11 shows the first manufacturing method, in which the ceramic green sheet 10 is first placed in the lower mold 9A, and then the upper mold 9B is placed in the lower mold 9A.
The green sheet 10 is pressed by descending to obtain a concave structure. Next, a plating process is performed to form a conductive layer 6,
7, the IC package is completed.

また第12図は第2の製造方法を示すもので、予め所望
のパターンの導電層を印刷した複数のグリーンシート1
0a、10b、10cを用意し、続いて各グリーンシー
トを積層後シリコン型等を用いた熱プレスを行うことに
より凹状構造を得る。
FIG. 12 shows a second manufacturing method, in which a plurality of green sheets 1 are printed with a conductive layer in a desired pattern in advance.
0a, 10b, and 10c are prepared, and then each green sheet is laminated and hot pressed using a silicon mold or the like to obtain a concave structure.

次にメツキ処理を施こしてICパッケージを完成させる
Next, a plating process is performed to complete the IC package.

このように第9図及び第10図のような構造のICパッ
ケージは、プレス成型を行なうことによって容易に製造
することができる。
As described above, the IC package having the structure shown in FIGS. 9 and 10 can be easily manufactured by press molding.

(発明が解決しようとする課題) ところで従来のICパッケージ及びその製造方法では、
パッケージの特にrCチップを搭載する第1の絶縁体の
厚さを薄く形成したい場合はこれが困難になるという問
題がある。例えば最近脚光を浴びつつあるICカード等
に適用するICを製造しようとした場合、カードの携帯
性から薄型化が望まれているのでこの要望を満たすため
にはICパッケージ自身の薄型化を図らねばならない。
(Problem to be solved by the invention) However, in the conventional IC package and its manufacturing method,
There is a problem in that it becomes difficult to reduce the thickness of the package, especially the first insulator on which the rC chip is mounted. For example, when trying to manufacture an IC for use in IC cards, which have recently been in the spotlight, the card needs to be thinner for portability, so in order to meet this demand, the IC package itself must be made thinner. No.

このためには−例としてICチップ搭載面を構成してい
る第1の絶縁体の厚さは0. 5mm以下に形成したい
要望がある。しかし従来のようにプレス成型を利用した
製造方法ではこのような要求を満たすのは困難である。
For this purpose, for example, the thickness of the first insulator constituting the IC chip mounting surface is 0. There is a desire to form it to 5 mm or less. However, it is difficult to meet these requirements using conventional manufacturing methods that utilize press molding.

本発明は以上のような問題に対処してなされたもので、
薄型化を可能にしたICパッケージ及びその製造方法を
提供することを目的とするものである。
The present invention has been made in response to the above-mentioned problems.
The object of the present invention is to provide an IC package that can be made thinner and a method for manufacturing the same.

[発明の構成] (課題を解決するための手段) 上記目的を達成するために本発明のICパッケージは、
ICチップを搭載すべき薄板状絶縁体部と、この薄板状
絶縁体部の周辺部に固定され前記ICチップ上の電極パ
ッドと導通される導電層を有する枠状絶縁体部とから成
ることを特徴とするものである。
[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the IC package of the present invention has the following features:
It consists of a thin plate-like insulator on which an IC chip is mounted, and a frame-like insulator having a conductive layer fixed to the periphery of the thin plate-like insulator and electrically connected to the electrode pads on the IC chip. This is a characteristic feature.

また前記薄板状絶縁体部の厚さdは、d≦0.5皿の関
係に設定されることが望ましい。
Further, it is preferable that the thickness d of the thin plate-like insulator portion be set in a relationship such that d≦0.5.

さらに薄板状絶縁体部及び枠状絶縁体部の全体厚さをD
としたとき、d/D≦0.5かつD≦1.5mmの関係
に設定されることが望ましい。
Furthermore, the overall thickness of the thin plate-like insulator part and the frame-like insulator part is D
In this case, it is desirable to set the relationship of d/D≦0.5 and D≦1.5 mm.

また本発明のICパッケージの製造方法は、ICチップ
を搭載すべき薄板状絶縁体を用意する工程と、この薄板
状絶縁体とほぼ等しい周辺形状を有する枠状絶縁体を用
意する工程と、薄板状絶縁体の周辺部に枠状絶縁体を重
ね両者を一体化する工程とから成ることを特徴とするも
のである。
Further, the method for manufacturing an IC package of the present invention includes a step of preparing a thin plate-like insulator on which an IC chip is to be mounted, a step of preparing a frame-like insulator having a peripheral shape approximately equal to that of the thin plate-like insulator, This method is characterized by the step of stacking a frame-shaped insulator on the peripheral portion of the frame-shaped insulator and integrating the two.

また前記薄板状絶縁体及び枠状絶縁体としてはセラミッ
クグリーンシートを用いることが望ましい。さらに両絶
縁体としては焼結セラミックを用いることができる。さ
らにまた両絶縁体を一体化する工程は熱処理を含むこと
ができる。
Furthermore, it is desirable to use ceramic green sheets as the thin plate-like insulator and the frame-like insulator. Furthermore, sintered ceramic can be used as both insulators. Furthermore, the step of integrating both insulators can include heat treatment.

(作 用) ICチップを搭載すべき絶縁体部は薄板状から成ってい
るのでICパッケージの薄型化を図ることができる。ま
た前記のように、d≦0. 5mmの関係に又はd/D
≦0,5かつD≦1. 5nmnの関係に設定すること
により、最も望ましい効果が得られる。
(Function) Since the insulator portion on which the IC chip is mounted is made of a thin plate, the IC package can be made thinner. Moreover, as mentioned above, d≦0. 5mm relationship or d/D
≦0,5 and D≦1. By setting the relationship of 5 nm to 5 nm, the most desirable effect can be obtained.

またICパッケージを製造する場合、薄板状絶縁体と枠
状絶縁体とを別個に用意し、両絶縁体を一体化すること
によりICパッケージを製造するようにしたので、薄型
化されたICパッケージを容易に製造することができる
。両絶縁体としてはセラミックグリーンシートを又は焼
結セラミックを用いることが望ましい。さらに両絶縁体
を一体化する工程は熱処理を含むことが望ましい。
In addition, when manufacturing an IC package, a thin plate insulator and a frame insulator are prepared separately, and the IC package is manufactured by integrating both insulators, so that a thinner IC package can be produced. It can be easily manufactured. It is desirable to use ceramic green sheets or sintered ceramics as both insulators. Furthermore, it is desirable that the step of integrating both insulators includes heat treatment.

(実施例) 以下図面を参照して本発明の詳細な説明する。(Example) The present invention will be described in detail below with reference to the drawings.

第1図及び第2図は本発明のICパッケージの第1の実
施例を示す斜視図及び断面図で、11はICチップ13
を搭載すべき薄板状絶縁体、12は薄板状絶縁体11と
その周辺部で一体化された枠状絶縁体でこれら両絶縁体
は例えばセラミック又は樹脂等によって構成されている
。薄板状絶縁体11のICチップ搭載面の周囲には複数
の例えば6個のポンディングパッドを有する導電層16
が端面に向かって形成されていると共に、厚さ方向に設
けられたスルーホール19には導電層20が形成され、
さらに底面から側面にかけて導電層21が形成されてい
る。また枠状絶縁体12の表面から側面にかけて導電層
17が形成されている。
1 and 2 are a perspective view and a sectional view showing a first embodiment of the IC package of the present invention, and 11 is an IC chip 13.
The thin plate-shaped insulator 12 on which the thin plate-shaped insulator is mounted is a frame-shaped insulator that is integrated with the thin plate-shaped insulator 11 at its peripheral portion, and both of these insulators are made of, for example, ceramic or resin. A conductive layer 16 having a plurality of, for example, six bonding pads, is arranged around the IC chip mounting surface of the thin plate insulator 11.
is formed toward the end face, and a conductive layer 20 is formed in the through hole 19 provided in the thickness direction,
Furthermore, a conductive layer 21 is formed from the bottom surface to the side surfaces. Further, a conductive layer 17 is formed from the surface to the side surface of the frame-shaped insulator 12.

これら各導電層16,20,21.17は互いに導通し
ている。ICチップ13上に設けられている電極パッド
14はポンデイグワイヤ15を介して導電層16と導通
されており、よって電極パッド14は導電層17と導通
されている。18はICチップ13を覆う樹脂で、枠状
絶縁体12の凹部内にモールドされてICチップ13を
外部雰囲気から保護している。
These conductive layers 16, 20, 21.17 are electrically connected to each other. The electrode pads 14 provided on the IC chip 13 are electrically connected to the conductive layer 16 via the bonding wire 15, and therefore the electrode pads 14 are electrically connected to the conductive layer 17. A resin 18 covers the IC chip 13, and is molded into the recess of the frame-shaped insulator 12 to protect the IC chip 13 from the external atmosphere.

ここで薄板状絶縁体11の厚さをd、薄板状絶縁体11
及び枠状絶縁体12の全体厚さをDとすると、各絶縁体
11.12をd≦0.5mmの関係を満足するように設
定したとき、又はd/D≦0.5かつD≦1.5mmの
関係に設定したとき、最も望ましい効果を得ることがで
きる。しかし、d≦0.2mmで、d/D≦0.5かつ
D≦1、 0mmの関係に設定してもよい効果が得られ
る。
Here, the thickness of the thin plate insulator 11 is d, and the thickness of the thin plate insulator 11 is d.
When the overall thickness of the frame-shaped insulator 12 is D, each insulator 11.12 is set to satisfy the relationship d≦0.5 mm, or d/D≦0.5 and D≦1. The most desirable effect can be obtained when the relationship is set to .5 mm. However, when d≦0.2 mm, good effects can be obtained by setting the relationship of d/D≦0.5 and D≦1, 0 mm.

このようにICチップ13を搭載すべき絶縁体11の厚
さを薄く形成することにより、ICパッケージの薄型化
を図ることができる。このような薄型化ICパッケージ
は以下に示すような本発明のICパッケージの製造方法
によって実現できる。
By forming the insulator 11 on which the IC chip 13 is to be mounted thin in this manner, the IC package can be made thinner. Such a thin IC package can be realized by the method of manufacturing an IC package of the present invention as described below.

第5図は本発明のICパッケージの製造方法の第1の実
施例を示すもので、特に低温焼結系によって製造する場
合を示している。
FIG. 5 shows a first embodiment of the method for manufacturing an IC package of the present invention, and particularly shows the case where the IC package is manufactured using a low-temperature sintering system.

(A)先ず複数のセラミックグリーンシート(未焼結セ
ラミック)12a、12b、12cを用意し、積層した
後熱プレスによって一体化する。
(A) First, a plurality of ceramic green sheets (unsintered ceramic) 12a, 12b, and 12c are prepared, laminated, and then integrated by hot pressing.

次に一体化されたシート12′を金型打ち抜きによって
枠状に成型した後焼結を行う。これによって枠状絶縁体
12が形成される。枠の表面及び側面には所望の段階で
導電層17が形成されている。
Next, the integrated sheet 12' is formed into a frame shape by die punching, and then sintered. As a result, a frame-shaped insulator 12 is formed. A conductive layer 17 is formed on the surface and side surfaces of the frame at desired stages.

またグリーンシートは必ずしも複数枚必要ではな(所定
厚さが得られれば1枚でもよい。
Further, a plurality of green sheets are not necessarily required (one green sheet may be used as long as a predetermined thickness can be obtained).

(B)グリーンシート11−を用意し、スルーホール1
9を所定数例えば6個パンチングした後、スルーホール
19に導体ペースト(Ag、Ag−Pd、Au、Cu、
Pt系金属等)を充てんして熱プレスする。次に81の
ようにシートの表面及び裏面に導電層16.20を印刷
後焼結を行なう。
(B) Prepare green sheet 11- and through hole 1
After punching a predetermined number of holes 9, for example, 6, a conductive paste (Ag, Ag-Pd, Au, Cu,
(Pt-based metal, etc.) and hot press. Next, as shown in 81, conductive layers 16 and 20 are printed on the front and back surfaces of the sheet and then sintered.

又はB2のようにシートを一度焼結した後に、表面及び
裏面に導電層16.20を印刷後焼結を行なう。これに
よって薄板状絶縁体11が形成される。
Alternatively, as in B2, after sintering the sheet, conductive layers 16 and 20 are printed on the front and back surfaces, and then sintering is performed. As a result, a thin plate-like insulator 11 is formed.

(C)(A)及び(B)の各工程で形成された枠状絶縁
体12及び薄板状絶縁体11を用意し、薄板状絶縁体1
1の周辺部に枠状絶縁体12を耐熱性接着剤又はガラス
ボンド等の接着部材を介して重ねた後、熱処理を行なっ
て両絶縁体を一体化する。側面の電極はペースト印刷を
行って焼結して導通させる。次に薄板状絶縁体11の略
中央面にICチップ13を搭載し、ワイヤボンディング
を行なった後、樹脂18のモールドを行なう。以上によ
って第1図及び第2図に示したような構造のICパッケ
ージが得られる。
(C) Prepare the frame-shaped insulator 12 and the thin plate-shaped insulator 11 formed in each step of (A) and (B), and
After a frame-shaped insulator 12 is stacked on the peripheral portion of the insulator 1 with an adhesive member such as a heat-resistant adhesive or a glass bond interposed therebetween, a heat treatment is performed to integrate the two insulators. The side electrodes are printed with paste and sintered to make them conductive. Next, an IC chip 13 is mounted approximately on the center surface of the thin plate-like insulator 11, wire bonding is performed, and then molding with resin 18 is performed. Through the above steps, an IC package having the structure shown in FIGS. 1 and 2 is obtained.

第6図は本発明のICパッケージの製造方法の第2の実
施例を示すもので、特に高温焼結系(アルミナ系)によ
って製造する場合を示している。
FIG. 6 shows a second embodiment of the method for manufacturing an IC package of the present invention, and particularly shows the case where the IC package is manufactured using a high temperature sintering system (alumina system).

(A)前記第1の実施例による(A)の工程と同様な方
法で枠状絶縁体12を形成することができるので、説明
は省略する。
(A) Since the frame-shaped insulator 12 can be formed by the same method as the step (A) according to the first embodiment, the explanation will be omitted.

(B)前記第1の実施例による(B)の工程において、
スルーホール19をパンチングした後、B1のようにシ
ート11′の焼結を行い、次にシートの表面及び裏面に
導体ペースト(Ag、Ag−Pd、Au、Cu、Pt系
金属等)を印刷して導電層16.20を形成する。又は
B2のように、スルーホール19をパンチングした後シ
ートの表面及び裏面に導体ペースh (W、Mo系金属
等)を印刷して導電層16.20を形成し、続いて焼結
を行う。これによって薄板状絶縁体11が形成される。
(B) In the step (B) according to the first embodiment,
After punching the through holes 19, the sheet 11' is sintered as shown in B1, and then conductive paste (Ag, Ag-Pd, Au, Cu, Pt metal, etc.) is printed on the front and back surfaces of the sheet. A conductive layer 16.20 is then formed. Alternatively, as in B2, after punching through holes 19, a conductive paste h (W, Mo-based metal, etc.) is printed on the front and back surfaces of the sheet to form conductive layers 16 and 20, followed by sintering. As a result, a thin plate-like insulator 11 is formed.

(C)前記第1の実施例による(C)の工程と同様な方
法で両絶縁体11.12を一体化してICパッケージを
得ることができるので、説明は省略する。
(C) Since the IC package can be obtained by integrating both the insulators 11 and 12 in the same manner as the step (C) according to the first embodiment, the explanation will be omitted.

第3図及び第4図は本発明のICパッケージの第2の実
施例を示す斜視図及び断面図で、第1図及び第2図の第
1の実施例に比べて、枠状絶縁体12の厚さ方向に予め
スルーホール19を設けて導電層20を形成すると共に
、この導電層20と導通ずるようにその表面に導電層1
7を形成した点が異なっている。このような薄型化IC
パッケージは以下に示すような本発明のICパッケージ
の製造方法によって実現できる。
3 and 4 are a perspective view and a sectional view showing a second embodiment of the IC package of the present invention. A conductive layer 20 is formed by providing a through hole 19 in advance in the thickness direction, and a conductive layer 1 is formed on the surface of the conductive layer 20 so as to be electrically conductive with the conductive layer 20.
The difference is that 7 was formed. Such thin IC
The package can be realized by the method of manufacturing an IC package of the present invention as shown below.

第7図は本発明のICパッケージの製造方法の第3の実
施例を示すものである。
FIG. 7 shows a third embodiment of the method for manufacturing an IC package of the present invention.

(A)Alのように予めスルーホール19a。(A) Through hole 19a in advance like Al.

19b、19cを各々形成しこれらに導電層20a、2
0b、20cを形成した例えば3枚の焼結セラミック2
2a、22b、22cを用意し、これらを積層して22
のように一体化させる。又はA2のように複数の焼結セ
ラミックを積層して一体化した後パンチングしてスルー
ホール19を形成し、次にスルーホール19に導電層2
0を形成する。これによって枠状絶縁体12が形成され
る。
19b and 19c are respectively formed and conductive layers 20a and 20a are formed thereon.
For example, three sintered ceramics 2 formed with 0b and 20c
Prepare 2a, 22b, 22c and stack them to form 22
unify it like this. Alternatively, as shown in A2, multiple sintered ceramics are stacked and integrated, then punched to form a through hole 19, and then a conductive layer 2 is formed in the through hole 19.
form 0. As a result, a frame-shaped insulator 12 is formed.

(B)焼結セラミックの表面に導電層16を印刷するこ
とにより、薄板状絶縁体11を形成する。
(B) A thin plate-like insulator 11 is formed by printing a conductive layer 16 on the surface of the sintered ceramic.

(C)(A)及び(B)の各工程で形成された枠状絶縁
体12及び薄板状絶縁体11を用意し、ガラスフリット
等の接着部材を介して両絶縁体11.12を重ねて焼結
して一体化する。次に工Cチップ13を搭載し、ワイヤ
ボンディングを行なった後、樹脂18のモールドを行う
。以上によって第3図及び第4図に示したような構造の
ICパッケージが得られる。
(C) Prepare the frame-shaped insulator 12 and the thin plate-shaped insulator 11 formed in each step of (A) and (B), and overlap both insulators 11 and 12 with an adhesive member such as glass frit. Sinter and integrate. Next, the C-chip 13 is mounted, wire bonding is performed, and then resin 18 is molded. Through the above steps, an IC package having the structure shown in FIGS. 3 and 4 is obtained.

また従来知られているグリーンシートを積層することに
よって前記(A)及び(B)で形成された枠状絶縁体1
2及び薄板状絶縁体11に相当した各シートを形成し、
これら各シートを重ねて一括焼結することによっても第
3図及び第4図に示したような構造のICパッケージが
得られる。
Moreover, the frame-shaped insulator 1 formed by the above (A) and (B) by laminating conventionally known green sheets.
2 and a sheet corresponding to the thin plate-like insulator 11,
An IC package having the structure shown in FIGS. 3 and 4 can also be obtained by stacking these sheets and sintering them all at once.

このように本発明のICパッケージ及びその製造方法の
各実施例によれば、薄型化されたICパッケージを得る
ことができ、又このように薄型化されたICパッケージ
を容易に製造することができる。
As described above, according to the embodiments of the IC package and the manufacturing method thereof of the present invention, it is possible to obtain a thinned IC package, and it is also possible to easily manufacture such a thinned IC package. .

本又実施例で示した導電層の数及び配置パターンは一例
を示したもので、目的、用途等に応じて種々の変形が可
能である。また導電層の形成はスルーホールを介して、
又は側面を介して任意の選択が可能であり、いずれの構
造においても薄型化されたICパッケージを得ることが
できる。
The number of conductive layers and the arrangement pattern shown in this embodiment are merely examples, and various modifications can be made depending on the purpose, use, etc. In addition, the conductive layer is formed through a through hole.
Alternatively, any structure can be selected via the side surface, and a thinned IC package can be obtained in either structure.

さらに実施例ではICパッケージを個別に得る例で示し
たが、第8図に示したように多数個分が形成された枠状
絶縁体12及びこれに対応した薄板状絶縁体11を用意
し、両絶縁体12.11を重ねて一体化した後ワイヤー
ソー等によって個別に分割することによって多数個取り
も容易に行なうことができる。
Further, in the embodiment, an example was shown in which IC packages were obtained individually, but as shown in FIG. By stacking and integrating the two insulators 12 and 11 and then dividing them into individual pieces using a wire saw or the like, it is possible to easily produce a large number of pieces.

[発明の効果] 以上述べたように本発明によれば、予め薄板状絶縁体及
び枠状絶縁体を別個に用意し、両絶縁体を一体化してI
Cパッケージを製造するようにしたので、薄型化された
ICパッケージを容易に得ることができる。
[Effects of the Invention] As described above, according to the present invention, a thin plate-like insulator and a frame-like insulator are prepared separately in advance, and both insulators are integrated.
Since the C package is manufactured, a thinned IC package can be easily obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明のICパッケージの第1の実
施例を示す斜視図及び断面図、第3図及び第4図は本発
明のICパッケージの第2の実施例を示す斜視図及び断
面図、第5図(A)乃至(C)は本発明のICパッケー
ジの製造方法の第1の実施例を示す工程図、第6図(A
)乃至(C)は本発明のICパッケージの製造方法の第
2の実施例を示す工程図、第7図(A)乃至(C)は本
発明のICパッケージの製造方法の第3の実施例を示す
工程図、第8図は本発明のICパッケージの製造方法の
変形例を示す工程図、第9図及び第10図は従来のIC
パッケージを示す斜視図及び断面図、第11図及び第1
2図は従来のICパッケージの製造方法を示す工程図で
ある。 1・・・薄板状絶縁体、12・・・枠状絶縁体、3・・
・ICチップ、15・・・ボンディングワイヤ、6.1
7.20・・・導電層、 8・・・樹脂(絶縁体)、19・・・スルーホール。
1 and 2 are perspective views and sectional views showing a first embodiment of the IC package of the present invention, and FIGS. 3 and 4 are perspective views showing a second embodiment of the IC package of the present invention. 5(A) to 5(C) are process diagrams showing the first embodiment of the method for manufacturing an IC package of the present invention, and FIG. 6(A) is a cross-sectional view.
) to (C) are process diagrams showing a second embodiment of the method for manufacturing an IC package of the present invention, and FIGS. 7(A) to (C) are process diagrams showing a third embodiment of the method for manufacturing an IC package of the present invention. FIG. 8 is a process diagram showing a modified example of the method for manufacturing an IC package of the present invention, and FIGS. 9 and 10 are process diagrams showing a conventional IC package manufacturing method.
A perspective view and a sectional view showing the package, FIGS. 11 and 1
FIG. 2 is a process diagram showing a conventional method for manufacturing an IC package. 1... Thin plate-shaped insulator, 12... Frame-shaped insulator, 3...
・IC chip, 15...bonding wire, 6.1
7.20... Conductive layer, 8... Resin (insulator), 19... Through hole.

Claims (7)

【特許請求の範囲】[Claims] (1)ICチップを搭載すべき薄板状絶縁体部と、この
薄板状絶縁体部の周辺部に一体化され前記ICチップ上
の電極パッドと導通される導電層を有する枠状絶縁体部
とから成ることを特徴とするICパッケージ。
(1) A thin plate-like insulator portion on which an IC chip is to be mounted, and a frame-like insulator portion having a conductive layer integrated into the peripheral portion of the thin plate-like insulator portion and electrically connected to the electrode pads on the IC chip. An IC package characterized by comprising:
(2)薄板状絶縁体部の厚さをdとしたとき、d≦0.
5mmの関係に設定された請求項1記載のICパッケー
ジ。
(2) When the thickness of the thin plate insulator portion is d, d≦0.
The IC package according to claim 1, wherein the IC package is set to have a relationship of 5 mm.
(3)薄板状絶縁体部及び枠状絶縁体部の全体の厚さを
Dとしたとき、d/D≦0.5かつD≦1.5mmの関
係に設定された請求項1記載のICパッケージ。
(3) The IC according to claim 1, wherein the IC is set to have a relationship of d/D≦0.5 and D≦1.5 mm, where D is the overall thickness of the thin plate-like insulator portion and the frame-like insulator portion. package.
(4)ICチップを搭載すべき薄板状絶縁体を用意する
工程と、この薄板状絶縁体とほぼ等しい周辺形状を有す
る枠状絶縁体を用意する工程と、薄板状絶縁体の周辺部
に枠状絶縁体を重ね両者を一体化する工程とから成るこ
とを特徴とするICパッケージの製造方法。
(4) A step of preparing a thin plate-like insulator on which an IC chip is to be mounted, a step of preparing a frame-like insulator having a peripheral shape approximately equal to that of the thin-plate insulator, and a step of preparing a frame-like insulator having a peripheral shape approximately equal to that of the thin plate-like insulator; 1. A method for manufacturing an IC package, comprising the steps of stacking two insulators and integrating the two.
(5)薄板状絶縁体及び枠状絶縁体としてセラミックグ
リーンシートを用いる請求項4記載のICパッケージの
製造方法。
(5) The method for manufacturing an IC package according to claim 4, wherein a ceramic green sheet is used as the thin plate-like insulator and the frame-like insulator.
(6)薄板状絶縁体及び枠状絶縁体として焼結セラミッ
クを用いる請求項4記載のICパッケージの製造方法。
(6) The method for manufacturing an IC package according to claim 4, wherein sintered ceramic is used as the thin plate-like insulator and the frame-like insulator.
(7)薄板状絶縁体及び枠状絶縁体を一体化する工程が
熱処理を含む工程から成る請求項4記載のICパッケー
ジの製造方法。
(7) The method for manufacturing an IC package according to claim 4, wherein the step of integrating the thin plate-like insulator and the frame-like insulator comprises a step including heat treatment.
JP3316290A 1990-02-14 1990-02-14 Ic package and manufacture thereof Pending JPH03236265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3316290A JPH03236265A (en) 1990-02-14 1990-02-14 Ic package and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3316290A JPH03236265A (en) 1990-02-14 1990-02-14 Ic package and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03236265A true JPH03236265A (en) 1991-10-22

Family

ID=12378862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3316290A Pending JPH03236265A (en) 1990-02-14 1990-02-14 Ic package and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03236265A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011129161A1 (en) * 2010-04-13 2011-10-20 株式会社村田製作所 Module substrate, production method for module substrate, and terminal connection board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011129161A1 (en) * 2010-04-13 2011-10-20 株式会社村田製作所 Module substrate, production method for module substrate, and terminal connection board
US9192051B2 (en) 2010-04-13 2015-11-17 Murata Manufacturing Co., Ltd. Module substrate, module-substrate manufacturing method, and terminal connection substrate

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