JPH03236237A - Method and apparatus for forming wiring - Google Patents

Abstract

PURPOSE:To make the throughput in forming a wiring excellent without steps for applying, exposing and developing an organic light sensitive material and the like and to make it possible to cope with the small amount of production of many kinds of ICs by sequentially performing two steps for forming an active layer corresponding to the desired wiring pattern on the surface of the insulating film on a substrate and for selective CVD for metal. CONSTITUTION:A wafer 109 is conveyed into an electron-beam projecting chamber 116 by a wafer conveying mechanism. Thus the wafer is set. An electron beam is deflected, and a pattern is drawn. After the wafer 109 is conveyed into a film forming chamber 102 and set, Ar gas is introduced on the rear surface side of the wafer 109 through a gas introducing pipe 111. H2 is introduced into the film forming chamber 102. The wafer 109 receives infrared rays from wafer heating halogen lamps 106 through a quartz window 114. The wafer 109 is heated to a specified temperature. After the wafer 109 is heated to the specified temperature, WF6 gas is introduced in addition to the H2 gas. Thus W is selectively grown. The wafer 109 is cooled. The wafer 109 is taken out of the chamber, and the wiring forming step of the W is finished.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wiring forming method and an apparatus therefor, and in particular, the present invention relates to a wiring forming method and an apparatus therefor. The present invention relates to a wiring forming method suitable for forming a pattern and a wiring forming apparatus for carrying out the method.

[Conventional technology]

With the effects of mass production of semiconductors, the unit price per chip is decreasing and functionality is increasing year by year, and the number of devices equipped with semiconductors is expanding to include products that did not previously use semiconductors, such as automobiles and air conditioners. .

In particular, facsimiles, cameras, OA equipment, etc.
The market cannot survive unless the product is equipped with a chip microcontroller and increases its added value.
(Application 5epecjficIn
Demand for integrated C1rcuits (hereinafter referred to as ASICs) continues to expand. ASICs can be broadly divided into two types depending on their specific applications. In other words, custom ICs and specific application ICs are general-purpose products (App-1 ICs).
ation S peeific S standard
Product (hereinafter referred to as ASSP).

A custom IC is an IC made by an LSI manufacturer in response to a user's order, and an ASSP is a type of general-purpose product that is planned and designed by an LSI manufacturer themselves for a large number of users in a specific field. Therefore, the latter is the production number 1
In contrast to the production of a small variety of products of about 1,000,000 units, the former requires the production of a wide variety of products with a production volume of 100,000 units or less from users. Furthermore, as products become more diversified year by year, it is expected that the demand for production of a wide variety of products in small quantities will further increase.

However, the wiring formation method conventionally used in ASIC production is limited to LS1 for mass production. That is, D.R.A.
Memories such as M and SRAM, general-purpose microcomputers,
The method was exactly the same as that used with CPUs and the like. That is, the second
As shown in the process flow diagram shown in the figure, wiring is formed through several steps: AQ sputtering film formation → organic photosensitive material (hereinafter referred to as resist) coating and baking → exposure → development → etching of the AQ film and removal of the resist. was.

In contrast to the above-mentioned conventional techniques, a method has been reported in which wiring is drawn directly on an insulating film using a focused laser beam, which does not require not only a resist but also an exposure mask. This method heats the surface of the insulating film using focused laser light.
Raw material gases Cr(Co), W(Co), Mo(
Co) s t T X CQ4 I triisobutyl-aluminum
m, T I B A: l, bis (1, 1, 1, 5゜5
．． 5-hexafluoro-2,4-pentane diionate)
Copper (If) (bis-(1,l,1,5,5゜5-he
xafluoro-2,4-pentanediona
te) copper (If )) etc. as raw materials,
Cr film, W film, Mo film, Ti film, AQ film, Cu film, respectively.
It forms a film.

Previous literature on direct writing of metals with a laser beam includes Applied Physics Letters, Vol. 45 (1984), pp. 617 to 61.
9 pages (Appl, phys.

Lett, 45, 617-619 (1984)] and Applied Physics Letters, Vol. 46 (1984)].
985), pp. 204-206 [Appl.

Phys, Lett, 46, 204-206 (198
5) Examples include E.

Next, metal selective CVD will be described as one process used in the wiring forming method of the present invention, although it is not directly related to conventional wiring forming methods.

This method originally consisted of connection holes (contact holes or through holes) provided in interlayer insulating films to connect upper and lower interconnections, which became more apparent as LSIs became more highly integrated.
This is a technology developed to improve metal-embedded housing, and in particular, selective CVD of W is the method that is most expected to be put into practical use.

W selection CVD is performed on an insulating film (S) heated to 250°C or higher.
Tungsten hexafluoride (WFt) gas and hydrogen (
H2) By introducing and contacting a mixed gas with a gas, and performing one of the following reactions.

This is a method of growing a W film on an underlying Si or metal (here, the case of Si is shown).

WF, +3H2→W+6HF ・・・・・・(
2) On an insulating film such as Sin2, the reaction (1) does not occur, and the reaction (2) does not proceed at temperatures below 700°C, so W selectively grows only on the Sl, forming the above-mentioned fine connection hole. In embedding, selective filling will be accomplished.

Literature that has been described so far regarding CVD of W selection includes Journal of Electrochemical Society, Vol. 131 (1984), pp. 1427 to 1433.
Page [J, Electrochem.

Soc, 131, 1984. pp1427-1433]
Proceedings of VLSI Multilevel Interconnection Conference, June 1987, pp. 132-137 (Proc.
VLSI Multilevel Interc
connection conference, ju
ne 1987.

Examples include PP132-13'73.

Recently, SiH4 has been used instead of H2 as a reducing gas.
A method using a system gas has been reported. For example, EC5
This method is described in the proceedings of the Japan Chapter 1st Symposium (1988) r CVD Technology for Very LSI, pages 48 to 65.

If this method is used, the substrate heating temperature will be 250 to 320°C.
It is possible to perform high-speed film formation at such low temperatures. In addition, in the case of this method, selectivity is lost at temperatures above 340° C., and selective filling of holes cannot be performed.

[Problem to be solved by the invention]

Conventional wiring technology using the above-mentioned resist is excellent in terms of high integration, miniaturization, and throughput improvement when mass producing the same product type, but it is not suitable for ASICs from users who request high-mix production in small quantities. , the conventional wiring formation method with a large number of steps is too costly, and therefore LSI
There was a problem in that manufacturers could only accept orders for products that exceeded a certain production number.

On the other hand, as mentioned earlier, a technique has also been reported in which metal wiring is drawn directly on the insulating film using a focused laser beam without using a resist, but this method only draws metal wiring on the spot of the laser beam. Since a metal film cannot be formed, it takes a considerable amount of time to scan the entire wiring pattern with a laser beam. Therefore, with this technique, L
It is practically impossible to form the SI wiring itself, and this wiring technology is currently used only for a small portion of the entire wiring, such as wiring correction or mask white spot correction. In order to use it for wiring formation, it is necessary to consider not only the reduction in the number of steps in wiring formation but also the throughput of wiring formation itself, but the above method does not take this point into consideration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring forming method that has good wiring formation throughput, reduces the number of steps in wiring formation, and is compatible with low-volume, high-mix production of ICs.

[Means to solve the problem]

In order to achieve the above object, the present invention eliminates the processes of resist coating, exposure, development, and metal film etching as a specific measure to reduce the number of steps in wiring formation, and forms a metal wiring pattern on an insulating film. It is designed to be formed directly. Furthermore, the present invention dramatically improves the metal film formation speed compared to the conventional wiring forming method that uses direct drawing of wiring using a laser beam without using a resist or a mask.

That is, in the present invention, in order to achieve the above object, in a method of directly forming a wiring pattern on an insulating film on a substrate, an active layer corresponding to a desired wiring pattern is formed on the surface of an insulating film on the substrate. The two processes of formation (ii) metal selection CVD are performed sequentially.

Regarding the formation of the active layer on the insulating film in (i) of the process described in L, a method of scanning an electron beam focused on the surface of the insulating film can be used.

Furthermore, the sensitivity of active layer formation to the electron beam can be improved by previously treating the surface of the insulating film with halogen gas plasma before scanning with the electron beam.

Further, regarding the formation of the active layer (i), a method of scanning an ion beam focused on the surface of the insulating film can also be used.

In the method using the electron or ion beam described above,
At the current beam current density level, the scanning speed is approximately the same as or slightly slower than the scanning speed required for exposure using a regular electron beam exposure resist, and the time required to form the active layer is: Although it varies depending on the desired wiring pattern and the size of the target wafer, it usually takes from several tens of minutes to several hours per wafer. Therefore, the total time required to form the active layer per wafer and the time required to form the metal film by metal selective CVD (usually about several minutes) is the same as the time required to form wiring by direct metal writing with a laser beam. Several orders of magnitude smaller than
This is within the range of practical use as a wiring formation method for a small number of chips.

If an electron beam or ion beam device with a current density higher than the current value is developed in the future, it will be possible to further shorten the time required for forming the wiring.

Furthermore, as a method for forming an active layer on the surface of an insulating film in (i) above, the surface of the insulating film is surface-treated with halogen plasma, and then light is irradiated in an exposure device, and only the irradiated portion is subjected to a photochemical reaction. It is also possible to use an activation method. Compared to the beam scanning method mentioned earlier, this method requires a mask (called a reticle in commonly used reduced projection exposure equipment), just like when using a regular ultraviolet exposure resist. Although this is a drawback, the time required to form the active layer per unifer is about several minutes, and the throughput is significantly improved compared to the method using beam scanning.

Therefore, it is considered preferable to use this method as a wiring forming method for cases where the number of chips to be produced is larger than that of ICs produced by forming active layers using electron beams or ion beams. As is clear from comparing FIG. 1 and FIG. 2, which show the wiring formation process of the present invention and the conventional technology, this method requires a large number of wiring formation steps compared to the conventional process using resist. It is possible to reduce the

However, even if any active layer formation method such as electron beam or ion beam is used, as long as the wiring process is performed by selective CVD of the metal used in the present invention, it is not suitable for LSIs aiming for high integration and miniaturization. Not suitable. This means that during selective CVD of metals, the direction of film growth is as shown in Figures 1(c) and (d).
This is because the film grows not only in the vertical direction but also in the horizontal direction, as shown in FIG.

Next, regarding the metal selection CVD process (1i) above, the most well-known selection process is tungsten W.
VD, that is, a single-stage C in which a mixed gas of WFG and a reducing gas such as H2 or SiH4 is flowed over a heated substrate in a CVD reaction vessel set up for selective CVD.
Using a VD method, or using a bifurcated CVD method in which WF alone or diluted with an inert gas such as Ar is flowed over the substrate, and then WF and the above reducing gas are flowed over the heated substrate. Alternatively, this can be achieved by using a two or more stage CVD method in which WF and H2 are flowed, and then WF and another reducing gas are flowed.

In addition, as reducing gas, H2, SiH4, Syu2H5
゜BH3, PH3, etc. can be used alone or in combination.

In the above explanation, we have described the method of forming a W film using the most common source gas, WF, but WCQ6 and WCQ, which have low vapor pressure at room temperature, are heated and vaporized, and this is used as the source gas. It is also possible to form a W film by this method. Furthermore, MoF, ,MoCQ, ,MoC
Q5 can also be formed with a Mo film in the same manner as described above.

In addition, in CVD where one surface reaction is rate-limiting, differences in surface reaction rate occur depending on the surface condition, so by selecting the type of metal compound gas, Ti.

Al1. It goes without saying that selective film formation of Cu and the like is also possible.

In the halogen gas plasma processing apparatus used in the present invention,
High frequency (preferably 10kHz)
above) to generate plasma. However, when plasma is generated, if it sputters the walls of the processing chamber and metal contaminants adhere to the wafer, the subsequent W CV
During the treatment, W grows using this as a nucleus, which may lead to a decrease in selectivity. Therefore, the plasma processing equipment uses a so-called cathode coupling method, in which the substrate is negatively charged when high frequency waves are applied to the electrodes via a blocking capacitor, and the part close to the substrate surface that is a source of metal contamination is made of quartz. It is important to have a structure in which it is covered with a plate in order to exhibit the effects of the present invention.

[Effect]

Among the above configurations, the active layer is formed on the surface of the insulating film by comparing the chemical composition of the surface of the insulating film, which is not normally formed with metal selective CVD, with the chemical composition of the surface of the insulating film in areas where no other active layer is formed. Alternatively, it has the effect of increasing the content of metal elements to form a metal film to form wiring.

The inventors of the present application confirmed the effect of forming an active layer on the surface of the insulating film described above using the following experimental data. That is, WF and H were deposited on a Si wafer with a natural oxide film on the surface.
Approximately 200 W by CVD selection of W using 2 as raw material.
A sample was prepared with a film formed on it, and the interface of this sample was subjected to Auger electron spectroscopy
Depth direction analysis was performed using a spectroscopy (hereinafter referred to as AES) device. Figure 11(a) shows 3
This figure shows the AES depth profile of the above sample analyzed using an excitation electron beam of kV and 1.2 μA, where the horizontal axis shows the sputtering time and the vertical axis shows the Auger electron intensity of each element. This figure shows that F and O exist as residual impurities at the interface between Si and W. Furthermore, an identical sample (diameter 1
The irradiation area was varied using the same voltage and current as above (i.e., three samples of approximately 7 mm square size were sampled from the center of a 25 mm wafer, and the analysis position was within la1). FIGS. 11(b) and 11(c) show the results of AES depth direction analysis performed in the same manner as above using an electron beam (with varying irradiation current density). From these figures, by increasing the irradiation current density, F
It can be seen that the detection sensitivity of and ◯, especially the detection sensitivity of F, is significantly lower than that of W and Si.

In addition, in the above experiment, the measurement order of these elements was changed to F→0−'
p C-+ Si -+ W, but 1 For example, W → Si -+ (:, -+ Q 4 F
If the measurement order of the elements is reversed as shown in Figure 11(a)
Even with the irradiation current density in the case of , F was not detected at all as shown in FIG.

The above phenomenon is considered to be because F and O were desorbed from the surface during irradiation with the electron beam used for measurement.

In such an example, it is also known that when the surface of CaF, which is an insulator, is irradiated with an electron beam, approximately one F atom is desorbed for each irradiated electron. In other words, it is shown that electron irradiation has the effect of increasing the content of Si or metal elements on the surface of that part compared to other parts of the surface that are not irradiated with electrons.

Furthermore, even if the surface is an oxide, an active layer is formed by the desorption of ○ by electron beam irradiation as described above, but if the surface is treated with a gas plasma containing F, F By terminating this, it becomes possible to form an active layer on the surface more efficiently for the reasons mentioned above.

Moreover, although F is shown here as the gas of the gas plasma, other halogen gases (for example, CQ-based gases) exhibit similar effects. That is, performing surface treatment of the insulating film with halogen gas plasma before irradiating the electron beam is effective in forming the active layer on the above-mentioned insulating film surface.
It has the effect of further increasing sensitivity to electron beam irradiation.

Further, in the example described above, energy called electron irradiation was irradiated onto the surface of the insulating film, but even if the energy is irradiated with ultraviolet rays, the same effect can be obtained. However, for example, if the insulating film is 5 in2, its absorption wavelength will be short-wavelength ultraviolet light of 200 nm or less, and the surface will not be absorbed by the ultraviolet light conventionally used for sensitizing resists, so surface treatment with halogen gas plasma is necessary. It is necessary to form a halogen element adsorption layer on the surface of the insulating film to absorb ultraviolet light.

In general, when atoms or molecules are adsorbed on a solid surface, especially in the case of chemisorption, which has strong interactions, a new energy level is created between the surface and the adsorbed species, which affects the valence band of the substrate. Adsorbed species that interact with the substrate naturally affect the electronic structure of the mortar. for example,
Comparing the absorption spectrum of an isolated molecule (gas state) of dimethylcadmium (CH,)2Cd and after adsorption, the absorption spectrum of the molecule itself shows a peak at about 215 nm, and almost no light absorption is observed at long wavelengths of 300 nm or more. I can't. On the other hand, the adsorbed species absorbs light even at 600 nm. Thus, when a molecule is adsorbed, its absorption generally shifts to longer wavelengths. Therefore, in the above case, by irradiating the surface of the substrate with an argon ion laser (514, 5 nm) that does not cause absorption in the gas phase, only the adsorbed species can be selectively reacted. Note that when a surface adsorbed species is irradiated with light, the excitation process may be electronic excitation and vibrational excitation, and the reaction may be desorption or decomposition of the adsorbed species.

As described above, the surface treatment using halogen gas plasma on the insulating film in the present invention has the effect of making it possible to absorb light even in the wavelength range that the insulating film does not originally absorb, and then irradiation with ultraviolet light. By doing so, it has the effect of exciting the adsorption layer of the halogen element and causing it to be desorbed. Then, on the insulating film after the halogen element has been desorbed, the Si or metal element that was bonded before desorption remains in a free state, and this is the growth nucleus when performing the later selective CVD of the metal. becomes.

Literature regarding the general phenomena caused by light irradiation of the above-mentioned adsorbed species includes, for example, the one described in "Surface," Vol. 26, No. 11, pp. 825-836 (1988).

Next, it will be shown by the following experimental data that ion beam irradiation has the effect of forming an active layer on the surface of an insulating film in the same way as electron beam irradiation.

Two types of samples shown in Table 1 were prepared and subjected to X-ray photoelectron spectroscopy (X-ray Photoelectron 5P).
ectr.

5copy, XPS, or E1ectro
n S spectroscopy for Chemical
al Analysis, ESCA, hereinafter ESC
, A) is used to process S by Ar sputter etching.
The activation effect of i02 surface was investigated.

Umbrella processing condition details Ar sputter etch: Back pressure: 3 X 10-' To
rr.

Ar flow rate: 100sec.

p: IQmTorr.

RF power: 480W (13,56MHz).

Substrate bias knee 550V.

Etching amount: 250 people (in terms of Sin2 film) First, the content ratio of Si and O (0/Sj) on the surface was determined. The results are shown in Table 2.

Table 2 Results of elemental analysis of the surface of Si○2 film by ESCA In terms of stoichiometry, including O sorbed on the surface, perfect SiO2 has a ○/Sj ratio of 2.
However, all the values in Table 2 are 2.0 or more (that is, O richer than S i 02).

This is because the sample contains adsorbed 02 because it was exposed to the atmosphere before analysis. As is clear from Table 2, in Ar sputtering, the sputtering efficiency of ○ is higher than that of Si, and therefore the surface of the Ar sputter-etched sample (#2 sample) is the same as the surface of the untreated sample (#1 sample). It is Si-rich compared to the previous model.

Furthermore, in order to verify in more detail, the spectrum of the 5i2P peak when the X-ray incident angle on the 5402 surface was 30° and 90' was determined. The ESCA results of the untreated sample (#1) and the Ar sputter-etched sample (#2) are shown in FIGS. 12(a) and 12(b), respectively. Here, the horizontal axis represents binding energy, and the vertical axis represents peak intensity. The shallower the incident angle of the X-rays, the shallower the depth of the X-rays penetrating from the surface, which indicates information closer to the surface layer. Also,
- During boat fishing, the stable 5i-0 bond is broken and the unbonded Si
It is known that when a 5i-8i bond occurs, a chemical shift occurs to the lower energy side.

In FIG. 12(a), 3 on the untreated Si02 surface.
While the peaks at 0' and 90° are exactly the same,
In the surface after Ar sputter etching shown in FIG. 12(b), the peak at 30°, which is in the surface layer, shifts to the lower energy side and the line width becomes broader. Regarding the peak of 30@, which is more superficial, the above two samples (
A comparison of #1 and #2) is shown in FIG. 12(c). From this figure, in sample #2, the Si02 surface is A
It is clearly seen that stable 5i-0 bonds are broken by r-sputter etching to generate unbonded Si and 5i-3i bonds, that is, the surface is activated. This indicates that an ion beam with a high ion current density that impinges on the surface, similar to or higher than Ar sputter etching, has a sufficient activation effect on the surface of the insulating film. In the above description, Ar ions have been described, but other ions have similar effects because the sputtering efficiency against ion bombardment is greater than that of Si when the sputtering efficiency is 0. Additionally, focused ion beams (Focu
Regarding the Ga ion beam used in the sed ion beam (FIB) device, at the same time as the above-mentioned effect, Ga adheres to the irradiated area and this Ga itself becomes a growth nucleus in metal selective CVD.
A new effect is also added, and it has the effect of forming an active layer on the surface of the insulating film.

As the electron beam irradiation chamber used for the above-described process of forming an active layer on the surface of the insulating film, a commonly used EB exposure apparatus can be used. In addition, the ion beam irradiation chamber is equipped with a commonly used secondary ion analysis (S eco
ndary I on Mass Spec-tro
Scopy, SIM S) equipment, focused ion beam (FI
B) A device can be used. These are devices that process wafers in a vacuum, and can be transported relatively easily in a vacuum to perform continuous selective CVD of metals, but the ultraviolet light irradiation chamber is usually used There is a need to improve reduced projection exposure equipment so that the wafer can be placed in a vacuum. This is because once the wafer is exposed to the atmosphere, oxygen and moisture in the atmosphere are adsorbed onto the surface of the formed active layer, reducing the density of active points on the surface.

After performing the active layer formation process on the surface of the insulating film described above, W
By performing selective CVD using FG and a reducing gas such as H2 or SiH, W is not formed at all on the insulating film on which no active layer is formed, and only the surface of the active layer reacts with the underlying layer. Alternatively, W grows by reaction with reducing gas. That is, this selective CVD process has the effect of growing W only on the active layer corresponding to the wiring pattern to form the wiring.

Note that the insulating film used in the present invention is an inorganic insulating film such as a thermal oxide film, a thermal nitride film, PSG, BPSG, a plasma oxide film, a plasma nitride film, or SOG.

It refers to all insulating films used in LSIs, including organic insulating films such as PIQ.

〔Example〕

Hereinafter, embodiments of the present invention will be explained in four cases using the drawings.

Example=1 This example is an example of the wiring forming method of the present invention in which the active layer forming process on the surface of the insulating film is performed by scanning a focused electron beam. FIG. 3 shows the process flow, and FIG. 7 shows the apparatus used for forming the wiring. This embodiment will be described below with reference to FIG. 3 while referring to FIG.

After the wafer 109 is placed in the load lock chamber 101 shown in FIG. 7, the inside of the load lock chamber 101 is evacuated. After the inside is evacuated to about 10-' Torr, the wafer 109 is heated to about 200 tons by a lamp heater (not shown) in the same room, and the moisture adhering to the wafer 109 is burned out. After confirming that the pressure increase in the load lock chamber 101 due to moisture burning out from the wafer 109 has stopped during heating (after approximately 2 minutes), the heating is stopped, the gate valves 104 and 105 are opened, and the wafer 109 to the electron beam irradiation chamber 116 by a wafer transport mechanism (not shown).
Transport and install. This electron beam irradiation chamber 116 is
X-Y stage 117, electron lens 118, electron gun 11
The electron beam irradiation chamber 1 is opened by opening the gate valve 105 when the wafer 109 is carried into the electron beam irradiation chamber 116.
Although the pressure at 16 increases slightly, it recovers and returns to the original pressure at the moment the gate valve 105 is closed after the wafer 109 is placed. After confirming this, CAD (Computer A
The electron beam is scanned according to data input in advance into a computer (not shown) for IDE Design.

In this example, the test pattern is 3x3mm.
Lines and spaces of 0.5 μm and 2.5 μm (that is, 1000 rectangular lines of 0.5 μm×3vn) were drawn in the corners. Further, the electron beam was used for writing at an accelerating voltage of 20 kV and a current of about 10 nA. In this example, since only a small area of 3 x 3 mm square was drawn for testing purposes, scanning of the electron beam was completed in a few seconds.

Next, the gate valve 105 is opened, and the wafer 109 is transferred by a wafer transfer mechanism (not shown) to the film forming chamber 102, which has been previously evacuated to 10<-5 >Torr or less. After transporting and installing the wafer 109 in the film forming chamber 102,
Close the gate valve 105 and supply Ar from the gas introduction pipe 111.
Gas is introduced to the back side of the wafer 109. Film forming chamber 102
At the same time as the internal pressure starts to rise gradually, the gate valve 104 is closed and H2 gas is introduced into the film forming chamber 102. In the film forming chamber 102, the wafer 109 receives infrared rays from the 5-wafer heating halogen lamp 106 through the quartz window 114, and is heated to a predetermined temperature. The power of the wafer heating halogen lamp 106 is set between the quartz window 114 and the wafer 1.
Wafer 1
It is controlled by an infrared radiation thermometer 110 installed to measure the temperature of 09.

In addition, the inner wall of the film forming chamber 102 is cooled with water, and the temperature of the inner wall of the film forming chamber 102 excluding the surface of the wafer 109 is controlled by
The temperature is lowered to a sufficient temperature (approximately 120° C. or lower) to substantially prevent the film-forming reaction from proceeding even during heating. After the wafer 109 is heated to a predetermined temperature, WF and gases are introduced in addition to H2 gas to selectively grow W. After the film has grown to a predetermined thickness (approximately 0.5 μm in this example), the introduction of H2 gas and WFG gas is stopped, and the wafer heating halogen lamp 106 is turned off.

Evacuate. Here, the gate valve 104 is opened and the wafer 109 is transferred to the load lock chamber 101. Next, the gate valve 104 is closed, N2 is introduced and leaked,
At the same time, the wafer 109 is cooled and the load lock chamber 101
After the internal pressure reaches atmospheric pressure, the wafer 109 is taken out to the outside, and the W wiring formation process is completed.

FIG. 13 shows how the wafer surface changes as the process progresses. FIG. 13(a) shows the initial wafer surface, and the surface is an insulating film (Sin2).

FIG. 13(,b) shows how the active layer 202 is formed with 0.5 μm lines at 3 μm intervals with a 2.5 μm spacing by an electron beam. Also, the 13th
Figure (c) shows a metal arrangement made of W with a thickness of 0.5 μm using the active layer formed as described above as a core. 203 is shown. Here, W also grows in the lateral direction, increasing the wiring width, and as a result, line-and-space wiring of 1.5 μm is formed.

Next, the appearance of the wafer after forming the W wiring in this example was evaluated in terms of selectivity and film morphology.
Electrical evaluation was performed on the film specific resistance of the wiring. Selectivity was evaluated by observing in the dark field with an optical microscope at 2000x magnification to see how many W particles exist per unit area in the space where Sun is exposed between the W wiring after the W wiring is formed. did. For membrane morphology, W
After the wiring film was formed, the film surface was examined using a scanning electron microscope (Scan).
ningElectron Microscopy,
The samples were observed and evaluated using a SEM (hereinafter referred to as SEM) at a magnification of about 10,000 to 20,000 times. As a result, for selectivity.

No W particles were found within a 3 x 3 mm square area, confirming that the selectivity was extremely good. Regarding the film morphology, since H2 was used as the reducing gas in this example, the film thickness was 0.
Although the film had a surface roughness of about 0.1 μm compared to 5 μm, which is typical of an H2-reduced film, it is considered that this level of surface roughness is sufficient for use as wiring. Next, pads were provided at both ends of the W wiring, and the resistance between the pads was measured using a prober, and the specific resistance of the film was calculated from the wiring cross-sectional area and wiring length observed and measured using the SEM described above. There are 75 sets of patterns on one wafer,
Furthermore, since there are 10 parts in one pattern where wiring between pads can be measured, a total of 750 parts can be measured, but this time, measurements were arbitrarily performed at 50 parts.

The resulting film specific resistance was 8 to 12 μΩ, which was approximately the same level as the film specific resistance obtained by ordinary H2-reduced W CVD. Note that in this example, the W wiring was formed by H2 reduction CVD, which is generally known to have a low film specific resistance, with emphasis on keeping the wiring resistance low, but if a slight increase in resistance is allowed. For example, by forming W wiring using S i H or reduction CVD, it is possible to obtain a W film with a smooth film surface and excellent film morphology.

Comparative example: In order to compare the case where the irradiated electron current is lowered in forming an active layer on the surface of an insulating film by an electron beam, the current of the electron beam when scanning the electron beam in Example 1 was lowered from 10 nA to 1 nA. Wiring was formed using the same equipment and under the same conditions as in Example 1, except for the following.

Although the selectivity was very good and was on the same level as in Example 1, the film morphology was extremely rough, resulting in a W film that could be more appropriately called a structure in which W grains were arranged in a straight line rather than a wiring. Ta. This is considered to be because the density of active points on the active layer was low due to the low irradiated electron current during formation of the active layer using an electron beam, and crystal growth occurred while the density of W formation nuclei was low at the initial stage of W film formation.

Example 2: In this example, in the wiring forming method of the present invention, halogen gas plasma treatment is performed on the surface of the insulating film before the active layer forming process, so that the active layer forming process on the insulating film surface can be performed with high sensitivity. This is an example in which it is possible to do so. FIG. 4 shows the process flow, and FIG. 8 shows the apparatus used for forming the wiring.

The difference between this embodiment and the first embodiment is that, as can be seen by comparing FIGS. 7 and 8, a plasma processing chamber 103 is provided between the film forming chamber 102 and the electron beam irradiation chamber 116. Therefore, before the wafer 109 is transferred from the load lock chamber 101 to the electron beam irradiation chamber 116, the wafer 109 is first transferred to the plasma processing chamber 103, and after plasma gas treatment is performed, the wafer 109 is transferred to the electron beam irradiation chamber 116. This is what we are doing. Therefore, in the description of this embodiment, the wafer 10
9 is installed in the plasma processing chamber 103 to the stage where it is transported to the electron beam irradiation chamber 116 after plasma processing.The rest is completely the same except for particular differences, so the explanation will be omitted here. .

The plasma processing chamber 103 is preheated to 1O-7T or
It is evacuated to about r using a cryopump (not shown). In addition, this plasma processing chamber 103 performs only surface treatment of the wafer 109, and the wafer-side electrode is provided with a cathode coupling to prevent metal contaminants from adhering to the wafer 109 from the inner walls and electrodes of the plasma processing chamber 103. During the discharge, a negative potential bias is applied to the wafer side to suppress sputtering of the inner wall of the plasma processing chamber 103 by the ions being discharged as much as possible, so that only the wafer 109 on the cathode electrode 108 side is surface-treated. It is configured. Further, this cathode electrode 108 is provided with a quartz cover (not shown) in order to suppress metal contamination from the electrode exposed portion on the outer periphery of the wafer 109 as much as possible. When the gate valve 105 is opened when the wafer 109 is transferred from the load lock chamber 101 to the plasma processing chamber 103, the plasma processing chamber 1
The pressure inside 03 increases slightly, but when the gate valve 105 is closed after the wafer 109 is placed, the pressure instantly returns to the original pressure. After confirming this, Ar gas, NF, and gas are introduced into the plasma processing chamber 103 from the gas introduction port 112.

Next, the plasma processing chamber 103 is turned on by the high frequency power supply 113.
High frequency power is applied to the cathode electrode 108 in the NF3.
Generate plasma. After discharging for a predetermined time, A
The introduction of r gas, NF, and gas and the application of high frequency power are stopped, and the discharge is stopped. After confirming that the pressure inside the plasma processing chamber 103 has recovered to about 10-' Torr, the gate valve 120 is opened and the wafer 109 is evacuated to below 10-' Torr in advance in the electron beam irradiation chamber 116. The wafer is transported and installed by a wafer transport mechanism (not shown).

From now on, the irradiation electron current in electron beam irradiation will be set to 1.
Everything was the same as in Example 1 except that the irradiation was performed at nA (
In other words, the same treatment as in the comparative example was performed.

The final wafer after W wiring was formed was evaluated for 1 selectivity, film morphology, and film resistivity of the wiring in the same manner as described in Example 1. The results were obtained. What should be noted here is that in forming the active layer on the surface of the insulating film, even though irradiation was performed with the current of the irradiated electron beam reduced to 1710 as in Example 1, the The surface morphology was not rough and was equivalent to Example 1.

This is 5# as mentioned before! It is thought that the sensitivity to electron irradiation was improved because the surface of the membrane was fluorinated by NF and plasma treatment in advance. Furthermore, this result shows that when irradiation is performed with the irradiation electron current 10 times higher, 10 nA, the scanning speed can be increased 10 times, and therefore, an improvement in throughput can be expected.

Embodiment 3: This embodiment is an example of the wiring forming method of the present invention in which active layer formation on the surface of an insulating film is performed by scanning a focused ion beam. FIG. 5 shows the process flow, and FIG. 9 shows the apparatus used for forming the wiring.

In this example, the process was the same as in the example 1 above, except that the activation treatment of the insulating film surface was changed from an electron beam to an ion beam.
is exactly the same. In FIG. 9, 121 is an ion beam irradiation chamber, an ion lens 122, a differential evacuation chamber 1
23, and an ion generation chamber 124.

The ion beam used in this example is a Ga ion beam that is generally used in focused ion beams (FIB), with an ion current of 10 nA and an acceleration voltage of 3 to 10 kV.
Irradiation was performed with Although the minimum focused beam diameter was set at 0.5 μm, it was difficult to reduce the beam diameter any further because the accelerating voltage was low as described below. In other words, in general, it is necessary to increase the acceleration voltage to reduce the focused diameter of the ion beam, but if it is increased to about 20 kV or more, sputtering phenomenon on the surface of the insulating film will occur rather than Ga depositing on the insulating film. become.

It has already been mentioned that sputtering activates the insulating film surface, but preliminary experiments conducted by varying the accelerating voltage revealed that G rather than the Si-rich surface generated by sputtering
It was already known that if metal a was attached, the nucleation density of the W wiring would be higher and the film morphology would be better even at the same ion current, so in this example, Ga
The irradiation was carried out in the accelerating voltage range that resulted in adhesion. However, when a finer wiring width is required, by increasing the accelerating voltage and lowering the scanning speed, the surface of the insulating film can be sputter-etched, making it possible to form an active layer with a finer pattern.

In this example, the selectivity, film morphology, and film specific resistance of the wiring were evaluated in the same manner as described in Example 1 for the wafer obtained by forming W wiring by W selective CVD. The same good results as in Example 1 were obtained.

Example 4: In this example, in the wiring forming method of the present invention, as a treatment for forming an active layer on the surface of an insulating film, halogen gas plasma treatment is first performed, and an active layer on the surface of the insulating film is formed by irradiation with ultraviolet rays. This is an example in which an active layer was formed on the surface of the insulating film by irradiating ultraviolet rays with a line-and-space test pattern similar to that in Example 1 using a projection reduction exposure device after processing to make it possible. . FIG. 6 shows the process flow, and FIG. 10 shows the apparatus used for forming the wiring.

The difference between this embodiment and the above-mentioned embodiment 2 is that FIGS.
As can be seen by comparing with the figure, the electron beam irradiation chamber 11
6 is replaced by an ultraviolet irradiation chamber 125. This ultraviolet irradiation chamber 125 includes a quartz window 126, an optical lens 1
27, a reticle 128, and an ultraviolet lamp 129. The difference between the process flows of FIG. 4 and FIG. 6 is that in this example, the halogen gas in the halogen gas plasma treatment was changed from NF3 gas to CQ2 gas.
The two points are that gas was used instead, and that the activation treatment of the insulating film surface was changed from electron beam irradiation to ultraviolet irradiation. Other than that, the wiring formation process was carried out in the same manner as in Example 2.

For the ultraviolet irradiation chamber 125, a G-line (436 nm) aligner, which is generally commercially available as a reduction projection fog light device, was modified so that the wafer 109 could be transported in a vacuum and the wafer 109 could be irradiated with ultraviolet rays in a vacuum. Ultraviolet irradiation is approximately 300mW/
am2 intensity for approximately 3 seconds (i.e. 900 m W/
an2) Exposure was performed.

In this example, exposure was performed with ultraviolet light at a wavelength of 436 nm as described above, but since similar effects can be expected with shorter wavelengths, the i-line (365 nm), which is recently commercially available,
It is also possible to use an aligner or a KrF excimer (248 nm) aligner.

In this embodiment, as in the first embodiment, the selection CV of W
The wafers obtained by forming W wiring in accordance with D were evaluated in terms of selectivity, film morphology, and film specific resistance of the wiring in the same manner as described in Example 1. The results were obtained.

Although several aspects of the present invention have been described in detail above, the present invention is not limited only to the conditions of the device 1 shown in the above embodiment, and the electron beam or ion beam irradiation device may also be an electric field type lens, a magnetic field type It may use any lens,
Further, the ultraviolet irradiation device may be not only a reduction projection type but also a conventionally used ultraviolet exposure device such as a one-to-one projection type. However, if the wafer is placed in a vacuum and continuous processing is performed, the mask-contact type, which involves the movement of the mask, requires technical innovation in the transport system.

In addition, in the plasma processing of the present invention, there is no metal contamination on the wafer, and an etching chamber is used that can introduce halogen gases such as NF, CO2, and BCl23, and can apply high frequencies. By using a cold wall type CVD film forming chamber capable of forming a film and using an apparatus having a transfer mechanism capable of vacuum transfer of a wafer between these processing chambers, the same effects as in the embodiments of the present invention can be obtained. be able to.

In the above example, the surface treatment of the insulating film using halogen-based gas plasma was performed in an Ar sputter etching chamber, but since the surface treatment described above is mainly based on chemical etching, other methods without metal contamination, such as E
A method that has been applied or is being considered for application to a semiconductor process, such as a CR microwave plasma method, can be used. Furthermore, regarding the target selected CVD system and metal, the WF, -82 system or W
The system is not limited to selective CVD of W using the F, -5iH, system, but also a system that enables selective CVD, such as MoF.
, -H2 system, MoF, -5iH, selection of Mo by system C
It goes without saying that the present invention can also be applied to AΩ selective CVD and Cu selective CVD using VD, alkyl AQ, and other organometallic compounds as raw materials.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to use a resist like in the past when forming wiring, and a significant step reduction in the wiring forming process is realized.
This can greatly contribute to shortening the time from user ordering to product supply. In addition, it has the effect of making it possible to significantly reduce costs, especially in the semiconductor production sector where high-mix, low-volume production is performed.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the wiring forming process of the wiring forming method according to the present invention, FIG. 2 is an explanatory diagram showing the wiring forming process of the conventional method, and FIGS. 3 to 6 are wiring diagrams of the embodiment of the present invention. 7 to 10 are block diagrams of the wiring forming apparatus used in the above examples, and FIG. 11 shows an experiment to demonstrate the formation of an active layer on the surface of an insulating film by an electron beam. A with varying irradiation current density was used.
The depth direction profile obtained by ES, FIG. 12 shows the spectrum of the 5i2p peak obtained by ESCA, which was used in an experiment to demonstrate the effect of an ion beam on the formation of an active layer on the surface of an insulating film, and FIG. 13 shows an example of the present invention. FIG. 3 is an explanatory diagram showing details of the wiring formation process. Explanation of symbols 101... Load lock chamber 102... Film forming chamber 103... Plasma processing chamber 104, 105, 120... Gate valve 106...
・Halogen lamp 107 for wafer heating...Thermocouple
108...Cathode electrode 109...Wafer 110...Infrared radiation thermometer 111.112...Gas inlet 113...High frequency power supply 114...Quartz window 115
...Calcium fluoride window 116...Electron beam irradiation chamber 117...X-Y stage 18...Electron lens 119...Electron gun 21...
・Ion beam irradiation room

Claims (1)

[Scope of Claims] 1. A method of forming a wiring pattern directly on an insulating film on a substrate by selective CVD of metal without providing steps of coating, exposing, and developing an organic photosensitive material, the method comprising: A wiring forming method characterized by sequentially performing two processes: formation of an active layer corresponding to a desired wiring pattern on the surface of the upper insulating film and selective CVD of metal. 2. In the wiring forming method according to claim 1, the formation of the active layer on the surface of the insulating film has a chemical composition that contains less Si or metal elements than the chemical composition of the surface of the insulating film in other areas where there is no active layer. A wiring forming method characterized by increasing the wiring rate. 3. The wiring forming method according to claim 2, wherein the active layer is formed on the surface of the insulating film by scanning the surface of the insulating film with a focused electron beam. 4. In the wiring forming method according to claim 2, the active layer is formed on the surface of the insulating film by treating the surface of the insulating film with halogen gas plasma and then scanning the surface of the insulating film with a focused electron beam. A wiring forming method characterized by: 5. The wiring forming method according to claim 2, wherein the active layer is formed on the surface of the insulating film by scanning an ion beam focused on the surface of the insulating film. 6. In the wiring forming method according to claim 2, the active layer is formed on the surface of the insulating film by subjecting the surface of the insulating film to surface treatment with halogen gas plasma, and then photochemically reacting only the portion irradiated with light in an exposure device. 1. A wiring formation method characterized in that the wiring formation method is performed by activating the wiring. 7. In the wiring forming method according to any one of claims 1 to 6, forming the active layer on the surface of the insulating film and selective CVD of the metal are performed continuously without exposing the substrate to the atmosphere. A wiring forming method characterized by: 8. A scanning electron beam irradiation chamber, a metal selection CVD chamber disposed near the scanning electron beam irradiation chamber, and a method for connecting the scanning electron beam irradiation chamber and the metal selection CVD chamber without exposing the substrate to the atmosphere. A wiring forming apparatus comprising: a conveying mechanism. 9. A plasma processing chamber, a means for introducing a gas containing at least a halogen gas or a halogen compound gas into the plasma processing chamber, a scanning electron beam irradiation chamber, and a metal selection CVD disposed near the scanning electron beam irradiation chamber. room and
A wiring forming apparatus comprising a mechanism for transporting a substrate between the plasma processing chamber, the scanning electron beam irradiation chamber, and the metal selective CVD chamber without exposing the substrate to the atmosphere. 10. A scanning ion beam irradiation chamber, a metal selection CVD chamber located near the scanning ion beam irradiation chamber, and a method for creating a connection between the scanning ion beam irradiation chamber and the metal selection CVD chamber without exposing the substrate to the atmosphere. A wiring forming apparatus comprising: a conveying mechanism. 11. A plasma processing chamber, a means for introducing a gas containing at least a halogen gas or a halogen compound gas into the plasma processing chamber, an ultraviolet exposure chamber, a metal selective CVD chamber disposed near the ultraviolet exposure chamber, and a substrate. A wiring forming apparatus comprising: a mechanism for transporting between the plasma processing chamber, the ultraviolet exposure chamber, and the metal selective CVD chamber without exposing the metal to the atmosphere.