JPH03235657A - Dc-dc converter - Google Patents

Abstract

PURPOSE:To avoid the degradation of an efficiency even if an input voltage is elevated by a method wherein an inductor is provided between a plurality of capacitors and an output capacitors. CONSTITUTION:An output capacitor C3 is connected in parallel with a plurality of capacitors C1 and C2 and an inductor L is provided between the capacitors C1 and C2 and the output capacitors C3. A plurality of the capacitors C1 and C2 are successively charged by a DC power supply E and the output capacitor C3 is charged by the charged capacitors C1 and C2. An energy is stored in the inductor L while the capacitor C3 is charged. While the output capacitors C3 is not charged by the capacitors C1 and C2, the energy stored in the inductor L is supplied to the output capacitors C3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a switched circuit that charges a plurality of capacitors connected in series with a DC power supply and obtains a DC output voltage from the voltage divided by the capacitors. Cavacitor type D
This relates to a C-DC converter.

[Conventional technology]

For example, in Japanese Patent Application Laid-open No. 58-58863, there is a DC-DC
A switched capacitor transformer is proposed as a converter.

In addition, Honjojin has filed a patent application for this type of twisted capacitor type DC-DC converter in Japanese Patent Application No. 63-231223. Figure 5 is a circuit diagram of the main part of the DC-DC converter, and Figures 6 and 7 are 1) C-D
FIG. 2 is a circuit diagram of an equivalent circuit of a C converter.

In FIG. 5, a DC power source 10 consisting of a battery is connected between voltage input terminals t, +, and tz.

- the surveying pressure input terminal tl is also an example voltage output terminal via a series circuit of switch 1.2; is connected to.

Further, the other side voltage input terminal t2 is connected to the other side voltage output terminal t2°. A series circuit of a capacitor C7 and a switch 4 is connected in parallel to the switch 2, and a connection intermediate point between the capacitor C5 and the switch 4 is connected to the other side voltage input terminal t2 via the switch 3. The other side voltage input terminal L2 is connected to the above-mentioned voltage output terminal t1° via a series circuit of switches 7 and 8, and a series circuit of a capacitor Ct and a sui nochi 6 is connected in parallel to switch 8. has been done. and switch 6 and capacitor C2
The intermediate point of the connection is connected to the negative side pressure input terminals t and l via the switch 5. In addition, the voltage control output terminal t1° is connected to the other side voltage output terminals t and 2° via a smoothing capacitor C3, and both voltage output terminals t
A load 11 is interposed between 1°+j20. The switches 1, 2, 3, .

Next, the operation of this DC-DC converter is shown in Figures 6 and 7.
This will be explained with figures.

The switches 1, 2, . . . , 8 of this DC-DC converter are controlled to be turned on or off by applying a clock signal for on/off control thereto. Also, switches 1.4, 6.7 and switches 2, 3,
5.8 are designed to alternately swing. When a DC voltage of lO■ is applied between the voltage input terminals tI+t2, the voltage is divided by the capacitors CI and C2, and a DC voltage of 5V is output between the voltage output terminals t1°+j2°.

Now, capacitor C2 is already connected to input terminal Vi and output voltage V
, and assuming that capacitor C9 has completed discharging, switches 1.4 and 6.7 are on and switches 2 and 3.58 are off, as shown in Figure 6. The equivalent circuit shown is shown below. Thereby, capacitor C
I is charged with a potential difference V, V, (=10-5 = 5 V). On the other hand, capacitor C that has been fully charged
2 supplies energy to the load 11 by its discharge. When the switches 1, 4, 6, and 7 are in the OFF state and the switches 2, 3, and 5.8 are in the ON state, as shown in FIG. This becomes an equivalent circuit. Then, the previously discharged capacitor C2 has a potential difference of V and -V as before.

Conversely, the capacitor C1, which has completed charging first, supplies energy to the load 11 by discharging the capacitor C1. By repeating such switching operations at the frequency of the clock signal, energy is continuously supplied to the load 11.

At 22, the smoothing capacitor C3 uses the energy supplied from the capacitor C1C2 to smooth voltage fluctuations that occur at high frequencies due to the frequency of the clock signal or the on/off operation of a switch. Note that, in order to stabilize the output voltage V0 against fluctuations in the input voltage (2), the pulse width of the clock signal is subjected to PWM control in relation to the input terminal (V). In this way, this DC-DC converter has input terminal ■1
is divided by capacitors C1 and Cz to output voltage ■. By obtaining this, the input/output voltage ratio is 2:1.

(Problem to be Solved by the Invention) Here, the input voltage V is 12V, and the output voltage V0 is 5V.
When manufacturing a c-oc converter, set the metamorphic ratio to 2=
It is appropriate to select 1. In that case, ■.

-V when stabilizing the output voltage v0 to 5V. , that is, an excess voltage of 6-5=IV is generated.

Conventionally, this surplus voltage is reduced by the internal impedance of the DC-DC converter, such as the on-resistance of a switch. Therefore, the conventional DC-DC with a metamorphic ratio of 2=1
The converter is operated by a person as shown in Figure 4.

The output voltage is , and its internal impedance is equivalent to a circuit.

For this reason, this type of DC-DCC comparator.

There is a problem in that when , the power consumption due to the internal impedances r, .

In view of such problems, the present invention provides a switched capacitor type DC whose efficiency does not decrease even when the input voltage increases.
- The purpose is to provide a DC converter.

[Means for Solving the Problems] The OC-OC converter according to the present invention includes a plurality of series-connected capacitors connected to a DC power supply, an output capacitor connected in parallel to the capacitors, and an output capacitor connected in parallel to the capacitors. A switched capacitor type DC-DC converter comprising a plurality of switches that perform switching operations to connect to the capacitor, characterized in that an inductor is interposed between the capacitor and the output capacitor. shall be.

(Function) Multiple capacitors are sequentially charged by a DC power supply. The charged capacitor charges the output capacitor.

Energy is stored in the inductor during that charging period. During the period when the output capacitor is not being charged by the capacitor, the energy accumulated in the inductor is released to the output capacitor.

As a result, the surplus voltage generated when the output voltage is reduced to % or less of the input voltage is accumulated in the inductor, and there is no power consumption and efficiency does not decrease.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a circuit diagram of a main part of a DC-DC converter according to the present invention. Voltage input terminal 1. ．． A DC power supply E, which is a battery, for example, is connected between the terminals 12 and 12 with its positive electrode + serving as the voltage input terminal 1, and the voltage input terminal t2 is grounded.

Voltage input terminal 1+ is connected to voltage output terminal t3 via a series circuit of switches S, , S, and inductor L. Switch S2 has capacitor CI and switch S,
A series circuit is connected in parallel with the capacitor C1 and the switch S3, and the connection portion between the capacitor C1 and the switch S3 is grounded via the switch S4. Further, the voltage input terminals t, I are connected to the connection portion between the switches S2 and 33 via a series circuit with the switches S and 36. A series circuit of a capacitor C2 and a switch S is connected in parallel to the switch S6, and a connection portion between the capacitor C2 and the switch S7 is grounded via a switch Sl. The voltage output terminal L3 is connected to the voltage output terminal t4 via a load RL,
Voltage output terminal t4 is grounded. Voltage output terminal t3
．． An output capacitor C1 is connected between tn and tn.

A diode D having an anode on the output capacitor C3 side is connected in parallel to the series circuit of the inductor L and the output capacitor C1. The output voltage of the voltage output terminal t3 is provided to the adder 10, and the adder 10 is provided with the target output voltage (2). The output of the adder 10 is input to the amplifier 11, and the output is input to the pulse width converter 12.
has been input to. The pulse width converter 12 converts the clock pulse φ shown in FIG. , positive. ,φ.

To outputs a clock pulse φ.

The clock pulse 7° is applied to the switches S*, Sb, and Ss. The clock pulse φ is applied to the switch S.

The clock pulse T is applied to the switches S2, S4, and S7.
0 is applied to switch S.

Said switch S7. Ss is a Pchaflu 05FET, and switches S2, 33. N-channel MO3FETs are used for Ss, Sb, Sw, and Sa.

Further, the inductance of the inductor L is, for example, about 5 μH, and the capacitors CI, C2, and output capacitor C3 are multilayer ceramic capacitors with a capacitance of, for example, 22 μF.

Next, the operation of the DC-DC converter configured as described above will be explained with reference to FIG. 2 showing clock pulses and FIG. 3 showing an equivalent circuit of the DC-DC converter. This DC
-The switches St, S2...S of the DC converter are
Clock pulse φa + for on/off control, respectively
n@+φ. , 7°, the switches St, 53S6 . SR and switch S2.34. Ss and St perform switching operations alternately.

Here, the on-resistance of switches S+, Sz...S8 is O,
Let the off resistance be ■.

Now the clock pulse is positive. ,φ. switch S+
, S3, S6, Ss are turned on, clock pulse 7°, φ. Therefore, during the period T in which the switches S2, 34°3s, and S7 are in the off state, the equivalent circuit becomes as shown in FIG. 3(a). As a result, the capacitors C+ and Cz are charged by the input terminal ■1, and the respective terminal voltages Xl and Xz become .The output capacitor C3 is charged by the voltage of the capacitor C2, and its terminal voltage becomes X. Also, energy is supplied to the load R via the inductor L, and the output voltage is
. (=X,). As a result, the terminal voltage Xz of the capacitor C2 decreases, and the terminal voltage X1 of the capacitor C1 increases. Next, clock pulses T,,φ. Switches S+, Ss, S6, and Ss are turned off by clock pulses 7° and φ. Switch Sz
, 54Ss, and Sy are in the on state during period T3, the equivalent circuit becomes as shown in FIG. 3(b). As a result, the output capacitor C3 is charged by the voltage of the capacitor C1 whose terminal voltage x1 has increased, and its terminal voltage becomes X3. Energy is also supplied to the load RL via the inductor L, and the output voltage becomes .

(= X 3). Also clock pulse 78. φ.

7°, φ. In the period Tz and T when neither exists, the equivalent circuit becomes as shown in FIG. 3(C). As a result, both the capacitors C1 and CZ are no longer charged by the input terminal (2), while the output capacitor C3 becomes an inductor and is discharged through the load RL.

In this way, energy is supplied from the capacitors CI and C2 to the load R+, resulting in an output voltage ■. This means that the decrease in Then, such switching operation is repeated at the frequency of the clock pulse, and energy is continuously supplied to the load R4. And the output voltage■.

and the target output voltage (3) of the output voltage are compared by the adder lO, and the pulse width converter 12 is
is the clock pulse 7,,φ that it outputs. The so-called PWM changes the duty ratio T, /Ts of the clock pulse 7°, the duty ratio T3/Ts of φ0.
The output voltage ■ is equal to the target output voltage ■3 by controlling and changing the charging time of capacitors CI and CZ. is obtained.

Next, the principle of the present invention will be explained with reference to FIGS. 2 and 3.

Capacitors C, , C2 repeat the operation of switching between their series state and the parallel state with respect to output capacitor C3 at high speed. Vo
) and period T.

The energy flowing into the inductor at is U.

Then, Ul = (Xz Xl)IL -T+ ・
...(1).

Also, in period T2, if the energy flowing out from the inductor L is C2, then C2=X3 ・I , ・Tz ”
・(2) Further, in period T, if the energy flowing into the inductor is U, then ut = (x, -L)IL ・T3 ... (3
).

Furthermore, in period T4, if the energy flowing out from inductor L is C4, then tJ= "X3 ' TL ・T4
”'(4).

Here, in a steady state, the energy flowing into the inductor and the energy flowing out are equal, so U + + U
*=Uz+Ua...(5)
becomes. Here, T = T3. 8 and T2=T
, T. Define as FF. And X in equations (1) and (3).

If we rearrange the formula, Vi −TON=2 (TOFF +T(IN)
・X3...(6). Furthermore, the switching period,
That is, the clock pulse period T is (TOFF + TON)
and the duty d of the clock pulse is T. ,
/'r, then equation (6) becomes Vi 2 (TON+TOFF) T
It becomes S.

However, here there is a restriction of d%. This is because when d≧Raku, none of the equivalent circuits shown in FIGS. 3(a), (b), and (c) can be obtained. In this way, even if the input voltage ■ changes, by changing the duty d, the terminal voltage of the output capacitor C3 x 3, that is, the output voltage ■. can be kept constant. And duty d is %
In the following case, the energy stored in the inductor is released to the output capacitor C3, and there is no power consumption in the inductor, resulting in an output voltage of less than A at the input terminal.

This will prevent a decrease in efficiency when stabilizing the temperature.

The DC-DC converter of the present invention has a maximum output of 10 W and an input voltage of 70% or more over IIV to 16 V when capacitors C+, Cz, and C1l are of 22 μF and a 5 μH choke coil is used as the inductor L. High efficiency was obtained.

[Effects of the Invention] As detailed above, according to the present invention, energy is accumulated in the inductor in the charging circuit during the period when the output capacitor is charged by the capacitor, and energy is accumulated in the inductor in the charging circuit during the period when the output capacitor is not charged by the capacitor. Since the energy stored in the inductor is released to the output capacitor, the inductor absorbs the excess voltage when obtaining an output voltage that is less than % of the input voltage, and no unnecessary power consumption occurs. Therefore, an output voltage of 2 or less at the input terminal can be stably obtained, and there is an excellent effect of providing a highly efficient and economical C-DC converter.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the main parts of the DC-DC converter according to the present invention, Fig. 2 is a waveform diagram of clock pulses for performing a switching operation, Fig. 3 is an equivalent circuit diagram of the DC-DC converter, and Fig. 4 is a schematic explanatory diagram of a DC-DC converter, Figure 5 is a circuit diagram of a conventional DC-DC converter, and Figure 6 is a schematic explanatory diagram of a DC-DC converter.
7 and 7 are equivalent circuit diagrams thereof. 10... Adder E... DC power supply Sl, St
...S8...Switch C,,C,...Capacitor C3...Output capacitor Shi...Inductor RL...Load D...Diode

Claims (1)

[Claims] 1. A plurality of series-connected capacitors connected to a DC power supply, an output capacitor connected in parallel to the capacitors, and a plurality of capacitors that perform a switching operation to connect the output capacitors to the capacitors. A switched capacitor type DC-DC converter comprising a switch, characterized in that an inductor is interposed between the capacitor and the output capacitor.
-DC converter.