JPH03235121A - Branch history table control system - Google Patents

Abstract

PURPOSE:To curtail the overhead in a data processor to be generated by detecting an exception event such as virtual space absence, etc. by inhibiting a fact that a branch instruction for executing a branch between different virtual spaces hits against a branch history table. CONSTITUTION:The system is constituted of a write permitting flag (WEF) 1, an instruction address register (IAR) 2, a branch destination address register (DAR) 3, a virtual space number comparing circuit (WSC) 4, an instruction address array (IAA) 5, a branch address array (DAA) 6, a branch destination information array (DIA) 7, an instruction address comparing circuit (IAC) 8, an AND circuit 10, a branch detecting flag (BHF) 11, and a predicted branch destination address register (PDAR) 12. In such a state, it is inhibited that a branch instruction for executing a branch between different virtual spaces hits against a branch history table. In such a way, the overhead of a data processor generated by detecting an exception event such as virtual space absence, etc., can be curtailed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a branch history table control method, and particularly to a branch history table control method in a data processing device that employs a virtual storage method.

[Prior Art] Branch history tables are currently used in various data processing devices, and store the address of a branch instruction (branch instruction address) and the address of the branch destination instruction related to that branch instruction (branch history table).
(The branch destination address corresponding to the branch instruction address) is stored as a pair (the branch history table is stored as a pair of
).

By the way, in a data processing device that employs a certain kind of virtual memory method, virtual addresses (VA) are used.

Virtual Address) is configured as shown in FIG. That is, the upper bit of VA contains a virtual space number (WSN, Working 5
The lower bits of VA (bits other than bits related to WSN) have a relative virtual address (EVA, Effec tive Virt
ual Address). In VAs with such configurations, the fact that the WSNs are different indicates that the virtual spaces themselves related to the VAs are different.

As described above, in the branch history table used in a data processing device that adopts the virtual storage method in which VA is configured, the previously existing virtual space disappears while a certain process is being performed by O3 (Operating System) etc. In such a case, if a branch instruction that branches between different virtual spaces hits the branch history table,
There is a possibility that an instruction in a virtual space that does not exist may be prefetched.

[Problem to be solved by the invention]

As mentioned above, in the branch history table used in a data processing device that employs a virtual memory system in which VA is configured as shown in Figure 2, a branch instruction that branches between different virtual spaces is hit. , there is a possibility that an instruction in a virtual space that does not exist may be prefetched.

In this case, an exceptional event such as the absence of a virtual space is detected, but since the branch according to the branch instruction is not actually executed, the exceptional event is ignored.

Therefore, there is a drawback in that the data processing device incurs an overhead due to the detection of the exceptional event and the ignoring of the exceptional event.

In view of the above-mentioned points, an object of the present invention is to be able to prevent a branch instruction that branches between different virtual spaces from hitting a branch history table, and to prevent a branch instruction from hitting a branch history table, which occurs due to the detection of an exceptional event such as the absence of a virtual space. An object of the present invention is to provide a branch history table control method that can reduce overhead in a data processing device.

[Means to solve the problem]

The branch history table control method of the present invention is applicable to a data processing device that employs a virtual memory method and has a branch history table that stores a branch instruction address and a branch destination address corresponding to the branch instruction address in pairs. A first register that holds an instruction fetch address when reading the table and a branch instruction address when writing the branch history table, and a branch destination address that corresponds to the branch instruction address held by the first register when writing the branch history table. a second register to be held, and a first to compare a part of the branch instruction address held by the first register and a part of the branch destination address held by the second register when writing the branch history table; a comparison means for storing the comparison result of the first comparison means corresponding to the branch history table, and a storage means for storing the comparison result of the first comparison means corresponding to the branch history table, and an instruction fetch address held by the first register when reading the branch history table and the branch history table. If the comparison result between the second comparison means for comparing the stored branch instruction address and the first comparison means stored by the storage means indicates a mismatch, the second comparison means and a first inhibiting means for inhibiting detection of a predicted branch destination address by invalidating the comparison result.

Further, the branch history table control method of the present invention provides a data processing device that employs a virtual storage method and has a branch history table that stores a branch instruction address and a branch destination address corresponding to the branch instruction address in pairs.
A third register that holds an instruction fetch address when reading the branch history table and a branch instruction address when writing the branch history table, and an instruction fetch address held by the third register when reading the branch history table and the branch history table. A third comparison means that compares a stored branch instruction address with a portion of the branch instruction address stored in the branch history table and a portion of the branch destination address corresponding to the branch instruction address. a fourth comparing means; and a second deterrent for inhibiting detection of a predicted branch destination address by invalidating the comparison result of the third comparing means when the comparison result of the fourth comparing means shows a mismatch; means.

[Effect]

In the branch history table control method of the present invention, the first register holds the instruction fetch address when reading the branch history table, holds the branch instruction address when writing the branch history table, and the second register holds the instruction fetch address when writing the branch history table. A branch target address corresponding to a branch instruction address held by a register of The storage means stores the comparison result of the first comparison means corresponding to the branch history table, and the second comparison means Compare the instruction fetch address held by the register with the branch instruction address stored in the branch history table,
The first deterrent means is stored by the storage means.
If the comparison result of the comparison means shows a discrepancy, the second
The comparison result of the comparing means is invalidated to suppress detection of the predicted branch destination address.

Further, in the branch history table control method of the present invention, the third register holds the instruction fetch address when reading the branch history table and holds the branch instruction address when writing the branch history table, and the third comparing means holds the instruction fetch address when reading the branch history table. The instruction fetch address held by the third register is compared with the branch instruction address stored in the branch history table, and the fourth comparison means compares the instruction fetch address held by the third register with the branch instruction address stored in the branch history table. The second inhibiting means compares the branch instruction address with a part of the branch destination address corresponding to the branch instruction address, and invalidates the comparison result of the third comparing means when the comparison result of the fourth comparing means indicates a mismatch. to suppress detection of the predicted branch destination address.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a block diagram showing the configuration of an embodiment of the branch history table control method of the present invention. Enable F
lag) 1 and the instruction address register (IAR, In5
traction Address Register
er)2 and branch destination address registers (DAR, Des
tinationAddress Register
) 3 and the virtual space number comparison circuit (WSCe Wor
kin gSpace number Com
Parat.

r) 4 and instruction address array (IAA, In5tr
address array) 5 and branch destination address array (DAA, De 5tina).
tion Address Array) 6, and a branch destination information array (DIA++Dest1).
Nation Information Arta
y) 'r and instruction address comparison circuit (IAC, 1nst
ruction Address Compa
rator) 8, AND circuit 10, and branch detection flag (BHFa Branch Hit Flag) 1
) and the predicted branch destination address register (PDAR*Pr
Directed Destination Add
ress Register) 12 and signal 1610
1 to 1) and 6. Here, IAA
5 and DAA6 create a branch history table (BHT
, BranchH3story Table) are configured. Also, the first register is realized by IAR2, the second register is realized by DAR3, and W
Se2 realizes a first comparing means, DrA7 realizes a storage means, lAC3 realizes a second comparing means, and the AND circuit 10 realizes a first inhibiting means. It is assumed that the branch history table control method of this embodiment is applied to a data processing apparatus that employs a virtual storage method in which a VA is configured as shown in FIG.

WEFI is an F/F (F l i p/F 1op) that is set when registering (writing) an address (branch instruction address and branch destination address) in the BHT, and controls instruction fetching via the signal line 101. Equipment (IFC
, In5truction Fetch Controller) (not shown), the IAA5. DAA6
and instructs writing to DIA7.

IAR2 is a register that receives an instruction fetch address when writing BHT and receives a branch instruction address when writing BIT.
The virtual space number (WSN) of the virtual space where the branch instruction exists is received via the signal line 105 to WSe2. (see figure),
A certain number of upper bits in the address (some bits necessary for comparison in IAC8) are sent to IAA5 and lAC3 via signal line 106, and signal line 107
via IAA5. The lower bits in the address (other than the fixed upper bits mentioned above) are transferred to DAA6 and DIA7 in RAM (Random ACCeS3 Me
mOr7a IAA5. It is sent as the address of the RAM forming each of DAA6 and DIA7.

DAR3 is a register that holds a branch destination address corresponding to the branch instruction address held in IAR2 at the time of BIT writing, receives the branch destination address from the ADC via signal m103, and sends the branch address to DAA6 via signal line 109. Sends destination address and sends W via signal &1IIO8
The WSN of the virtual space where the branch destination instruction exists (receiver is a part of the taken branch destination address) is sent to Se2.

WSe2 is a comparison circuit that compares the WSN of the virtual space where the branch instruction exists and the WSN of the virtual space where the branch destination instruction exists to detect whether they are equal. The WSN and the WSN of the virtual space where the branch destination instruction exists are received from IAR2 and DAR3 via signal lines 105 and 108, and if they are equal, the comparison result is set to "1", and if they are not equal, the comparison result is set to "1". The comparison result is “O”, and the comparison result (W
The SN comparison result) is sent to the DIA 7 via the signal line 1)0.

The IAA5 in the BHT is a table that stores the history of branch instruction addresses, and uses the lower bits of the address (branch instruction address or instruction fetch address) sent from the IAR2 via the signal line 107 as an address to connect the signal line 104. When a write is instructed (permitted) by WEFI via the IAR2 via the signal line 106 (when WEFl is sent), the upper bits of the branch instruction address sent from the IAR2 are written via the signal line 106, and when a read is instructed from the WEFI (
When WEFI is reset), the upper bits of the branch instruction address remaining as history are sent to lA via signal line 1)1.
Send to C3.

The DAA6 in the BHT is a table that stores the history of branch destination addresses in correspondence with the history of branch instruction addresses in the IAA5, and uses the lower bits of the address sent from the IAR2 via the signal line 107 as an address. line 1
When a write is instructed from WEFl via signal g104, the branch destination address sent from DAR3 is written via signal g109, and when a read is instructed from WEFI, the branch destination address remaining as a history is sent to the signal g109. line 1
)2 to the PDAR 12.

DIA7 compares the WSN in the paired branch instruction address and the WSN in the branch destination address in correspondence with TAA5 and DAA6 (corresponding to BHT and entry).
WEF is a table to be stored, and WEF is
When writing is instructed by I, the comparison result sent from WSe2 via signal line 1)0 is stored, and WEFI
When a read instruction is given, the stored comparison result is sent to the AND circuit 10 via the signal line 1)3.

lAC3 is the instruction fetch address and B
This is a comparison circuit that detects a match with the historical branch instruction address in the HT, and it compares the upper bits of the instruction fetch address sent from the IAR 2 via the signal line 106 and the signal line 1).
1 and the upper bits of the branch instruction address sent from the IAA5, and the comparison result indicates whether or not they match (indicates "l" if they are equal, and "0" if they are different). ” address match signal) on signal line 1) 4
The signal is sent to the AND circuit 10 via.

The AND circuit 10 is a gate that checks whether or not the same branch instruction address as the instruction fetch address is on the history in the BHT when BIT is successively issued.
The address match signal sent from C3 is logically ANDed with the WSN comparison result sent from DIA7 via signal line 1)3, and the result of the logical product is used to detect the predicted branch destination via signal line 1)5. Send it to BHFII as a signal.

BHFII is an F/F that indicates whether a predicted branch destination address has been detected (F/F that is set to indicate that a predicted branch destination address has been detected if the predicted branch destination detection signal is “1”) receives a predicted branch destination detection signal sent from the AND circuit 10 via the signal line 1)5, and sends a signal based on the predicted branch destination detection signal to the IFC via the signal line 1)7.

PDAR12 is a register that corresponds to BHFII and receives the predicted branch destination address, and is connected to D via signal line 1)2.
It receives the historical branch destination address in the BHT sent from the AA6, and sends the branch destination address as a predicted branch destination address to the ADC via the signal *1)6.

Next, the operation of the branch history table control system of this embodiment configured as described above will be explained.

First, the operation when BHT is continuously output will be explained.

When continuously outputting BHT, "01" is first set in WEFI, and the instruction fetch address is set in IAR2.

Based on these cents, lAC8 compares the historical branch instruction address in IAA5 and the instruction fetch address in IARZ.

If the branch instruction address on the history and the instruction fetch address match in this comparison, the output of rAc8 (address match signal on signal line 1 4) becomes "1".

At this point, if the DIA 7 shows that the WSN of the virtual space where the branch instruction exists and the WSN of the virtual space where the branch destination instruction exists are equal, the output (signal line 1) 5 of the AND circuit 10 The predicted branch destination detection signal) becomes “1” (DIA9 detects W in the virtual space where the branch instruction exists).
If it is shown that the SN and the WSN of the virtual space where the branch destination instruction exists are different, the output of the AND circuit IO is always “
0'', and even if the output of AC8 becomes "1", detection of the predicted branch destination address is inhibited).

When the output of the AND circuit 10 becomes "1", BHFil is set, and BHFII sends a signal indicating detection of a predicted branch destination address to the IFC.

At the same time, PDAR12 receives the predicted branch destination address from DAA6, and transfers the predicted branch destination address to ADC.
Next, the operation during BHT writing will be explained.

When writing BHT, 1)” is set in WEFI,
The branch instruction address is set in IAR2, and DAR34
The branch destination address corresponding to the current branch instruction address is set.

Based on these cents (based on the WSN in the sent branch instruction address and branch target address), WSe
Step 2 checks whether the virtual space where the branch instruction exists is equal to the virtual space where the branch destination instruction exists.

If the two are equal in this check, the output of WSe2 (signal & WSN comparison result on 1llO) is 1”, D
“l” is stored in IA7.

If the above check shows that they are different, "0" is stored in DIA7. By storing this "0", as described above, the detection of the predicted branch destination address when BHT continues is suppressed.

In this way, a branch instruction that branches between different virtual spaces is prevented from hitting the branch history table.

FIG. 1(b) is a block diagram showing the configuration of another embodiment of the branch history table control method of the present invention. The branch history table control method of this embodiment uses WEFI and I
AR2, DAR3, ■AA5, DAA6, lA
C3, WSe2, AND circuit 10, BHFII, PDAR 12, and signal lines 101 to 103, 109. ．．
1) 2 1) 4 to 123 (The components in FIG. 1(b) that are similar to the components in FIG. 1(a) are the same as those in FIG. 1(a). ). Here, B by IAA5 and DAA6
HT is configured. Furthermore, [AR2 realizes the third register, lAC3 realizes the third comparison means, WSe2 realizes the fourth comparison means, and A
The second suppression means is realized by the ND circuit IO.

Note that the branch history table control method of this embodiment is also similar to the branch history table control method shown in FIG. shall apply to processing equipment.

WEFI registers (writes) the address to BHT.
It receives a BHT registration signal sent from the EFC (not shown) via the signal line 101, and instructs writing to the IAA5 and DAA6 via the signal m11B.

IAR2 is a register that receives an instruction fetch address when writing a BHT, and receives a branch instruction address when writing a BIT, and receives an address sent from an ADC (not shown) via a signal line 102. A fixed number of high-order bits (some bits necessary for comparison in lAC8) in the address are sent to IAA5 and lAC3 via the signal line 120, and the lower bits in the address are sent to IAA5 and DAA6 via the signal line 120. and the address of the RAM forming each of DAA6.

DAR3 is a register that holds a branch destination address corresponding to the branch instruction address held in rAR2 at the time of BHT writing, receives the branch destination address sent from the ADC via the signal line 103, and receives the branch destination address via the signal line 109. D.A.
The branch destination address is sent to A6.

IAA5 in the BHT is a table that stores the history of branch instruction addresses, and uses the lower bits of the address sent from 1AR2 via the signal line 120 as an address.
When a write is instructed by WEFl via signal line 1) 8, the upper bits of the branch instruction address sent from IAR2 are written via signal line 1) 9, and when read is instructed from WEFI. The upper bits of the branch instruction address remaining as history are sent via signal line 1)1.
WSN (
(see FIG. 2) is sent to WSe2 via the signal line 121.

The DAA6 in the BHT is a table that stores the history of branch destination addresses corresponding to the history of branch instruction addresses in the IAA5, and uses the lower bits of the address sent from the IAR2 via the signal m120 as the address. 1
) 8, the branch destination address sent from DAR3 is written via the signal line 109, and when read is instructed from WEFI, the branch destination address remains as a history. The signal line 1
)2 to the PDAR 12, and the WSN in the branch destination address is sent to the WSe2 via the signal line 122.

lAC3 is the instruction fetch address and B
This is a comparison circuit that detects a match with the historical branch instruction address in the HT, and it compares the upper bits of the instruction fetch address sent from the IAR2 via the signal line 1)9 with the signal line 1).
1 and the upper bit of the branch instruction address sent from the IAA5, and the comparison result indicates whether or not they match (indicates "1" if they are equal, and "0" if they are different). ” address match signal) on signal line 1) 4
The signal is sent to the AND circuit 1o via the AND circuit 1o.

WSe2 is a comparison circuit that compares the WSN of the virtual space where the branch instruction exists and the WSN of the virtual space where the branch destination instruction exists to detect whether they are equal. Signal each of the WSN and the WSN of the virtual space where the branch destination instruction exists! 5121 and 122
is received from IAA5 and DAA6 via
WSN comparison result) to the AND circuit 1 via the signal line 123.
Send to 0.

The AND circuit 10 is a gate that checks whether or not the same branch instruction address as the instruction fetch address exists in the history in the BHT when the BHT is successively issued.
The address match signal sent from C3 is ANDed with the WSN comparison result sent from WSe2 via signal line 123, and the result of the AND is sent as a predictive branch destination detection signal via signal line 1)5. Send to BHFII.

BHFII and PDAR 12 have the same functions as BHFII and PDAR 12 in the embodiment shown in FIG. 1(a).

Next, the operation of the branch history table control system of this embodiment configured as described above will be explained.

First, the operation when BHT is continuously output will be explained.

At the time of successive BHT output, 0'' is first set in WEFI and the instruction fetch address is written in IAR2.

Based on these sets, 1Ac8 compares the historical branch instruction address in IAA5 and the instruction fetch address in IARZ.

In this comparison, if the branch instruction address on the history and the instruction fetch address match, the output of lAC3 (address match signal on signal line 1) becomes "1".

At this point, if WSe2 indicates that the WSN in the branch instruction address on the branch history is equal to the WSN in the branch destination address corresponding to that branch instruction address, then
The output of the AND circuit 10 (the predicted branch destination detection signal on the signal '1al15) becomes "l".

When the output of the AND circuit 10 becomes "1", BHFil is sent, and BHFll sends a signal indicating detection of the predicted branch destination address to the IFC.

At the same time, PDAR12 receives the predicted branch destination address from DAA6, and transfers the predicted branch destination address to ADC.
Send to.

WSN in branch instruction address in history by WSe2
If it is shown that the WSN in the branch destination address corresponding to the branch instruction address is different, the AND circuit 10
The output of is always "0".

When the output of the AND circuit 10 becomes "θ", BHFil is reset and detection of the predicted branch destination address is inhibited.

Next, the operation during BHT writing will be explained (this operation is similar to the operation in conventional BHT control).
.

When writing BHT, "1" is set to WEFI, the branch instruction address is set to IAR2, and DAR3 is set.
The branch destination address corresponding to the branch instruction address is then sent.

By setting WEFI to 1'', a write instruction is issued to [AA5 and DAA6], and [is set in IAR2 to the storage area in IAAS at the address indicated by the lower bit of the branch instruction address in AR2. The branch instruction address is written to DAA6 at the same address.
The branch destination address set in DAR3 is written to the storage area within.

〔Effect of the invention〕

As explained above, the present invention prevents a branch instruction that branches between different virtual spaces from hitting the branch history table, thereby eliminating the possibility of prefetching an instruction in a virtual space that does not exist. This has the effect of reducing the overhead of the data processing device caused by the detection of an exceptional event such as the absence of a virtual space.

Furthermore, in the branch history table control method of the present invention in which DIA is provided, comparison information regarding the virtual space (WSN comparison results, etc.) is stored in correspondence with the branch history table, and the comparison information is combined with other information. This has the effect of enabling more precise control over the branch history table.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing the configuration of one embodiment of the present invention, FIG. 1(b) is a block diagram showing the configuration of another embodiment of the present invention, and FIG. FIG. 4 is a diagram illustrating an example of a configuration of a virtual address (VA) in a virtual memory system adopted in a data processing system to which the branch history table control system shown in ) and (b) is applied. In the figure, 1...Write enable flag (WEF), 2...Instruction address register (IAR), 3...Branch destination address register (DAR), 4.9. Virtual space number comparison circuit (WEF).
SC), 5... Instruction address array (IAA), 6
...Branch destination address array (DAA), 7...Branch destination information array (DIA), 8...Instruction address comparison circuit (IAC), 10...AND circuit, 1)...Branch detection flag (BHF), 12...Predicted branch destination address register (PDAR), toi~123...Signal line. Figure 1 (Q)

Claims (2)

[Claims] (1) In a data processing device that employs a virtual memory method and has a branch history table that stores a branch instruction address and a branch destination address corresponding to the branch instruction address as a pair, the instruction fetch address is stored when reading the branch history table. a first register that holds a branch instruction address when writing the branch history table; and a second register that holds a branch destination address corresponding to the branch instruction address held by the first register when writing the branch history table. , a first comparing means for comparing a part of the branch instruction address held by the first register and a part of the branch destination address held by the second register when writing the branch history table; storage means for storing the comparison result of the first comparison means corresponding to the table; an instruction fetch address held by the first register when reading the branch history table; and a branch instruction address stored in the branch history table. and a second comparison means for comparing the first and second comparison means, and when the comparison result of the first comparison means stored in the storage means indicates a mismatch, invalidate the comparison result of the second comparison means and make a prediction. 1. A branch history table control method, comprising: first suppressing means for suppressing detection of a branch destination address. (2) In a data processing device that employs a virtual memory method and has a branch history table that stores a branch instruction address and a branch destination address corresponding to the branch instruction address as a pair, the instruction fetch address is stored when reading the branch history table. a third register that holds a branch instruction address when a branch history table is written; an instruction fetch address held by the third register when a branch history table is read; and a branch instruction address stored by the branch history table. Third to compare
a fourth comparison means for comparing a part of the branch instruction address stored in the branch history table with a part of the branch destination address corresponding to the branch instruction address; and this fourth comparison means. branch history table control characterized by having a second inhibiting means for inhibiting detection of a predicted branch destination address by invalidating the comparison result of the third comparing means when the comparison result of the third comparing means indicates a mismatch; method.