JPH03234050A - Surface testing method for external terminal of semiconductor package - Google Patents
Surface testing method for external terminal of semiconductor packageInfo
- Publication number
- JPH03234050A JPH03234050A JP3011690A JP3011690A JPH03234050A JP H03234050 A JPH03234050 A JP H03234050A JP 3011690 A JP3011690 A JP 3011690A JP 3011690 A JP3011690 A JP 3011690A JP H03234050 A JPH03234050 A JP H03234050A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- semiconductor package
- external terminal
- solder
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000012360 testing method Methods 0.000 title claims description 6
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 229910052797 bismuth Inorganic materials 0.000 claims description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 46
- 239000006023 eutectic alloy Substances 0.000 abstract description 8
- 238000012790 confirmation Methods 0.000 abstract description 2
- 150000001621 bismuth Chemical class 0.000 abstract 2
- 150000002471 indium Chemical class 0.000 abstract 2
- 238000007747 plating Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 208000032544 Cicatrix Diseases 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- KHZAWAWPXXNLGB-UHFFFAOYSA-N [Bi].[Pb].[Sn] Chemical compound [Bi].[Pb].[Sn] KHZAWAWPXXNLGB-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 230000037387 scars Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔概要〕
錫めっきされた外部端子に生ｆるボイスカー（錫の針状
結晶）の発生、成長を確認する半導体パッケージ外部端
子の表面試験方法に関し、短時間で錫ホイスカーの発生
、成長の確認することを目的とし、
半導体パッケージにおける錫めっきされた外部端子の一
部分に、インジウム系又はビスマス系のはんだを付着し
、該はんだが付着された外部端子を有する前記半導体パ
ッケージを、所定の環境下で所定時間放置し、該所定時
間経過後に該外部端子の表面を確認するように構成する
。[Detailed Description of the Invention] [Summary] A method for testing the surface of external terminals of semiconductor packages to confirm the generation and growth of voice cars (acicular crystals of tin) on tin-plated external terminals. For the purpose of confirming the generation and growth of , the external terminal is left for a predetermined time under a predetermined environment, and the surface of the external terminal is checked after the predetermined time has elapsed.
本発明は、錫めっきされた外部端子に生じるボイスカー
（Ｗｈｉｓｋｅｒ）の発生、成長を確認する半導体パッ
ケージ外部端子の表面試験方法に関する。The present invention relates to a method for testing the surface of external terminals of semiconductor packages for checking the generation and growth of voice kerbs (whiskers) that occur on tin-plated external terminals.
近年、半導体用パッケージの外部端子に生じる錫ボイス
カーにより電子、電気回路が短絡する危険性があること
から、錫ボイスカーの発生を防止することが要求されて
いる。そのため、パッケージ等に影響を与えないで錫ホ
イスカーの発生を防止する必要があると共に、錫ホイス
カーの発生しない半導体パッケージを選択する必要があ
る。In recent years, since there is a risk that electronic and electrical circuits may be short-circuited due to tin voice ker generated at external terminals of semiconductor packages, it is required to prevent the generation of tin voice ker. Therefore, it is necessary to prevent the generation of tin whiskers without affecting the package, etc., and it is also necessary to select a semiconductor package in which tin whiskers do not occur.
一般に、半導体用パッケージの錫めっきされた外部端子
に生じる錫ホイスカーは、早いものでは数日、遅いもの
では数年後より錫めっき面から錫が針状結晶として成長
し、長いものでは数帆にも成長する。この錫ボイスカー
が発生すると電ｆ、電気回路の短絡する場合があり、高
信頼性を要するコンピュータ、通信機器ではその対策が
不可欠な条件となっている。In general, tin whiskers that occur on the tin-plated external terminals of semiconductor packages occur as needle-shaped crystals of tin that grow from the tin-plated surface as quickly as a few days or as slowly as several years. also grows. If this tin voice car occurs, it may cause a short circuit in electric f/circuits, and countermeasures are essential for computers and communication equipment that require high reliability.
従来、錫ボイスカーの発生、成長の確認試験では、錫め
っき端子を有する半導体パッケージ等を所定の環境下で
長時間放置し、定期的に錫ボイスカーの観察調査を行っ
ていた。この観察調査は、主に数十倍の拡大鏡により行
われる。Conventionally, in tests to confirm the generation and growth of tin voice ker, semiconductor packages with tin-plated terminals were left in a predetermined environment for a long period of time, and tin voice ker was observed and investigated periodically. This observational investigation is mainly performed using a magnifying glass of several tens of times.
ところで、錫ホイスカーの発生には長時間を要し、錫ボ
イスカーを観察できずに当該半導体パッケージの優位差
を確認できない場合が多く、システムへ組み込んで数年
後に錫ホイスカーが発生して問題となる場合がある。す
なわち、錫ホイスカーの確認調査に長時間貸しても、該
錫ホイスカーの発生の有無を明確に判断できないという
問題がある。By the way, it takes a long time for tin whiskers to occur, and it is often impossible to confirm the superiority of the semiconductor package because it is not possible to observe the tin voice ker.Tin whiskers can occur several years after being incorporated into a system, causing problems. There are cases. That is, there is a problem in that even if the tester is used for a long time to confirm tin whiskers, it is not possible to clearly determine whether or not tin whiskers are generated.
そこで、本発明は上記課題に鑑みなきれたもので、短時
間で錫ボイスカーの発生、成長の確認可能な半導体パッ
ケージ外部端子の表面試験方法を提供することを目的と
する。SUMMARY OF THE INVENTION The present invention was developed in view of the above-mentioned problems, and it is an object of the present invention to provide a method for testing the surface of external terminals of a semiconductor package, which allows confirmation of the generation and growth of tin voice ker in a short period of time.
本発明は上記課題を解決するために、半導体パッケージ
における錫めっきされた外部端子の一部分に、インジウ
ム系又はビスマス系のはんだを付着し、該はんだが付着
された外部端子を有する前記半導体パッケージを、所定
の環境下で所定時間放置し、該所定時間経過後に該外部
端子の表面を確認するように構成する。In order to solve the above problems, the present invention attaches indium-based or bismuth-based solder to a portion of the tin-plated external terminal of a semiconductor package, and provides the semiconductor package having the external terminal to which the solder is attached. The device is configured to be left in a predetermined environment for a predetermined period of time, and to check the surface of the external terminal after the elapse of the predetermined period.
上述のように、外部端子にインジウム系又はビスマス系
のはんだを付着し、所定環境下で所定時間放置する。こ
れにより、錫ボイスカーが発生するものは数日乃至数週
間で発生する。As described above, indium-based or bismuth-based solder is attached to the external terminals and left in a predetermined environment for a predetermined period of time. As a result, tin voice cars occur within a few days to a few weeks.
従って、各種錫めっき端子を有する半導体パッケージ間
の優位差を確認することが可能となり、錫ホイスカーの
発生、成長状況を短時間で判断することが可能となる。Therefore, it becomes possible to confirm the superiority difference between semiconductor packages having various types of tin-plated terminals, and it becomes possible to judge the occurrence and growth status of tin whiskers in a short time.
第１図に本発明の一実施例の説明図を示し、第２図に第
１図における第２Ａ及び第２８の工程の概念図を示す。FIG. 1 shows an explanatory diagram of an embodiment of the present invention, and FIG. 2 shows a conceptual diagram of steps 2A and 28 in FIG. 1.
図において、半導体パッケージ１の外部端子２の錫めつ
き３を行う（第１の工程）。In the figure, tin plating 3 is performed on the external terminals 2 of the semiconductor package 1 (first step).
これを外部端子２の錫めつき３の一部分、例えば、シー
テイングブレーン２ａ付近まではんだ５を付着する（第
１図第２Ａの工程、第２図（Ａ））。Solder 5 is applied to a portion of the tin plating 3 of the external terminal 2, for example, to the vicinity of the seating brain 2a (step 2A in FIG. 1, FIG. 2A).
又は、外部端子２に錫めつき３を行った半導体パッケー
ジをプリント基板４に実装して、外部端子２にはんだ５
を付着する（第１図第２Ｂの工程、第２図（Ｂ））。Alternatively, a semiconductor package whose external terminals 2 are tinned 3 is mounted on a printed circuit board 4, and solder 5 is applied to the external terminals 2.
(Step of FIG. 1, FIG. 2B, FIG. 2(B)).
ここで、はんだ５は、インジウム系の例えばインジウム
・錫（Ｉｎ−８ｎ）の共晶合金はんだ、又はビスマス系
の例えばビスマス・鉛・錫（Ｂｉ−Ｐｂ−３ｎ）の共晶
合金はんだが用いられる。Here, the solder 5 is an indium-based eutectic alloy solder such as indium-tin (In-8n), or a bismuth-based eutectic alloy solder such as bismuth-lead-tin (Bi-Pb-3n). .
次に、第２Ａ及び第２Ｂの工程における半導体パッケー
ジ１を所定環境下で所定時間放置する（第３の工程）。Next, the semiconductor package 1 in the steps 2A and 2B is left for a predetermined time in a predetermined environment (third step).
例えば、温度５０℃の環境下で数日乃至数週間放置する
。そして、外部端子２の表面での錫ホイスカーの発生、
成長の状態を観察確認するものである（第４の工程）。For example, it is left in an environment at a temperature of 50° C. for several days to several weeks. Then, the generation of tin whiskers on the surface of the external terminal 2,
This is to observe and confirm the state of growth (fourth step).
そこで、錫ホイスカーが発生、成長の放置時間に対する
結果を第１表及び第２表に示す。Therefore, Tables 1 and 2 show the results of tin whisker generation and growth with respect to the standing time.
第１表は、外部端子２に直接はんだ５を付着させた場合
の錫ホイスカーの発生、成長の表である。Table 1 shows the generation and growth of tin whiskers when the solder 5 is directly attached to the external terminal 2.
ここで、半導体パッケージ１はサーデイツプタイプパッ
ケージを用い、外部端子２にフラックス（ミル規格ＭＩ
Ｌ−Ｆ−１４２５６ＴＹＰＥ ＲＭＡ相当）を塗布し
た後はんだ５を付着させた。試料１はＩｎ−３ｎ共品合
金はんだを用い、試料２はＢ１−Ｐｂ−３ｎ共晶合金は
んだを用い、試料３は錫・鉛（Ｓｎ−Ｐｂ ）共晶合金
はんだを用いたもので、試料４ははんだ５を付着させな
い場合である。これらを温度５０℃で恒温放置して、錫
ボイスカーの発生、成長の結果を調べたものである。Here, the semiconductor package 1 is a deep dip type package, and the external terminals 2 are filled with flux (mil standard MI).
LF-14256TYPE RMA equivalent) was applied, and then solder 5 was applied. Sample 1 uses In-3n eutectic alloy solder, Sample 2 uses B1-Pb-3n eutectic alloy solder, and Sample 3 uses tin-lead (Sn-Pb) eutectic alloy solder. 4 is the case where the solder 5 is not attached. These were left at a constant temperature of 50° C., and the results of the generation and growth of tin voice ker were investigated.
第 １ 表
では、錫ホイスカーの発生が確認されず、試料３におい
ても確認されなかった。これに対して、試料１及び試料
２は４８時間後から錫ホイスカーの発生が確認され、試
料１に至っては３３６時間後に０．８０履の成長が確認
された。すなわち、インジウム系はんだ又はビスマス系
はんだを用い、５０℃で恒温放置することにより、錫ボ
イスカーの発生、成長が加速されることが認められる。In Table 1, the occurrence of tin whiskers was not confirmed, nor was it confirmed in Sample 3. On the other hand, in Samples 1 and 2, the generation of tin whiskers was confirmed after 48 hours, and in Sample 1, growth of 0.80 tin whiskers was confirmed after 336 hours. That is, it is recognized that the generation and growth of tin voice ker is accelerated by using indium-based solder or bismuth-based solder and leaving it at a constant temperature of 50°C.
以上の結果は、上記試料１〜４をプリント基板に実装し
た場合も同様であった。The above results were the same when Samples 1 to 4 were mounted on a printed circuit board.
第２表は、錫めっき外部端子を有するか一デイツプタイ
プの半導体パッケージ４種について、錫ボイスカーの発
生、成長の結果を調べたもので、はんだは）ｎ−３ｎ共
晶合金はんだを用いた。試料Ａ−Ｄは一般市販の同種の
半導体パッケージであり、それぞれにおいて錫めっき３
の方法が異なる場合の錫ボイスカーの発生、成長を調べ
たものである。これは、例えば、錫めっきには酸性浴と
アルカリ性浴があり、製造メーカーによりそれぞれ添加
剤等も異なるからである。Table 2 shows the results of the generation and growth of tin voice cars in four types of dip-type semiconductor packages having tin-plated external terminals, using an n-3n eutectic alloy solder. Samples A-D are generally commercially available semiconductor packages of the same type, each with tin plating 3.
The generation and growth of tin voice ker was investigated using different methods. This is because, for example, there are acid baths and alkaline baths for tin plating, and the additives and the like differ depending on the manufacturer.
第 ２ 表
験によれば錫ボイスカーの発生のし易さ等を明確に調査
することができた。なお、上記試料Ａ−Ｄをプリント基
板４に実装した場合、及びＢ１−Ｐｂ−８ｎ共晶合金は
んだを用いた場合でも同様の傾向の結果が得られた。According to the second experiment, it was possible to clearly investigate the ease with which tin voice ker occurs. Note that similar results were obtained when the above samples A to D were mounted on the printed circuit board 4 and when B1-Pb-8n eutectic alloy solder was used.
第２表に示すように、試料Ａ−Ｃは４８時間後から錫ホ
イスカーの発生が確認され、試料りは３３６時間後から
錫ボイスカーの発生が確認された。As shown in Table 2, the generation of tin whiskers was confirmed in samples A to C after 48 hours, and the generation of tin voice scars was confirmed in samples A to 336 hours later.
すなわち、錫めっきが異なる場合であっても、発生時間
の差こそあるが、錫ボイスカーの発生が認められた。That is, even when the tin plating was different, tin voice ker was observed to occur, although there was a difference in the time it took to occur.
従来方法では試料Ａ−Ｄの錫ホイスカーの発生がみられ
ず優位性を判断できなかったが、上記試〔発明の効果〕
以上のように本発明によれば、錫めっきされた外部端子
にインジウム系又はビスマス系のはんだを付着させて所
定の環境下で放置することにより、錫ボイスカーの発生
、成長が加速されて短時間で確認することができ、錫ホ
イスカーの発生し難い錫めっき技術の開発及び錫ホイス
カーの発生し難い半導体パッケージの選択を可能にする
ことができると共に、当該半導体パッケージを使用した
システム全体の信頼性を向上させることができる。In the conventional method, no tin whiskers were observed in Samples A to D, and the superiority could not be determined, but as described above, according to the present invention, indium was added to the tin-plated external terminal Development of a tin plating technology that makes it difficult for tin whiskers to occur by attaching a type or bismuth type solder and leaving it in a specified environment to accelerate the generation and growth of tin voice cars, which can be confirmed in a short time. It is possible to select a semiconductor package in which tin whiskers are unlikely to occur, and the reliability of the entire system using the semiconductor package can be improved.
第１図は本発明の一実施例の説明図、 第２図は第２Ａ及び第２Ｂの工程の概念図である。 図において、 １は半導体パッケージ、 ２は外部端子、 ３は錫めっき、 ４はプリント基板、 ５ははんだ を示す。 FIG. 1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is a conceptual diagram of steps 2A and 2B. In the figure, 1 is a semiconductor package, 2 is an external terminal, 3 is tin plating, 4 is a printed circuit board, 5 is solder shows.
Claims (1)
外部端子（２）の一部分に、インジウム系又はビスマス
系のはんだ（５）を付着し、 該はんだ（５）が付着された外部端子（２）を有する前
記半導体パッケージ（１）を、所定の環境下で所定時間
放置し、 該所定時間経過後に該外部端子（２）の表面を確認する
ことを特徴とする半導体パッケージ外部端子の表面試験
方法。[Claims] Indium-based or bismuth-based solder (5) is attached to a portion of the tin-plated (3) external terminal (2) of the semiconductor package (1), and the solder (5) is attached. The semiconductor package (1) having the external terminals (2) is left in a predetermined environment for a predetermined period of time, and the surface of the external terminals (2) is checked after the elapse of the predetermined period of time. Terminal surface testing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011690A JPH03234050A (en) | 1990-02-09 | 1990-02-09 | Surface testing method for external terminal of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011690A JPH03234050A (en) | 1990-02-09 | 1990-02-09 | Surface testing method for external terminal of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03234050A true JPH03234050A (en) | 1991-10-18 |
Family
ID=12294813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3011690A Pending JPH03234050A (en) | 1990-02-09 | 1990-02-09 | Surface testing method for external terminal of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03234050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180042615A (en) * | 2016-10-18 | 2018-04-26 | 현대자동차주식회사 | Apparatus and method for lead-free soldering in vehicular electronics |
-
1990
- 1990-02-09 JP JP3011690A patent/JPH03234050A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180042615A (en) * | 2016-10-18 | 2018-04-26 | 현대자동차주식회사 | Apparatus and method for lead-free soldering in vehicular electronics |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7105383B2 (en) | Packaged semiconductor with coated leads and method therefore | |
| CN111579972A (en) | Service life detection method for PCBA board-level component | |
| Brusse | Tin whisker observations on pure tin-plated ceramic chip capacitors | |
| JPH03234050A (en) | Surface testing method for external terminal of semiconductor package | |
| Vo et al. | Tin whisker test standardization | |
| Gilg et al. | Known good die | |
| JP2002323528A (en) | Test method and testing fixture | |
| Turner et al. | A study into the re‐processing of pure tin termination finishes into tin‐lead | |
| JPS607200A (en) | Method of attaching part to printed board | |
| JPH03234049A (en) | Surface treatment for external terminal of semiconductor package | |
| JPH0240931A (en) | Manufacture of hybrid integrated circuit device | |
| JPH03190063A (en) | Terminal pin for semiconductor chip carrier | |
| Shaddock et al. | DIP test socket characterization for 300° C | |
| JP2910802B2 (en) | Inspection method for semiconductor device | |
| JPH0282634A (en) | Tape carrier | |
| Osterman | Assessing the risk posed by tin whiskers | |
| Ling et al. | Development and Qualification of the Hypertronics Stackable Connector for RBSP mission | |
| JPS6329273A (en) | Burn-in substrate | |
| Pauls | Test vehicles in surface insulation resistance testing | |
| JP2000077448A (en) | Forming method of bump electrode by plating | |
| Joly et al. | Surface mounting of very fine pitch components: a new challenge | |
| JP2003149287A (en) | Method and apparatus for inspecting semiconductor integrated circuit | |
| JPH0425045A (en) | Manufacture of ic module | |
| Kenyon | Nonionic Contamination Prevention—The Next Step Toward Guaranteed Printed Wiring Assembly Reliability | |
| JPS62250687A (en) | Method of mounting electronic parts |