JPH03232395A - Video signal converter - Google Patents

Abstract

PURPOSE:To convert a video signal to a video signal, which can be displayed by a normal television receiver, by inputting (Y)i, (R-Y)i, (Y)i+1, (B-Y)i+1 for one horizontal line and read out of a frame memory during a fixed period, simultaneously outputting the (Y)i, (R-Y)i, (B-Y)i+1 at same time and simultaneously outputting the (Y)i+1, (R-Y)i, and (B-Y)i+1 at same time during the next horizontal period. CONSTITUTION:A video signal converter is equipped with a line memory 10 in an input step and a frame memory 12 in double layer structure. The video signal, namely, a luminance signal is applied to the line memory 10 within one frame by a non-interlace system, and the video signals to be selectively and alternately color difference signals R-Y and B-Y continuously after the luminance signal are inputted by a clock frequency 13.5MHz for each horizontal line within each horizontal period. The video signal (Y, R-Y) or (Y, B-Y) for one line is written into the frame memory 12 next after being outputted from the line memory 10 by a 20.25MHz clock.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a video signal conversion device, and more particularly to a device for converting a video signal whose information has been compressed in a predetermined format into a normal video signal. [Prior Art] FIG. 11 shows an example of an image formant to which the present invention is symmetrical. According to this format, the sampling clock frequency is 13.5 MHz. For each frame image consisting of 858 total pixels in the X (horizontal) direction and 525 total lines in the Y (vertical) direction, the luminance signal Y and color difference signal R are processed in the X direction using band compression technology. -Y and B-Y pixels are each 352
, 176 , 176 , Y in the Y direction
, RY, B-Y are each 2 i+23 (i=o,
・・・・・・・・・239)4 i+23 (i=0.・
......119), 4i+25 (i=o,...
...119) is compressed into a horizontal line defined by That is, according to this format, there are 240 (2i+23) horizontal lines [23F, [25], ... [499] in one frame in a non-interlaced manner.
, [5011 are given, among which the first set (4i+23)
each horizontal line of

[23], [27], ... [499]
], Y for 352 pixels is given, and the Y
After that, RY for 176 pixels is given, and the second
Each horizontal line of M(4i + 25) [25], [
29]...[501], Y for 352 pixels is given, and subsequently, B-Y for 176 pixels is given. Such a format is used, for example, for information compression for recording images on a CD-ROM. [Problems to be Solved by the Invention] By the way, when a video signal of the above-mentioned formant is
-Even if it is reproduced from ROM etc., the luminance signal Y and the color difference signal R-
Since the times of Y and B-Y are different from each other, it cannot be displayed on a normal television receiver as it is. Also, even if interlace conversion is performed, the number of pixels in Y is (352X240),
Since the number of pixels of R-Y and B-Y is compressed to (178×120), there is a problem in that the screen is displayed on a screen reduced to about 1/2 of the normal size. The present invention has been made in view of such problems, and the luminance signal Y is provided in a non-interlaced manner within one frame, and color difference signals R-Y, B- are provided following Y during each horizontal period. It is an object of the present invention to provide a new video signal conversion device for converting a video signal in a format in which Y is given selectively and alternately into a video signal that can be displayed on a normal television receiver. Another object of the present invention is to provide a video signal conversion device for converting a video signal in the above format into a video signal that can be displayed on an enlarged screen on a normal television receiver. [Means for Solving the Problems] In order to achieve the above object, the first video signal conversion device of the present invention provides a luminance signal Y within one frame in a non-interlaced manner, and provides a luminance signal Y during each horizontal period. A video signal conversion method for converting a video signal in a format in which a luminance signal Y is followed by color difference signals R-Y and B-Y selectively and alternately into a video signal that can be displayed on a television receiver. The apparatus includes a first field memory for storing Y of the video signal applied in each horizontal period, and R-Y, B of the video signal applied alternately in each horizontal period.
- a frame memory consisting of a second field memory for storing Y; Y given during the same horizontal period;
Write R-Y to the first and second field memories at addresses corresponding to each other, and write Y and B-Y given during the same horizontal period to the first and second field memories, respectively, at addresses corresponding to each other. a write control means for writing; one horizontal line worth of (
Y )i, (R-\)t are read from the first and second field memories at mutually corresponding addresses, and (Y)i+tt (Y)i+tt (
(Y)i for one horizontal line read from the frame memory during a certain period; , (RY
Input H, (Y)++i, (B-Y)i+i, output (YN, (RY)i. CB-Y)i+1 at the same time and simultaneously during one horizontal period, and output the next one at the same time. During the horizontal period (Y )i+1. (RY)i
, (B-Y)1+1 are arranged in time and are output simultaneously. In the first video signal conversion device, the preferred readout control means according to the present invention includes a low address generating means for generating a low address 1/s that starts from a constant initial value and increments every l horizontal period; The present invention is configured to include column address generating means that generates a column address that starts from a constant initial value and increments at a constant cycle twice in one horizontal period. Further, in order to enlarge the screen in the video signal conversion device, the delay means (Y)II (R-Y)i
, (Y)i41. (B-Y)i+1 was configured to be output at a clock frequency that is 1/2 of the sampling clock frequency of the pre-conversion video signal. In the second video signal conversion device of the present invention, the luminance signal Y is provided within one frame in a non-interlaced manner, and the color difference signal R-
A video signal converting device for converting a video signal in a format in which Y and B-Y are given alternatively and alternately into a video signal that can be displayed on a television receiver, the above video signal being given in each horizontal period. The first step for accumulating Y of the video signal
and a second field memory for storing the video signals R-Y, B-Y given alternately every horizontal period; Y given during the same horizontal period; Write R-Y to the first and second field memories at addresses corresponding to each other, and write Y and B-Y given during the same horizontal period to the first and second field memories, respectively, at addresses corresponding to each other. Write control means for writing: 11
(Y)i for one horizontal line during the horizontal interval, (R-Y
)1 from the first and second field memories respectively at addresses corresponding to each other.The next horizontal period is set as a reading pause period, and (Y)i+1, CB-Y for one horizontal line is read during the next horizontal period. ) readout control means for reading i+1 from the first and second field memories at addresses corresponding to each other and making the next one horizontal period a readout pause period; one horizontal period read from the frame memory during a certain period; (Y)i, (R
-Y )i, (Y Hat, (B -y)i
+i is input and (Y)L (R-Y
)i, (B - Y)i11 at the same time and at the same time 1/4 of the sampling clock frequency of the video signal before conversion
output at a clock frequency of (Y)i+1. . (RY)L (B-Y) 141 at the same time and output at a clock frequency that is 1/4 of the sampling clock frequency of the pre-conversion video signal, and the next horizontal period is the output suspension period.Delay means and an interpolation means that performs predetermined interpolation processing on the data output from the delay means. In the second video signal conversion device, the preferred readout control means according to the present invention is a row address generation means that generates a row address incremented every two horizontal periods starting from an initial value that can be set to any value. and column address generating means that generates a column address twice in one horizontal period, which starts from an initial value that can be set to any value and increments at a constant cycle. Further, in the first or second video signal conversion device, the preferred write control means according to the present invention is a row address generation means for generating a row address that starts from a fixed initial value and increments at a fixed period. and; in-column address generation means that generates column addresses that start from a constant initial value and increment at a constant cycle twice in one horizontal period. [Function] The present invention uses a frame memory consisting of two layers of field memory, stores Y of the pre-conversion video signal in the first field memory, and stores R-Y, B- in the second field memory.
Accumulate Y alternately. At that time, Y and R-Y, Y and B-Y given in the same horizontal period are assigned to the first . Write to second field memory. A preferred write control means for this write provides a row address that starts from a certain initial value and increments at a certain period, and at the same time increments a column address starting from a certain first address within a certain period of time. By applying the same row address twice, Y and R-Y and Y and B-Y of the same horizontal line are respectively written into the memory with the same row address. When reading from the frame memory, reading of Y and RY and reading of Y and BY are alternately repeated at a constant cycle. In the first video signal conversion device, (Y)i, (R-Y
) t, and (Y ) 141. for one horizontal line.
(B-Y)i+1 are read at mutually corresponding addresses. Preferred readout control means for this purpose starts from a constant initial value (typically the row address of the first row) and increments the row address every horizontal period, while at the same time starting from a constant initial value (typically the row address of the first row). Starting from the column address (typically the column address of the first column), the column address is incremented at a constant period (read clock frequency) to a predetermined value (the last column address), and then returned to the above-mentioned initial value; Generation of such column addresses is repeated twice during one horizontal period. This allows you to use the same address for one horizontal line (
Y )i, (R-Y)z and (Y)1+1 for one horizontal line. (B-Y)1+1 is read from the frame memory. In this way, one horizontal line ((
Y )t, (RY)I and (Y
)I÷1. (B - Y )1+1 is written to the delay means and from there (Y)s, (R-Yl+
, CB -Y )ill are output at the same time and at the same time, and during the next horizontal period (Y )1+1 . (R-Y
)i, (B - Y)1+1 are output at the same time and at the same time. As a result, a video signal that can be displayed on an ordinary television receiver is obtained. Note that by setting the read clock frequency (for example, 13.5 MHz) of the delay means to 1/2 (6.75 MHz) of the sampling clock frequency of the pre-conversion video signal, the display range per pixel in the horizontal direction is expanded. Furthermore, the entire screen can be enlarged and displayed. In the second video signal conversion device, for screen enlargement display,
In one horizontal period ff1 (every two horizontal periods), one horizontal line's worth of (Y )i, (RY)i and one horizontal line's worth of (
Y)i11. (B-Y)i+1 are read from the first and second field memories at addresses corresponding to each other, and (Y)i, (R-Y)i, (
B - Y) January and one horizontal line (Y ) ILL
(RY)t. (B-Y)1+1 are read out at the same time and at the same time at a clock frequency that is 1/4 of the sampling clock frequency of the pre-conversion video signal. As a result, gaps are created between individual pixel data, but a good enlarged image can be obtained by interpolating by inserting appropriate data into these gaps by the interpolation means at the subsequent stage of the delay means. For example, if the pre-conversion sampling clock frequency is 13.5 MHz (352
The (178x120) pixels in the x240) pixel screen are
The sampling clock frequency is 6.75MHz (35
2x240) pixels and displayed on a regular television receiver. In the preferred readout control means for the second video signal conversion device, the range of the video signal to be read from the frame memory can be arbitrarily selected by setting the initial values of the row address and column address to arbitrary values. However, this allows you to enlarge the screen at any position within the screen. [Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Actual "Example E" - FIG. 1 is a block diagram of a video signal conversion device according to a first embodiment. This device includes a line memory 10 at the input stage, a frame memory 12 with a two-layer structure, and line memories (14A, 14B) at the output stage. (18A, 16B), (18A, 18B), a frame memory control circuit 20 for controlling writing/reading of the frame memory 12, a write address generation circuit 30, a read address generation circuit 40, and an address switching circuit 50. , and an output line memory control circuit 60 for controlling writing/reading of the output line memories 14A to 18B. To the line memory 10, a video signal having the format described above with reference to FIG. -Y, B-Y
A video signal in which the signals are selectively and alternately provided is inputted one horizontal line at a time at a clock frequency of 13.5 MHz. This one line worth of video signal (Y, RY) or (Y, B-Y) is then outputted from the line memory 10 at 20.25 MH2 (7) clocks and sent to the frame memory 10.
Written to 2. In writing, the frame memory 12
receives control signals such as a write control signal and a chip select signal from the frame memory control circuit 2°, and also receives a write address from the write address generation circuit 3o via the address switching circuit 50. FIG. 2 shows the address structure of the frame memory 12. As shown in the figure, this frame memory 12 consists of a first field memory 12A for Y storage and a second field memory 12B for R-Y and B-Ygm. The first field memories 12A each have (256×25θ)
It consists of a two-phase field memory MO, Ml of capacity, each phase having 176 column addresses and 240 row addresses. The second field memory 12B is (2
A single memory of 58x256) capacity with 176 column addresses and 240 row addresses. With such a memory configuration, Y and R-Y and Y and B-Y of the same horizontal line in one frame are stored in the first and second field memo 1J12A, respectively, at the same address.
The data is stored in 12B. In other words, the horizontal line according to the formant in Figure 9

[2
3] Y, R-Y are given 1; then their Y, R-
The data of Y is stored in the first and second field memories 12A.
At this time, 352 pieces of Y data are alternately distributed one by one to the two phases MO and Ml. Then the horizontal line

When Y and B-Y of [25] are given, those Y and B-Y data are written to the second row of the first and second field memories 12A, respectively, and at that time, 352 pieces of data are also written. The Y data is alternately distributed one by one to the two phases MO and Ml. Similarly, horizontal line

[27] Y, RY are both memories 12A, 12
written in the third row of B, respectively, and the horizontal line

[29]
Y and BY are respectively written in the fourth row of both memories 12A and 12B. In this way, each horizontal line (4
i+23] are stored in the first and second field memories 12A, 12B at the same address, and Y and B-Y of each horizontal line [4i+251 are stored in both field memories 12A, 12B at the same address. Accumulated. FIG. 3 shows a write address generation circuit 30 according to this embodiment,
Read address generation circuit 40 and address switching circuit 50
An example of a specific circuit configuration is shown below. Write address generation circuit 30
consists of an address counter 32 for generating row addresses and an address counter 34 for generating column addresses. The read address generation circuit 40 similarly includes an address counter 42 for generating row addresses and an address counter 44 for generating column addresses. The address switching circuit 50 includes a multiplexer 52 for switching row addresses and a multiplexer 54 for switching column Φ addresses. In the write address generation circuit 30, the row address
The counter 32 constantly receives "O" data at the precent value input terminal, receives WYLOAD from the control circuit 20 at the load terminal LD every frame, and receives DISP from the control circuit 20 at the clock input terminal CK for two horizontal periods. A row address for writing is generated starting from an initial value (“0”) and incrementing by 1 every two horizontal periods within each frame period. The column address fist counter 34 is
“0” data is constantly received at the preset value input terminal, and WXLOAD is set to 1 from the control circuit 20 at the load terminal LD.
WCK is received twice in each horizontal period, and WCK is received at the input clock frequency (20, 25 MHz) while data is being input from the control circuit 20 to the clock input terminal CK, and the clock signal starts from the initial value (“O”) within each horizontal period. Generates a column address for writing twice, incrementing by one every WCK. 4 and 5 show the write operation of the frame memory 12. During writing, the control signal C0N from the control circuit 20
According to T, both multiplexers 52 and 54 of the address switching circuit 50 are respectively switched to the write address generation circuit 30 side. At the timing within the horizontal period in FIG. 4, immediately after the horizontal synchronization signal, the load signal WYLOAD is in the enabled state (“
When DISP rises to "H" (FIG. 4 (E), (F)) under "L"), the row address 0 counter 32 is loaded with the initial value "0" in response. When the write clock signal WCK is input in synchronization with the input data while the load 'M number W
)) In response to the rising edge of the first clock, the column address counter 34 is loaded with an initial value "0" and starts counting WCK from this initial value. After loading the initial value as described above, the load signal WYLOA
D, WXLOAD becomes “H” (Fig. 4 (D), (E
)). On the other hand, at this time, in the frame memory 12,
The first field memo IJ 12 A has been switched to write mode by the control circuit 20. Therefore, from the row address 0 counter 32, the first field memory 1
A row address indicating the first row of 2A is generated, and the column address counter 34 synchronizes with WCK from the initial value AO (0) to AI (1), A2 (2), etc.
A column address is generated that increments up to 17G (176), which causes the horizontal line

The 352 data of Y in [23] are stored in the two-phase MO, Ml of the first field memory 12A.
is written to the first line of Just before the end of writing Y, the load signal WXLOAD once falls to "L" and then rises to "H" (FIG. 4(D)). As a result, the column address 0 counter 34 is loaded with the initial value (“0”) again, the column address returns to the initial value AO(0), and is again incremented one by one from the initial value. On the other hand, in the frame memory 12, the second field memory 12B is switched to write mode. This creates a horizontal line

[23] R-
The 176 pieces of data of Y are written to the first row of the second field memory 12A. In this way, the horizontal line

When the writing of Y and RY in [23] is completed and the next horizontal synchronizing signal comes, DISP changes to "L", and when the next horizontal period starts, it rises to "H" (Fig. 5). (C), <D)). In response to this rise, the row address counter 32 counts up, and the row address becomes a value specifying the second row of the field memories 12A, 12B. However, by the same operation as above, the horizontal line

[25]Y,
B-Y are the first and second field memories 1, respectively;
Written in the second line of 2A and 12B (Figure 5 (B))
. In this way, Y of the pre-conversion video signal is sequentially written to each row of the first field memory 12A for each horizontal line, and R-Y and B-Y of the pre-conversion video signal are written to the second field memory 12B for each horizontal line. are written alternately on each line. Next, the reading operation of the frame memory 12 will be explained. In the read address generation circuit 4o of FIG.
The address counter 42 constantly receives "0" data at the preset value input terminal, receives RYLOAD every frame from the control circuit 2o at the load terminal LD, and receives DISP 2 from the control circuit 20 at the clock input terminal CK. It is received every horizontal period, and the initial value (“
A row address for reading is generated starting from "0") and incremented by 1 every horizontal period.The row address counter 32 constantly receives "0" data from the preset value input terminal. RX from control circuit 20 to load terminal LD
LOAD is received twice every horizontal period, RCK is received at the output clock frequency (20, 25 MHz) while data is being input from the control circuit 20 to the clock input terminal CK, and the value is changed from the initial value (“0”) within each horizontal period. 1 for every RCK starting
Generates two incremented column addresses for reading. 6 and 7 show the read operation of the frame memory 12. When reading, the control signal C0N from the control circuit 20
According to T, both multiplexers 52 and 54 of the address switching circuit 50 are respectively switched to the read address generation circuit 40 side. At the timing within the horizontal period in FIG. 6, immediately after the horizontal synchronization signal, the load signal RYLOAD is in the enabled state (“
When DISP rises to "H" under "L") (FIG. 6 (F), (G)), the low fist address counter 42 is loaded with the initial value "0" in response. Load signal RXLOAD is enabled (“L”)
), when the read clock signal RCK is input (FIG. 4 (B), (C), (E)), the column address counter 44 changes to the initial value "0" in response to the rising edge of the first clock. is loaded and starts counting RCK from this initial value. After loading the initial values as described above, the load signal RYL
OAD and RXLOAD become “H” (Fig. 4 (E)
, (F)). On the other hand, at this time, in the frame memory 12, the first field memo 1J12A is switched to the read mode by the control circuit 20. Thus, a row address indicating the first row of the first field memory 12A is generated by the row address counter 42,
Column Φ address counter 44 synchronizes with RCK from initial value AO (0) to AI (1), A2 (2), etc.
A column address incrementing up to Al7G (176) is generated, which causes the horizontal line to be read from the first field memory 12A.

Y of [23] is read out. Just before the end of reading Y, the load signal RXLOAD once falls to "L" and then rises to "H" (
Figure 4(E)). As a result, the initial value ("0") is loaded into the column address counter 44 again, the column address returns to the initial value AO(0), and is again incremented one by one from the initial value. On the other hand, in the frame memory 12, the second field memory 12B is switched to the read mode. As a result, the first field memory 12A
Horizontal line from the first row of

RY of [23] is read out. In this way, the horizontal line

When the reading of Y and RY in [23] is completed, DISP changes to “L” and rises to “H” when the next horizontal period starts (6th
Figure (G), Figure 7 (C), (D)). In response to this rise, the low address counter 32 counts up, and the low address is field memo 1J12A,
This is the value that specifies the second row of 12B. By the same operation as above, the first and second field memories 1
Horizontal line from 2B

Y and B-Y of [25] are respectively read out (FIG. 5(B)). In this way, Y, RY and Y, BY are alternately read out from the first and second field memories 12A and 12B every horizontal period. Next, the operation of the output line memos 1J14A to 18B will be explained. These line memories operate as follows in response to control signals and clocks from the output line memory control circuit 60. First, in the horizontal period HDO, the horizontal line is read from the frame memory 12.

[23] (Y) 0. When (RY) 0 is output, (Y) 0 is stored in line memory 14A as 20.25
It is written with a MHz clock, and (RY)O is written into the line memory 16A with a 20.25 MHz clock. In the next horizontal period HD1, (Y)0 is read out from the line memory 14A with a clock of 6°75MHz, and at the same time, (Y)0 is read out from the line memory 18A at the same time.
RY)0 is read out with a 3.375MHz clock. On the other hand, during this horizontal period HDI, the frame memory 12
horizontal line read out

[2S] (Y)i, (B
-¥)1, (Y)1 is written to the line memory 14B, and (B-Y)1 is written to the line memory 18B. In the next horizontal period HD2, from the line memory 14B (
At the same time as Y)1 is read out with a 6°75MHz clock, (R
-Y)0 is the 3.375MHz clock again, and CB-Y)0 is 3.375MHz again from the line memory 18B.
It is read out using the clock. During this time, frame memory 1
Horizontal line output from 2

[27] (Y)2. (R
-Y)2 is written into the line memory 14A, and (RY)2 is written into the line memories 18A and 18B. Then, in the next horizontal period HD3, (Y)2. (RY)2
．． (B-Y)i are read out at the same time at the same time using the above clock. By the above operation, the device output terminal 70°72.7
4, the time axes are aligned with each other, and a video signal that can be displayed on an ordinary television receiver is obtained. Furthermore, in this embodiment, the read clock frequency of the output line memories 14A to 18B is 8.75 MHz, which is 1/2 of the sampling clock frequency of 13.5 MHz of the video signal before conversion, so that the display range of each pixel in the horizontal direction is is doubled, and as a result, the entire screen is enlarged and displayed twice. Support 91 Next, a second embodiment will be described with reference to FIGS. 9 and 10. This embodiment allows enlarged display at any position within the screen. For this purpose, in FIG. 9, output line memories (14A, 14B), (18A, 1
Interpolation circuits 80.82.84 and interpolation filters 90.92.94 are connected to the subsequent stages of 6B) and (18A. 18B), respectively. Furthermore, in FIG. 10, read address generation circuit 40'
row address counter 42, column address counter 42,
Each precent input terminal of the counter 44 has preset values PRESET Y and RRESET that can be set to any value externally (for example, from the control circuit 20).
X is given. As a result, when reading the frame memory 12, the row address from the row address counter 42 starts from PRESET Y, and the column address from the column address counter 44 starts from PRESET X for each horizontal period. . Furthermore, according to this embodiment, in order to enlarge the screen in the vertical direction,
DISP2 is applied every two horizontal periods, and reading from the frame memory 12 is performed every one horizontal period. That is, in the horizontal period HDO, (Y)0 has 176 data and (RY)0 has 8 data.
When 8 data have been read, the next horizontal period HD2 is a read pause period, and in the next horizontal period HD2 (YH, (B - Y
H is read out. In the line memories 14A to 18B, reading is also performed at intervals of one layer, for example, (Y)i during the horizontal period HDj.
, (RY)i, (B-Y)i+1 are read out at the same time and at the same time, the next horizontal period HDj
+l is the readout period, and the next horizontal period HD j+2
Inside (Y)i+1. (RY)i, (B
-Y Hat are read simultaneously at the same time, and the next horizontal period HDj+3 becomes a read suspension period. and,
In this embodiment, since the number of pixels is halved, the screen is enlarged in the horizontal direction. Therefore, Y is 3.3
It is read out with a 75 MHz clock, and RY and BY are read out with a 1.6875 MHz clock. The interpolation circuits 80, 82, and 84 consist of well-known "0" insertion circuits, and sample the video signals inputted from the line memories 14A to 18B at the upper and lower horizontal lines where no pixel data exists and at 8.75 MHz. Sometimes, the same data continues for two clocks, so data with the value "0" is inserted into the left and right dot positions. Interpolation filter 90,9
2.94 is a circuit with a well-known configuration, which smoothes the left and right vertical directions of each pixel. Due to the above operations and effects, the device output terminal 70.7
2.74 has a sampling frequency of 6.75 MHz (3
A video signal giving 52×240) pixel data is obtained, and this video signal is displayed on a television receiver on a normal television screen size. [Effects of the Invention] By having the above-described configuration, the present invention provides the following effects. According to the video signal conversion device of the first aspect, Y of the pre-conversion video signal is stored in the first field memory using a frame memory consisting of two layers of field memories, and R-Y, B
-Y is stored alternately in the second field memory, and at that time, Y and R-Y on the same line, and Y and B-Y are written at addresses corresponding to each other, and when reading, one line is stored at a constant cycle. Minutes (Y)i, (RY)
i and one line of (Y Hat, (RY)
Hat is read from the frame memory, and (Y)i, (R-Y) are read out during one horizontal period by the delay means.
L (B - Y )i+1 are output at the same time with the same time, and (Y)i+i, (R - Y ) are output during the next horizontal period.
Since the signals i and (B-Y)Hat are output at the same time at the same time, a video signal that can be displayed on a normal television receiver can be obtained. According to the video signal conversion device of claim 2, the row address is started from a constant initial value and incremented every horizontal period, and at the same time, the row address is started from a constant initial value twice during one horizontal period. By incrementing the column address at regular intervals, (Y)i for one horizontal line at the same address,
(RY)i or (Y)il for one horizontal line
Since l, (B-Y)j+1 is read from the frame memory, reading can be controlled with a simple circuit configuration. According to the video signal conversion device of claim 3, by setting the readout clock frequency of the delay means to 1/2 of the sampling clock frequency of the video signal before conversion, the display speed per pixel is expanded in the horizontal direction. It is also possible to enlarge and display the entire screen. According to the video signal conversion device of claim 4, (Y)i, (RY)j for one horizontal line and (R-Y)j for one horizontal line are stored in the frame memory at intervals of one horizontal period (every two horizontal periods).
Y)141. (B-Y)ill and (B-Y)ill are read out alternately, and (Y)i, (R-Y)i, (B-Y) for one horizontal line are read out from the delay means at intervals of one horizontal period.
ill and one horizontal line (Y)i+1, (R-
Y)i, (B-Y)! +1 are read out at the same time and at the same time at a clock frequency that is 1/4 of the sampling clock frequency of the video signal before conversion, and then interpolation is performed in the gaps between pixel data by the interpolation means, so that it can be used with a normal television receiver. A good enlarged screen can be obtained. According to the video signal conversion device of claim 5, in the device of claim 4, by making it possible to set the initial values of the row address and column address in the readout control means to arbitrary values, any arbitrary value in the screen can be set. You can enlarge the screen depending on the position. According to the video signal conversion device of claim 6, in the device of claim 1 or 4, the row address is incremented every horizontal period starting from a constant initial value, and at the same time, the row address is incremented twice during one horizontal period. By starting from a certain initial value and incrementing the column address at a certain period, one horizontal line's worth of (Y)i, (RY)+ or one horizontal line's worth of (Y) can be obtained with the same address. ill, (B-Y
) j+1 is written in the frame memory, so writing can be controlled with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a video signal conversion device according to the first embodiment of the present invention, FIG. 2 is a diagram showing the address structure of the frame memory 12 of the first embodiment, and FIG. is written to the frame memory 12 in FIG.
FIG. 4 is a timing diagram for explaining the write operation of the frame memory U 12; FIG. 5 is a block diagram showing the specific configuration of a circuit that controls reading; FIG. FIG. 8 is a timing diagram for explaining the read operation of the frame memory 12 according to the first embodiment, and FIG.
FIG. 8 is a timing diagram showing the write operation of the frame memory 12 according to the frame period according to the first embodiment.
FIG. 9 is a block diagram showing the overall configuration of the video signal conversion device according to the second embodiment. FIG. - A block diagram showing a specific configuration of a circuit for controlling readout, and FIG. 11 are diagrams showing an image diagram of a pre-conversion video signal to which the present invention is applied. 12 rivers/frame memory, 12A, 12B...field memory, 14A~1
8B...Line memory, 20...Frame memory control circuit, 30...Write address generation circuit, 32...Low medium address e counter for writing, 34...
...Writing column address e counter, 40.40
'...Read address generation circuit, 42.42'...
・Reading row address conflict counter, 44 (44')...Reading column address...
Counter, 50... Address switching circuit, 52.54... Multiplexer, 54... Latch circuit, 60... Output line memory control circuit, 80-84...
...Interpolation circuit, 90-94...Interpolation filter.

Claims (6)

[Claims] (1) The luminance signal Y is given in a non-interlaced manner within one frame, and the color difference signals R-Y and B-Y are alternatively and alternately given after the luminance signal Y during each horizontal period. A video signal conversion device for converting a video signal of such a format into a video signal that can be displayed on a television receiver, the device comprising: a first field memory for storing Y of the video signal given for each horizontal period; and R-Y, B-Y of the video signal alternately given every horizontal period.
A frame memory consisting of a second field memory for storing Y and R-Y given during the same horizontal period are written into the first and second field memories respectively at addresses corresponding to each other, and the same Y given during the horizontal period
, B-Y in the first and second field memories at mutually corresponding addresses, and (Y)i, ( for one horizontal line at a constant period).
R−Y)i is read from the first and second field memories at mutually corresponding addresses, and (Y)i+1 and (B−Y)i+1 for one horizontal line are read from the first and second field memories at mutually corresponding addresses. readout control means for reading each from the second field memory; and one readout from the frame memory during a certain period of time;
(Y)i, (RY)i, (Y)i+1 for horizontal lines
, (B-Y)i+1, and (Y)i during one horizontal period.
, (RY)i, and (B-Y)i+1 are output simultaneously at the same time, and (Y)i+1 and (RY)i+1 are output during the next horizontal period.
)i and (B-Y)i+1 at the same time and outputting them at the same time. (2) The read control means includes a row address generating means that generates a row address that starts from a certain initial value and increments every horizontal period; starts from a certain initial value and increments at a certain period. 2 column addresses in 1 horizontal period
2. The video signal converting apparatus according to claim 1, further comprising column address generating means for generating a column address every time. (3) The delay means includes (Y)i, (RY)i, (Y
)i+1 and (B-Y)i+1, respectively, at a clock frequency that is half the sampling clock frequency of the pre-conversion video signal. (4) The luminance signal Y is given in a non-interlaced manner within one frame, and the color difference signals R-Y and B-Y are alternatively and alternately given after the luminance signal Y during each horizontal period. A video signal conversion device for converting a video signal of such a format into a video signal that can be displayed on a television receiver, the device comprising: a first field memory for storing Y of the video signal given for each horizontal period; and R-Y, B-Y of the video signal alternately given every horizontal period.
A frame memory consisting of a second field memory for storing Y and R-Y given during the same horizontal period are written into the first and second field memories respectively at addresses corresponding to each other, and the same Y given during the horizontal period
, B-Y in the first and second field memories at mutually corresponding addresses, and (Y)i for one horizontal line during one horizontal period,
(RY)i is read from the first and second field memories at mutually corresponding addresses and the next one is read out.
A horizontal period is set as a reading pause period, and (Y)i+1 and (B-Y)i+1 for one horizontal line are read from the first and second field memories at mutually corresponding addresses during the next one horizontal period, readout control means that sets the next horizontal period as a readout pause period; and 1 readout from the frame memory during a certain period.
(Y)i, (RY)i, (Y)i+1 for horizontal lines
, (B-Y)i+1, and (Y)i during one horizontal period.
, (RY)i, (B-Y)i+1 are aligned in time and simultaneously set to 1/1 of the sampling clock frequency of the video signal before conversion.
4 clock frequency, the next horizontal period is an output suspension period, and (Y)i+1, (R-
A delay means for outputting Y)i and (B-Y)i+1 at the same time and at the same time at a clock frequency of 1/4 of the sampling clock frequency of the pre-conversion video signal, and setting the next horizontal period as an output suspension period; A video signal conversion device comprising: interpolation means that performs predetermined interpolation processing on data output from the delay means. (5) The read control means includes a row address generating means that generates a row address that starts from an initial value that can be set to any value and increments every two horizontal periods; 5. The video signal converting device according to claim 4, further comprising column address generating means that generates a column address that starts from a value and increments at a constant period twice in one horizontal period. (6) The write control means generates a row address that starts from a certain initial value and increments at a certain period.
Claim 1 or 4, characterized in that it comprises: address generation means; and column address generation means that generates a column address that starts from a constant initial value and increments at a constant cycle twice in one horizontal period. The video signal conversion device described in .