JPH03230754A - Switching power supply device - Google Patents

Abstract

PURPOSE:To reduce loss and enlarge output and make it into high frequency by changing the period when output voltage is applied to the secondary winding of a transformer by means of the switching means connected to the secondary winding of the transformer so as to control output voltage. CONSTITUTION:An FET 3 and a synchronous oscillating circuit 4 are provided on the primary side of a transformer 2, and an FET and a control circuit 7 are provide on the secondary side. The synchronous oscillating circuit 4 operates the FET 3 for the specified on period. The FET 5 comprises a channel 5b and a parasitic diode 5a. During the off period of the FET 3, the energy of the transformer 2 is discharged from a parasitic diode 5a to a smoothing capacitor 6 through a secondary winding 2c. After discharge, a secondary current flows from the smoothing capacitor 6 reversely to the transformer 2 through the channel 5b of the FET 5. This reverse flow period is controlled by a control circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a switching power supply device that supplies DC stabilized voltage to industrial and consumer electronic equipment.

Conventional technology Switching power supplies are used to reduce the cost, size, and size of electronic devices.
With the trend toward higher performance and energy savings, there is a strong demand for smaller, more stable outputs, and higher efficiency power supplies, and a regeneration-controlled switching power supply device with a circuit configuration as shown in FIG. 4 has been proposed.

The explanation will be given with reference to FIGS. 4 and 5.

In Fig. 4, 1 is a DC voltage or DC power source obtained by rectifying a commercial AC voltage, and 2 is a transformer with a primary winding 2a.
, primary bias winding 2b, secondary winding 2c, secondary winding 2c
It is equipped with a secondary bias winding 2d made by winding it up, 3 is the first switching element and is a field effect transistor (hereinafter referred to as FET), 3a is the parasitic diode of FET 3, and 3b is the channel of FET 3. The source is connected to the negative side of the DC power supply 1, and the drain is connected to one end of the primary winding 2a of the transformer 2. During the ON period of the FET 3, energy is stored in the transformer 2 through the channel 3b of the FET 3, and the energy is stored in the transformer 2 through the channel 3b of the FET 3. The energy stored in the transformer 2 is regenerated to the DC power supply 1 via the gastric diode 3a. 4 are resistors 41, 42, 43.
Capacitor 44°45, Zener diode 46. This is a synchronous oscillation circuit consisting of a bipolar transistor (hereinafter referred to as BPT) 47, which operates FET 3 in the required on period and continues the off period of FET 3 until the polarity of the induced voltage in the primary bias winding 2b of the transformer 2 is reversed. The oscillation is continued by repeating the on-off operation by turning off the oscilloscope for a sustained period of time. Reference numeral 5 denotes the second switching element, which is composed of an FET, 5a is the gastric diode of FET 5, 5b is the channel of FET 5, the source is connected to one end of the secondary winding 2c of the transformer 2, and the drain is connected to the smoothing capacitor 6. After the energy stored in the transformer 2 during the ON period of FET 3 is released from the gastric diode 5a of FET 5 to the smoothing capacitor 6 via the secondary winding 2c of the transformer 2 during the OFF period of FET 3,
This time, conversely, the control circuit 7 controls the reverse current period during which the secondary current flows from the smoothing capacitor 6 to the secondary winding 2c of the transformer 2 via the channel 5b of the FET 5. 7 is resistance 7
1°72.73.74. Error amplifier 75. Reference voltage 76
゜This is a control circuit for FET5 consisting of BPT77, which detects the output voltage Vo and compares it with the reference voltage 76 to determine the reference voltage 76.
When the voltage is higher than the reference voltage 76, the collector current of the BPT 77 is controlled to reduce the voltage drop across the resistor 71 (thereby increasing the gate-source voltage of the FET 5), and conversely, when it is lower than the reference voltage 76, the collector current of the BPT 77 is By increasing the voltage drop across resistor 71 and lowering the voltage between the gate and source of FET 5, the reverse flow period during which the secondary current flows is changed. It shows the voltage waveform VDSI at both ends, (b) shows the primary current 101 flowing through the primary winding 2a of the transformer 2, and (C) shows the drive pulse waveform VGSI of the synchronous oscillation circuit 4. (d) is the voltage waveform VO52 across FET5
, (e) shows the secondary current waveform ID2 flowing in the secondary winding 2C of the transformer 2, and (f) shows the secondary current waveform ID2 flowing in the secondary winding 2C of the transformer 2.
The drive pulse waveform V GS2 of 5 is shown, and the shaded period in the off period is when the secondary winding 2c of the transformer 2
It shows the reverse flow period during which the next current flows.

First, magnetic flux is generated in the transformer 2 by the primary current rot flowing through the primary winding 2a of the transformer 2 during the ON period of the FET 3, which operates with the ON period determined by the synchronous oscillation circuit 4, and energy is stored. At this time, 2 of transformer 2
An induced voltage is generated in the next windings 2c and 2d, but the structure is such that the voltage is applied in a direction that reverse biases the gastric diode 5a of the FET 5, and a reverse voltage is applied between the gate and source of the FET 5, so that the FET 5 Configured to turn off.

However, if No, the number of turns Np of the secondary bias winding 2d of the transformer 2 is the number of turns VIN of the primary winding 2a of the transformer 2 is the voltage VGS of the DC power supply 1 (max+ is the absolute maximum gate-source voltage of FET 5 It is voltage.

Next, when the FET 3 is turned off by the off signal of the synchronous oscillation circuit 4, a flyback voltage is generated in the primary winding 2a of the transformer 2, and at the same time, a flyback voltage is generated in the secondary winding 2c of the transformer 2.

2d also generates a flyback voltage and a voltage is applied in the direction of forward biasing the gastric diode 5a of the FET 5, so the energy stored in the transformer 2 or the secondary current flows through the secondary winding '1A2c of the transformer 2. The output voltage is emitted as a voltage Vo, is smoothed by a smoothing capacitor 6, and is supplied to the output terminal as an output voltage Vo.

At this time, the gate-source voltage VGS2 of FET5 has a time constant of 1. (1+ Controlled by control circuit 7 with one CR7+
R? The battery is charged to a voltage of 2 n VGS2, and the FET 5 is turned on.

However, C is the input capacitance R71 of the FET5, the resistance value R72 is the resistance value of the resistor 72, No is the number of turns of the secondary winding 2d of the transformer 2, and Ns is the number of turns of the secondary winding 2c of the transformer 2. Vo is the output voltage VF5 is the forward voltage I of the gastric diode 5a of FET5, and C77 is the collector current of BPT77 VGS2 (ll
ax) is the absolute maximum gate-source voltage of FET5.

All the energy stored in transformer 2 is released and 2
When the next current becomes zero, the voltage across the smoothing capacitor 6 is
That is, since the output voltage Vo is applied to the secondary winding 2c of the transformer 2, a secondary current flows in the opposite direction from the smoothing capacitor 6, and a magnetic flux in the opposite direction is generated in the transformer 2, and energy is accumulated. be done. In this state, the polarity of the induced voltage generated in each winding of the transformer 2 does not change, so the flyback voltage of the primary bias winding 2b of the transformer 2 also does not change, and the synchronous oscillation circuit 4 maintains the off period of the FET 3. The control circuit 7 controls the gate-source voltage, that is, the on-period of the FET 5, and when the FET 5 is turned off, the polarity of the induced voltage generated in each winding of the transformer 2 is reversed. The generated induced voltage reverse biases the gastric diode 5a of FET 5, and since FET 5 is also off, no secondary winding current flows (
The induced voltage generated in the primary winding 2a of the transformer 2 is F
The primary current 101 flows in the direction of charging the DC power supply 1 through the gastric diode 3a of the FET 3 because it is generated in the direction of making the connection end with the ET3 a negative voltage and the connection end with the DC power supply 1 a positive voltage. Energy accumulated in the transformer 2 during the off period is regenerated to the DC power supply 1. At this time, the polarity of the induced voltage generated in the primary bias winding 2b of the transformer 2 is also reversed, so the synchronous oscillation circuit 4 turns on the FET 3. When all the energy stored in the transformer 2 during the off period is released and the primary current becomes zero, the primary current in the opposite direction flows from the DC power supply 1 through the FET 3 which is already on, and the transformer 2, magnetic flux is generated and energy is accumulated. In this state, the polarity of the induced voltage generated in each winding of the transformer 2 does not change, and the synchronous oscillation circuit 4 keeps the FET 3 on. When the FET 3, which operates during the on period determined by the synchronous oscillation circuit 4, turns off,
The energy stored in the transformer 2 is released as a secondary current through the secondary winding 2c of the transformer 2.

By repeating these operations, the output voltage VO is supplied to the output terminal.

Furthermore, the operation for stably controlling the output voltage Vo will be explained in detail. Each operating waveform is shown in FIG. 5, and the off period (t
+~t3) is set as TOFF, of which the reverse flow period (t2~t3) of the dual current 102 is set as T'OFF, and on the other hand, the ON period (t
3 to t5) is TON, and when the regeneration period of the primary current IDI is TδN, the output current 10 is expressed as and the output voltage vo is expressed as .

However, LS is the inductance value of the secondary winding 2c of the transformer 2, NS is the number of turns NP of the secondary winding 2c of the transformer 2, T is the number of turns of the primary winding 2a of the transformer 2, and T is the oscillation period. = TON+ TOFFVIN is the voltage of the DC power supply 1.

That is, since the on period TON is kept at a constant value determined by the synchronous oscillation circuit 4, if the output voltage VO is constant, the off period T OFF is also constant, and the oscillation period T is also constant. The backflow period T'OFF can be changed by the FET 5 controlled by the control circuit 7, and when the output current 1o changes, the backflow period T'OFF changes if the output voltage vo is constant.
It can be controlled by changing OFF. Furthermore, I11 can be controlled by changing the reverse current period T'OFF even when the voltage of the DC power supply l changes.

In Fig. 5, the dotted line indicates no load when the output current 1o is zero, and when the reverse current is maximum, T'0FF-T O
FF, and the solid line indicates the maximum load when the output current Io is maximum, and T'0FF=O when the reverse current is zero.

Problems to be Solved by the Invention In the currently proposed circuit configuration as described above, (1) the voltage applied between the gate and source of the FET 5, which is the second switching element, is controlled using the voltage drop across the resistor; Therefore, the loss of the control circuit becomes large, and when the FET 5 is turned off, a reverse current flows due to a predetermined voltage applied between the gate and the source, and no more current can flow. That is, since turn-off is performed using the saturation characteristics of the FET, the switching loss of the FET 5 becomes large.

(2) In the control using the output current, in order to control the reverse flow period T'OFF during which the reverse current flows during a certain off-period of FET3, "r'oFF-AToF" is
p, and the reverse current is at its maximum. Therefore, the gate voltage between the gate and source of FET 5 that can sufficiently drive the maximum reverse current is set between the gate and source of FET 5 to minimize Ron loss.
must be applied within 2 T'OF from when FET3 is turned off. That is, it is necessary to set it as VGS2(ID2R).

However, VGS2 is the gate-source voltage of FET5, NG is the number of turns in the secondary bias winding 2d of transformer 2, NS is the number of turns in the secondary winding 2c of transformer 2, Vo is the output voltage, and VF5 is the Forward voltage of gastric diode 5a of FET5, R71 is resistance value of resistor 71, R72: resistance value of resistor 72, ! D2R is the maximum reverse current, VGS2 (ID2R) is the gate-source voltage required to drive the maximum reverse current ID2R determined by the characteristics of FET5, and C is the input capacitance of FET5.

Further, at the maximum load, T'opp=O, and the reverse current becomes zero, so it is necessary to make the gate-source voltage VO52 of the FET 5 zero during the off period of the FET 3. In other words, it is necessary to do so.

However, vS9t77 is the saturation voltage of BPT77 when a collector current is passed between the gate and source of FET5 to make it zero.

Furthermore, since a reverse voltage is applied between the gate and source of FET 5 when FET 3 is turned on, it is necessary to protect reverse voltage between the gate and source of FET 5.

However, VGS2 (+++ax) is the absolute maximum voltage between the gate and source of FET5.

When resistors R71, R72, and R73 are set under the above limitations, ■ Resistor R? +, R? 2. The loss of R73 is large.

(2) The voltage between the secondary windings of the transformer 2 cannot be set high, and in the control equilibrium state, the gate voltage of the FET 5 becomes low and Ron loss becomes large.

(2) When the FET 5 is turned off, the charge accumulated in the gate is discharged through the resistor 71, so that the discharge time, that is, the turn-off time is delayed, and the switching loss of the FET 5 becomes large.

■ In order to increase the output, a FET 5 with a large current rating is used, increasing the input capacity.

Therefore, the resistance values of the resistors 71, 72, and 73 must be made small, which significantly increases resistance loss and increases the control current, that is, the collector current of the npn-type BPT 77, which increases the drive capacity of the control circuit 7. Due to the increase in the size of the elements used and the increase in loss, it is difficult to increase the output of the switching power supply device.

■ As the frequency increases, the off-period of FET3 becomes shorter, so the resistance value of the resistor 71.72°73 must be reduced, and as a result, as mentioned in (4) above, the loss of the resistor is reduced. It is difficult to increase the frequency due to the increased size of the control circuit 7 and increased loss.

There were many issues such as these, and it was difficult to achieve high efficiency, high frequency, and high output as a switching power supply device.

The present invention solves these problems by controlling the time during which a constant gate voltage is applied between the gate and source of the FET, thereby reducing switching loss, resistance loss, and increasing output of the FET. The present invention provides a switching power supply device equipped with a control circuit that enables high frequency operation.

Means for Solving the Problems In order to solve the above problems, the present invention connects the emitter of a pnp type BPT to the gate and the collector to the source between the gate and source of the second switching element, and connects the emitter of the pnp type BPT to the source.
A parallel circuit of a capacitor and a diode is connected between the base and emitter of the PT, with the anode side connected to the base and the cathode side connected to the emitter, and the base of the pnp type BPT is connected to the npn type BP.
Connected to the collector of T77, the charging time of the capacitor is controlled by the collector current of the npn type BPT77, that is, the application time of the gate-source voltage of the FET is controlled by controlling the on/off time of the pnp type BPT. The structure is such that it is possible to do so.

Effect: This configuration controls the charging current of the capacitor. That is, by controlling the on/off period of the PNP type BPT, the gate voltage application time of the second switching element can be controlled, and the control current can also be reduced, thereby reducing loss in the control circuit. Furthermore, since the drive voltage is applied by turning on and off the pnp type BPT, the voltage set by the secondary bias winding 2c of the transformer 2 can be directly applied when the pnp type BPT is off, so that a sufficient drive voltage can be applied. can be supplied, and the pnp type B
Since the gate accumulated charge is discharged through the emitter of the pnp type BPT when the PT is turned on, it is possible to reduce switching loss, and it is also possible to easily increase the output power and frequency by changing the resistance value of the resistor. This makes it possible to increase efficiency, increase output power, and increase frequency of switching power supply devices.

Embodiment FIG. 1 is a circuit diagram of a switching power supply device according to an embodiment of the present invention. The explanation will be given with reference to FIGS. 1 and 2. In FIG. 1, the same parts as in FIG. 4 are denoted by the same reference numerals. 1 is a DC voltage or DC power source obtained by rectifying a commercial AC voltage, and 2 is a transformer with a primary winding 2a and a primary bias winding 2b.

It is equipped with a secondary winding 2c and a secondary bias winding 2d made by winding around the secondary winding 2C, 3 is a FET which is the first switching element, 3a is a gastric diode of FET 3, and 3b is a gastric diode of FET 3. It shows the channel of FET 3, and its source is connected to the negative side of DC power supply 1, and its drain is connected to one end of the primary winding 2a of transformer 2. Gastric diode 3 of FET 3 as well as storing energy
The energy stored in the transformer 2 is regenerated to the DC power supply 1 via the power supply a. 4 is a resistor 41.42°43, a capacitor 44.45. Zener diode 46.8PT4
This is a synchronous oscillation circuit consisting of 7, which operates the FET 3 in a predetermined on period, and turns off the FET 3 so that the off period of the FET 3 continues until the polarity of the induced voltage in the primary bias winding 2b of the transformer 2 is reversed. Let this turn on
It continues to oscillate by repeatedly turning off. 5 is the second
5a is a gastric diode of FET5, 5b is a channel, and the energy of the transformer 2 stored during the on period of FET3 is transferred to the FET5 through the secondary winding 2c of the transformer 2 during the off period of FET3. After being discharged from the gastric diode 5a to the smoothing capacitor 6, a control circuit 7 controls a backflow period in which the secondary current flows from the smoothing capacitor 6 to the secondary winding 2C of the transformer 2 via the channel 5b of the FET 5. controlled by 7 is a resistor 71.74.81. Error amplifier 75. reference voltage 76,
npn type BPT77, pnp type BPT82, capacitor 83. This is a control circuit for the FET 5 consisting of a diode 84, which detects the output voltage vo and compares it with the reference voltage 76.
When the voltage is higher than the reference voltage 76, the collector current of the npn type BPT 77 is controlled, the pnp type BPT 82 is turned off, and the FE
By turning on T5, the reverse flow period of the secondary current is lengthened,
Conversely, when the voltage is lower than the reference voltage 76, the collector current of the npn type BPT 77 flows, lowering the base potential of the BPT 82 and pn
By turning on the p-type BPT 82 and turning off the FET 5, the reverse flow period of the secondary current is shortened. In this way,
By controlling the time for charging the potential of the capacitor 83, that is, the base potential of the PNP BPT 82, to the threshold voltage by the collector current of the NPN BPT 77, the application time of the gate voltage of the FET 5 can be controlled, and the reverse flow period of the secondary current can be controlled. It is possible to change it.

Also, in FIG. 2, the same parts as in FIG. 5 are denoted by the same symbols. (a) shows the voltage waveform VOS+ across the FET 3, and (b) shows the voltage waveform VOS+ flowing across the primary winding 2a of the transformer 2.
The next current waveform I is shown, and (C) is the synchronous oscillation circuit 4.
(d) shows the drive pulse waveform VGSI of F
It shows the voltage waveform VDS2 across the ET5, and (e) shows the secondary current waveform ID2 flowing through the secondary winding 2C of the transformer 2.
, and (f) is the drive pulse waveform V of FET5.
GS2, and the hatched period during the off period of the FET 3 indicates a reverse flow period during which the secondary current flows through the secondary winding &ll2c of the transformer 2.

First, magnetic flux is generated in the transformer 2 by the primary current 101 flowing through the primary winding 2a of the transformer 2 during the ON period of the FET 3, which operates with the ON period determined by the synchronous oscillation circuit 4, and energy is stored. . At this time, the structure is such that a voltage is applied in a direction that reverse biases the gastric diode 5a of the FET 5, which generates an induced voltage in the secondary windings 2c and 2d of the transformer 2, and between the gate and source of the FET 5. , VGS2=(Vre4+Vcssn)1.4[V
] is applied so that the FET 5 is turned off.

However, VF84 is the forward voltage of diode 84, VCE
Reference numeral 82 denotes a collector-base voltage of the BPT 82, which in this state becomes a forward voltage of the PN junction.

Next, when the FET 3 is turned off by the off signal of the synchronous oscillation circuit 4, a flyback voltage is generated in the primary winding 2a of the transformer 2, and at the same time, a flyback voltage is also generated in the secondary windings 2c and 2d of the transformer 2, and the FET 5 Since a voltage is applied in the direction of forward biasing the gastric diode 5a, the energy stored in the transformer 2 is transferred to the secondary winding 2c of the transformer 2.
is emitted as a secondary current through the smoothing capacitor 6, and is supplied to the output terminal as an output voltage Vo.
FET5 is turned on.

However, C is the input capacitance of FET5, No is the number of turns of the secondary winding 2d of transformer 2, Ns is the number of turns of the secondary winding 2c of transformer 2, and V F 5 a is the gastric diode 5a of FET5. vo is the output voltage C82 is the capacitance of the capacitor 82, R71 is the resistance value of the resistor 71, and VGS2u++ax) is the absolute maximum gate-source voltage of the FET5.

All the energy stored in transformer 2 is released and 2
When the next current becomes zero, the voltage across the smoothing capacitor 6 is
That is, since the output voltage Vo is applied to the secondary winding 2C of the transformer 2, a secondary current flows in the opposite direction from the smoothing capacitor 6, a magnetic flux is generated in the transformer 2 in the opposite direction, and energy is accumulated. be done. In this state, the polarity of the induced voltage generated in each winding of the transformer 2 does not change, so the flyback voltage of the primary bias winding 12b of the transformer 2 also does not change, and the synchronous oscillation circuit 4 maintains the off period of the FET 3.

The control circuit 7 controls the voltage between the gate and source of the FET 5, that is, the on-period, and when the FET 5 is turned off, the polarity of the induced voltage generated in each winding of the transformer 2 is reversed. The induced voltage generated in FET 5 reverse biases the gastric diode 5a, and
Since ET5 is also off, the secondary winding current no longer flows, and the induced voltage generated in the primary winding 2a of the transformer 2 is
The primary current 10 is generated in the direction of charging the DC power supply 1 through the gastric diode 3a of the FET 3 because it generates a negative voltage at the connection end with the FET 3 and a positive voltage at the connection end with the DC power supply 1.
1 flows and the energy of the transformer 2 accumulated during the off period is regenerated to the DC power supply 1. At this time, transformer 2
Since the polarity of the induced voltage generated in the primary bias winding 2b is also reversed, the synchronous oscillation circuit 4 turns on the FET 3. When all the energy stored in transformer 2 during the off period is released and the primary current becomes zero, the FE is already turned on.
A primary current in the opposite direction to that described above flows from the DC power source 1 via T3, generating magnetic flux in the transformer 2 and storing energy. In this state, the polarity of the induced voltage generated in each winding of the transformer 2 does not change, and the synchronous oscillation circuit 4
remains on. When the FET 3, which operates during the on period determined by the synchronous oscillation circuit 4, is turned off, the energy stored in the transformer 2 is released as a secondary current through the secondary winding 2c of the transformer 2.

By repeating these operations, the output voltage Vo is supplied to the output terminal.

Furthermore, the operation for stably controlling the output voltage Vo will be explained in detail. Each operating waveform is shown in FIG. 2, and the off period (t
, ~t3) is set as T OFF, and two current currents ID
The backflow period (t2 to t3) of 2 is set as T'OFF, while the on period of the drive pulse waveform VGS+ of the synchronous oscillation circuit 4 (
t3 to t5) is TON, and the regeneration period of the primary current I is TδN, and the output voltage VO is expressed as .

However, Ls is the inductance value of the secondary winding 2C of the transformer 2, NS is the number of turns of the secondary winding 2C of the transformer 2, Np is the number of turns of the primary winding 2a of the transformer 2, and T is the oscillation period. At T = TON + TOFF, VIN
is the voltage of DC power supply 1,

That is, since the on period TON is kept at a constant value determined by the synchronous oscillation circuit 4, if the output voltage Vo is constant, the off period T OFF is also constant, and the oscillation period T is also constant. The period T'OFF can be changed by the FET 5 controlled by the control circuit 7, and when the output current 10 changes, if the output voltage ~'0 is constant, the backflow period T
It can be controlled by changing 'OFF'. Furthermore, changes in the voltage of the DC power supply 1 can be controlled by changing the backflow period T'OFF.

In Figure 2, the dotted line indicates no load when the output current 1o is zero, indicates the maximum load when the reverse current is at its maximum, and indicates T'0 when the reverse current is zero.
FF=O.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In FIG. 3, the same parts as in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, 85 is an npn type BP
T, which eliminates the secondary bias winding 2d of the transformer 2, and the secondary winding 2c of the transformer 2 is also the bias winding of the FET 5 of the second switching element. 9 is a resistance of 71°74.81. Error amplifier 75. reference voltage 76,
npn type BPT77.85. Capacitor 83. This is a control circuit for FET5 consisting of a diode 84, and the output voltage v
o is detected and compared with the reference voltage 76. If it is lower than the reference voltage, the collector current is passed through the npn type BPT 77 and the np
Raise the base potential of n-type BPT85 and npn-type BPT85
By turning on the FET5 and turning off the FET5, the reverse flow period of the secondary current is shortened, and conversely, when the voltage is higher than the reference voltage 76, the np
By limiting the current of the n-type BPT 77, turning off the npn-type BPT 85, and turning on the FET 5, the reverse flow period of the secondary current is lengthened. In this way, by controlling the time I11 to charge the potential of the capacitor 83, that is, the base potential of the npn type BPT 85, to the threshold voltage by the collector current of the npn type BPT 77, the applied voltage of the gate voltage of the FET 5 can be controlled, and the voltage applied to the gate voltage of the FET 5 can be controlled. It is possible to vary the current backflow period.

Since the operation is the same as that in FIG. 1, the explanation will be omitted.

Effects of the Invention As described above, according to the present invention, by controlling the charging current of the capacitor, the on/off period of the FET drive BPT, which is the second switching element, is controlled, and the reverse flow period of the secondary current is controlled. Since it is controllable, loss in the control circuit can be improved, and a voltage sufficient to drive the maximum reverse current can be directly applied from the secondary bias winding of the transformer when the drive BPT is turned off, and when the drive BPT is turned on. Can be discharged through the drive BPT at times,
Switching loss of the second switching element can be reduced. Furthermore, when a reverse voltage is applied to the second switching element, since the collector and base of the drive BPT are forward biased as a pn junction, this forward voltage and the base-emitter of the drive BPT The forward voltage of the diode connected between the FET and the gate and source of the FET, which is the second switching element, is also protected at this value.

Also, for higher output and higher frequency, the capacitance of the capacitor and the resistance value of the resistor connected in series between the gate of the FET, which is the second switching element, and the secondary bias winding of the transformer 2, The rise time of the gate can be easily set, and effects such as higher output and higher frequency can be easily achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of the switching power supply device of the present invention, FIG. 2 is an operation waveform diagram showing operating waveforms of each part in the circuit configuration of FIG. 1, and FIG. FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 4 is a circuit configuration diagram of a currently proposed switching power supply device, and FIG. 5 is an operation waveform diagram showing operating waveforms of each part in the circuit configuration of FIG. 4. 1...DC power supply, 2...Transformer, 2
a...Primary winding, 2b...Primary bias winding, 2c...Secondary winding, 2d...
Secondary bias winding, 3...FET, 3a...
...Gastric diode, 3b...FET3 channel, 4...Synchronized oscillation circuit, 5...
・FET, 5a... Gastric diode of FET5, 5b... Channel of FET5, 6...
... Smoothing capacitor, 7.9 ... Control circuit, 4
1,42.43.71,72゜73.74...
Resistor, 44.45.83...Capacitor, 46
...Zener diode, 47. '77°85
--- n p n type BPT, 82- p n p type B
PT, 75...Error amplifier, 76...
Reference voltage, 84...Diode, VDSI...
... Train-source voltage of FET3, Vas de... Gate-source voltage of FET3, IDI...
... Current in the primary winding 2a of the transformer, ``v' o
s:...Drain-source voltage of FET5, Vas=...Gate-source voltage of FET5, +02...Current of secondary winding 2c of transformer 2, Vo: Output voltage, ro: Output current.

Claims (1)

[Claims] The first switching element is turned on and off, and when the first switching element is on, the input voltage is applied to the primary winding of the transformer to flow the primary current, energy is stored in the transformer, and the first switching element is turned on. When the transformer is off, the energy stored in the transformer is released as a secondary current from the secondary winding of the transformer, and this secondary current is rectified and smoothed by a rectifying means and a smoothing means to obtain an output voltage. A second switching device connected in parallel to the rectifying means whose on/off period is controlled by controlling the charging current of the capacitor and the time constant of the resistor and capacitor after all the energy is released from the secondary winding of the transformer. The output voltage is applied to the secondary winding of the transformer via the element, and the output voltage is controlled by changing the period during which the output voltage is applied to the secondary winding of the transformer by the second switch means. Configured switching power supply.