JPH03228428A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction cased by a noise by constituting this output circuit so that the switching timings of output levels of plural output buffers are not overlapped logically. CONSTITUTION:The output circuit is provided with coincidence detecting circuit 211 for inputting the input signal 202 of a latch circuit 206 and the output signal of output buffer circuits 208, 209, and the AND circuit 212 of a signal from the coincidence detecting circuit 211 and the clock signal 204 of the latch circuit 206, and the AND circuit output 205 of an n-th buffer block in a buffer block 201 becomes the clock signal 204 of the latch circuit 206 of an n+1-th buffer block. In such a manner, in the output circuit provided with plural buffer blocks, it is prevented that operation timings of each output buffer circuit become the same, and the generation of a malfunction can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an output buffer circuit using complementary MO8) transistors (hereinafter referred to as CMO3Tr).

[Conventional technology]

A conventional output circuit of this type is shown in FIGS. 7 and 8.

This will be explained with reference to FIG.

First, in FIG. 7, a conventional output buffer circuit diagram shows a first buffer block 11. Second buffer block 2
1. Third buffer block 31, fourth buffer block 41, and first to fourth buffer blocks 711.
... 741 data input terminals 712, 722, 73
2,742 and the output terminal 713 of the buffer block.
, 723° 733, 743, latch signal input terminals 714, 724, 734, 744 of the buffer block, and a latch signal line 750.

FIG. 8 is a circuit diagram of each buffer block in FIG. 7.

In FIG. 8, a buffer block 801 includes a data input terminal 802, a buffer output terminal 803, a latch signal input terminal 804, a latch 805, an inverter 806 to which a latch output signal 809 is input, and a P-channel M
O8) transistor (hereinafter referred to as PMO8Tr) 807 and N-channel MO8) transistor (hereinafter referred to as NMOSTr)
) 808.

FIG. 9 is a timing diagram of each part of FIG. 7.

In FIGS. 7, 8, and 9, when the latch signal input terminal 804 is "1", the latch 805 outputs the level of the data input terminal 802 as it is as the latch output signal 809.

When the latch signal input terminal 804 is "0", the level before it becomes "0" is held in the latch 805, and the latch output signal 809 is output. Latch output signal 809 is “0”
When , the inverter 806 outputs 1", and NMO3Tr
808 is made conductive, and the buffer output terminal 803 is set to “0”.
”.When the latch output signal 809 is “1”, the inverter 806 outputs “0” and the PMO8Tr808
is made conductive and outputs “1” to the buffer output terminal 803.

Next, the operation of the output buffer circuit using the buffer block 801 described above will be explained. first buffer block 7
The latch signal input terminal 714 of the 11th buffer block, the latch signal input terminal 724 of the second buffer block 721, the latch signal input terminal 734 of the third buffer block, and the latch signal input terminal 744 of the fourth buffer block are latch signals. It is connected to a signal line 750. In FIG. 9, data input to the data input terminal 712, data input terminal 722, data input terminal 732, and data input terminal 742 is determined at a first timing b1, and is latched at a second timing b2. The level of the signal line 750 starts to change from '0' to '1'. Then, during the third to fourth timings b3 to b4, the buffer output terminal 713, the buffer output terminal 723, and the buffer output terminal 733 and,
The level of the buffer output terminal 743 changes and is determined at the fourth timing b4.

[Problem to be solved by the invention]

In the conventional output buffer circuit described above, when a large capacitive or inductive load is applied to the buffer output terminal, electromagnetic inductive noise is generated due to the large charging/discharging current during level switching, but the timing is Since the bits are the same, the noise level becomes particularly high, which has the drawback of causing malfunctions in other circuits on the same board and in external circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit which solves the above-mentioned drawbacks, prevents the operation timings of each output buffer circuit from being the same, and suppresses the occurrence of malfunctions.

[Means to solve the problem]

The configuration of the present invention is an output circuit including a plurality of buffer blocks each having an output latch circuit and an output buffer circuit for storing output data, in which an input signal of the latch circuit and an output signal of the output buffer circuit are input. a coincidence detection circuit; and an AND circuit of a signal from the coincidence detection circuit and a clock signal of the latch circuit; It is characterized in that it is a clock signal of the latch circuit of the block.

〔Example〕

Next, the present invention will be explained with reference to the drawings. 1st
The figure is a circuit diagram showing the output circuit of the first embodiment of the present invention.

In FIG. 1, the output circuit of the first embodiment of the present invention is as follows:
The first buffer block 111, the second buffer block 121, the third buffer block 131, and the fourth
the buffer block 141 of the first buffer block 111, the data input terminal 112 of the first buffer block 111, the second data input terminal 122, the third data input terminal 131, the fourth data input terminal 142, and the first buffer Output terminal 113
and a second buffer output terminal 123, a third buffer output terminal 133, a fourth buffer output terminal 143, and a latch signal input terminal 114 of the first buffer block.
The second latch signal input terminal 124, the third latch signal input terminal 134, the fourth latch signal input terminal 144, and the latch signal output terminal 115 of the first buffer block.
, a second latch signal output terminal 125 , a third latch signal output terminal 135 , and a fourth latch signal output terminal 14
5. FIG. 2 is a circuit diagram of each buffer block shown in FIG. 1. In FIG. 2, the buffer block 201 includes a data input terminal 202, a buffer output terminal 203, a latch signal input terminal 204, a latch signal output terminal 205, a latch 206, and a latch output terminal 203.
Inverter 207 to which 10 is input and PMO8Tr2
08, NMO3Tr209, and EX-N.

It includes an R gate 211 and an AND gate 212.

FIG. 3 is a timing diagram of each part of FIG. 2.

FIG. 4 is a timing diagram of each part of FIG. 1.

Next, the operation will be explained with reference to FIGS. 3 and 4.

Latch 206. Inverter 207. PMO8Tr208
, NMO8Tr 209 are the same as those of the conventional example shown in FIG. 8, and will therefore be omitted. During the period (T0 to T3) from timing T0 when the data at the data input terminal 202 begins to change to timing T3 when the level change at the buffer output terminal 203 ends (T0 to T3), the EX-NOR gate 21
The output of 1 becomes "0". The EX-NOR gate 21
A that inputs the output of 1 and the latch signal input terminal 204.
Latch signal output terminal 20 which is the output of ND gate 212
5, the level of the latch signal input terminal 204 is "1",
It becomes "1" when the level of the buffer output terminal 203 is not changing.

The aforementioned buffer block is connected to the latch signal output terminal 115 of the first buffer block 111 as shown in FIG.
The second latch signal input terminal 124 is connected to the second latch signal input terminal 124, the latch signal output terminal 125 is connected to the latch signal input terminal 134, and the latch signal output terminal 135 is connected to the latch signal input terminal 144.

Here, the first to fourth data input terminals 112°122.
132 and 142 change, and the latch input terminal 11
When the level "1" is input to the buffer block 111, the buffer block 121 is inputted to the buffer block 121 after the timing a1 at which the level of the buffer output terminal 113 changes.
In contrast, the level of the latch signal output terminal 115 is set to "1".

Next, the buffer block 121 similarly sets the latch signal output terminal 1250 level to "1" with respect to the buffer block 131 after timing a2 at which the level of the buffer output terminal 123 changes has passed. In this way, the timing al+a2 . at which the level of the buffer output terminal of each buffer block changes. a3+ am never overlaps. In addition, in this example,
(bit) output buffer, but it can be easily expanded to a larger number of bits.

FIG. 5 is a circuit diagram showing an output circuit of a second embodiment of the present invention. In FIG. 5, the output circuit of this embodiment has the first
to fourth buffer block 511゜521.531.
541 and first to fourth data input terminals 512, 52
2,532,542, the first to fourth latch signal input terminals 514,524゜534.544, and the first to fourth latch signal input terminals 514,524゜534.544,
latch signal output terminals 515, 525, 535, 545
and the first to fourth high impedances (Hi-Z)
Control terminals 516, 526, 536, 546 and Hi
-2 control edge 550.

FIG. 6 is a circuit diagram showing each buffer block of FIG. 5. In FIG. 6, a buffer block 601 includes a data input terminal 602, a buffer output terminal 603, a latch signal input terminal 604, a latch signal output terminal 605, a Hi-Z control terminal 606, and a latch that outputs an output 613. 607, inverter 608, and PMO8Tr60
9, NMO8Tr 610, and NAND gate all
, NOR gate 612 , and EX-NOR gate 614
, an OR gate 615, and an AND gate 616.

Next, the operation will be explained using FIGS. 5 and 6.

In FIG. 6, when the level of the Hi-Z control terminal 606 is "1", it is equivalent to FIG. 2 and operates in the same way. Hi
When the level of the −Z control terminal 606 is “0”, the buffer output terminal 6
03 is fixed in the Hi-Z state, and the latch signal output terminal 6
05, the level of the latch signal input terminal 604 is output as is. In this way, the present invention can also be applied to an output buffer circuit having an input terminal for a control signal that controls whether or not to set the output to Hi-Z. In this example, by adding an output to the output buffer block that indicates that the buffer output is not changing, and inputting that output to the latch input of the other output buffer blocks, the change timing of the output level of each output buffer can be overlapped. Logically control things so that they don't match.

〔Effect of the invention〕

As explained above, in order to prevent the switching timings of the output levels of a plurality of output buffers from logically overlapping, the present invention eliminates electromagnetic inductive noise caused by charging/discharging current of the load of the data output terminal at the time of data switching. This has the effect of preventing malfunctions caused by this type of noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an output buffer according to the first embodiment of the present invention, FIG. 2 is a circuit diagram of a buffer block according to the first embodiment of the present invention, and FIG. 3 is a circuit diagram of each part of the circuit of FIG. 2. timing diagram,
4 is a timing diagram of each part of the circuit of FIG. 1, FIG. 5 is a circuit diagram of the output buffer of the second embodiment of the present invention, and FIG. 6 is a diagram of the buffer block of the second embodiment of the present invention. circuit diagram,
FIG. 7 is a circuit diagram of a conventional output buffer, FIG. 8 is a circuit diagram of a conventional buffer block, and FIG. 9 is a timing diagram of each part of FIG. 111.121,131,141,201゜511.5
21,531,541,601,711゜721.73
1,741,801...Buffer block, 1
12,122,132,142,202゜512.52
2,532,542,602,712°722.732
, 742, 802... Data input terminal, 113
,123,133,143,203゜513.523,
533,543,603,713゜723.733,7
43,803...Buffer output terminal, 114,
124,134,144,204゜514.524,5
34,544,604°714.724,734,74
4,804...Latch signal input terminal, 115,
125,135°145.205,515,525,5
35,545°605...Latch signal output terminal, 206,607°805...Latch, 207
,608,806...Inverter, 208,6
09,807...P channel MO8Tr,
209. 610. 808=--N channel MO8
Tr, 210,613°809...Latch output, 211,614...EX-NOR gate, 2
12,616...AND gate, 516,5
26,536,546,606...Hi-Z
Control terminal, 550...Hi-Z control signal, 6
11...NAND gate, 612...
N. R gate, 5...OR gate, 0...Latch signal line.

Claims (2)

[Claims] (1) In an output circuit including a plurality of buffer blocks each having an output latch circuit for storing output data and an output buffer circuit, a coincidence detection circuit receives as input an input signal of the latch circuit and an output signal of the output buffer circuit. and,
an AND circuit of a signal from the coincidence detection circuit and a clock signal of the latch circuit; An output circuit characterized in that the clock signal is a clock signal of (2) The buffer block includes a control circuit that sets the output signal terminal of the output buffer circuit to high impedance, and a control circuit that disables the coincidence detection circuit by the output of the control circuit. output circuit.