JPH03228421A - Digital filter - Google Patents

Abstract

PURPOSE:To realize this efficient FIR(finte impulse response) type digital filter whose capacity is small and whose occupancy area is small by providing plural input data storage parts, and a storage means for holding so as to compensate a phase difference between respective input data inputted to respective input data storage parts. CONSTITUTION:The digital filter is provided with the plural input data storage parts 40, 41 for executing alternately the setting and the outputting of input data, an arithmetic part 46 for executing the digital filter operation of the input data, and selective means 44, 45 for taking out cyclically the input data from each of plural input data storage parts 40, 41 and supplying it to the arithmetic part 46. Also, the filter is provided with a storage means 43 for holding the input data inputted to at least one of input data storage parts 40, 41 by the time corresponding to a phase difference so as to compensate the phase difference between respective input data inputted to respective input data storage part 40, 41. In such a manner, the efficient FIR type digital filter with a small area can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to the fields of audio, communication, measurement, etc.
This paper relates to digital filters used in digital signal processing, which are becoming popular in recent years.

[Conventional technology]

Filter configurations used in digital filtering processing include an FIR type with a finite impulse response and an infinite IIR type (infinite impulse response). Of the two, the FIR type filter has a larger filter order (number of taps) than the IIR type, but has no group delay distortion.
Since it has the advantage of not causing limit cycle oscillation, it has been developed especially for use in the audio field as LSIs have become smaller in recent years. This FIR type filter also has a decimation filter to lower the sampling frequency to y:1, and an interpolation filter to raise the sampling frequency to 1:y.The former is a high-speed A/D converter. (a device that converts analog signals into digital signals), the latter is a high-speed D/A converter (
(a device that converts digital signals into analog signals).

The ΔΣ (delta-sigma) modulation method, which is one of the over-sampling noise shaving methods that has attracted attention in recent years as an A/D conversion method, converts analog signals into high-speed (for example, 3072KHz = 64X 48KH2)
) into a 1-bit PDM (pulse density modulation) signal, and shifts the quantization noise to a frequency band higher than the pass band. The quantization noise that has been shifted to a high frequency in this way can be removed by a digital decimation filter in the subsequent stage and converted into, for example, a 16-bit 48KHz PCM (pulse code modulation) signal. However, such digital decimation
An important issue is how to realize filters efficiently and economically.

The process performed by the above-mentioned FIR type digital decimation filter is to calculate a filter coefficient w having desired filter characteristics for an input digital signal a.

By multiplying and accumulating , a digital signal J = ΣW, ·a-, (rl is the number of taps of the filter) is obtained as an output, and in the case of a decimation ratio y:l, the input data rate fl The signal al is decimated to a signal bJ with an output data rate f,=(1/y)·f. At this time, the filter coefficient W is selected so that aliasing noise does not enter the signal band due to the decimation effect.

FIG. 5 shows an outline of the configuration of an actual digital filter.

In FIG. 5, the input digital signal al is stored in the input data storage section 1 for the required number of taps, and is sequentially sent to the multiplication accumulator 3 together with the coefficient data w from the coefficient data storage section 2. , through several taps of multiplication and accumulation, output data b is obtained, and output data f is determined by the output register 7.
is output at a data rate of . 4 is a control means for each of the above-mentioned components l, 2°3.7.

Among the above, the main function of the manual data storage section l is to change the decimation ratio to y:1. The number of filter taps is n
Then, past n pieces of data a (however, 1=-1 to -
n) and sequentially send them at appropriate timings to the arithmetic device together with the corresponding filter coefficients W, and y new data a, for the next arithmetic operation.
Take in (i=0~(y-1)), a −6* y −
Discard the y oldest data from 1 to a-0 and use a, -1 to a O+ a -1 to a - as data for the next calculation.
0*y is newly prepared.

To realize the above functions, shift registers, RA
M (Random Access Memory) or the like may be used. Particularly in digital filters, shift registers are often used due to real-time requirements and fixed arithmetic processing procedures. In other words, it takes advantage of the feature of shift registers, which allows data to be shifted in while shifting data out. n-word shift using means lO
While outputting the data of a-+ to a-0 from the last word in the register 9, it is fed back to the first word through the selection means 10, and then the selection means 10 is switched to the new data input side, and the data is inputted. While inputting new y-word data from data register 8, by shift operation,
By discarding the oldest y data of a-5*y-+ to a-n, it is possible to shift a-+ to a-n + y by y words. 11 is a multiplication accumulator, 12
is a coefficient data storage means (operation is similar to those shown in FIG. 5).

On the other hand, the FIR type filter is characterized by the left-right symmetry of the filter coefficient W (W r = W ng W z ”
W yl -r 4...), and there is a method that uses this property to halve the number of multiplications and accumulations. That is, as shown in FIG. 7, 14 and 15 are n/2 word shift registers, and the first word of one register 14 receives data from the input data register 13 or the same register 14 through the selection means 16. Input the data output from the last word of . The other register 15 is shiftable in both directions, and during operation, data is fed back from the last word to the first word in the same shift direction as the one register 14, and when data is updated, it is shifted in the opposite shift direction. Data from the last word of one register 14 is input and unnecessary oldest data is discarded. 17 is a pre-stage adder which adds the output data from the final word of one register 14 and the output data from the final word of the part in the same shift direction of the other register 15; input to the input end of 1
8 is a coefficient data storage means, and 19 is a multiplication accumulator.

According to such a configuration, the data of a-+ to a-fi are
In the 17 pre-stage adders, each symmetrical component is first added (
a−++a−n, a−a”a−n*++ . . This method is called the front-stage addition type.The front-stage addition type can reduce the number of multiplications and accumulations by half, but it is necessary to add chronologically symmetric data first. Therefore, it becomes necessary to use a so-called reversible shift register that can shift in both directions as the shift register 15 corresponding to the latter half (n/2+1 to n-th word). Due to the addition of transistors, etc., the area and circuit size of a resistor cell with a multi-channel resistor is approximately twice that of a conventional unidirectional resistor cell, making it uneconomical to realize a filter with a large number of taps. Ta.

[Problem to be Solved by the Invention J The above-mentioned two digital filters that use shift registers as data storage means both have advantages and disadvantages. In other words, the former method that does not use pre-addition uses shift and
Although the control of the register section is simple and requires a small area, in a filter in which the number of multiplications and accumulations is large and the number of taps n is large, a multiplication and accumulation speed twice as high as that of the latter is required. Furthermore, although the latter may require half the multiplication and accumulation speed of the former, the area of the shift register section becomes approximately 1.5 times as large.

Furthermore, in the above-mentioned digital filter, the arithmetic section has a rest period in addition to the calculation period, and the operation is not necessarily efficient.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an efficient digital filter with a small area.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a plurality of input data storage units that alternately set and output input data;
an arithmetic unit that performs a digital filter operation on input data;
selection means for cyclically extracting input data from each of the plurality of input data storage units and supplying the input data to the calculation unit; and compensation for a phase difference between each input data input to each of the input data storage units. and storage means for holding input data input to at least one of the input data storage units for a time corresponding to the phase difference.

[Function 1] According to the present invention, with the above configuration, it is possible to provide an efficient FIR type digital filter with a small capacity and a small occupied area.

〔Example〕

As a first embodiment of the present invention, the number of taps n is n=12.
8. Decimation ratio is 4 (y:n=4:l),
One word consists of 16-bit PCM data.
A case where the present invention is applied to an FIR type digital decimation filter will be explained using the configuration diagram in FIG. 1 and the clock timing diagram in FIG. 2.

In FIG. 1, data a is input to the digital decimation filter at a data rate f.
, are always taken into the 20 4-word shift registers at a data rate of f by a control clock called CKI generated by the 36 control section. That is, during one calculation period, T, = 1/f, C
Data aO to a3 are sequentially shifted into the shift register 20 by four clocks of KI and stored in the fourth to first words, respectively.

At the beginning of this period, a-+ to a-128 that have been captured in the past as a result of the repeated operation up to the previous time.
128 words of past data are stored in 21 A shift registers and 23 B shift registers with 64 words each, and in A shift register 21, the 1st to 64th words along the shift direction are stored. The past data from a-+ to a-64 is stored in order in each position, and in the B shift register 23, the past data from a-1111 to a-6, past data is stored in order. At this point, the chronological order of the stored data in the B shift register 23 is opposite to the shift direction because it has already been used in the previous time using the C shift register 22 and the parallel transfer means 27. This was obtained from the past operation of , and is similar to the operation of the current cycle shown below, and can be easily understood from this explanation of the operation. The C shift register 22 is
It has only a one-way shift function and has a capacity of y words, that is, 4 words, according to the decimation ratio of the filter, and shifts and data is taken in by the clock of either CR2 or GK3'.

Figure 2 shows each clock CK in this one calculation cycle.
The timings of I to CK6 and CK3' are shown, and the operation of each shift register is determined by the rising edge (Ris) of each clock.
ing) indicates input to the master side (that is, data capture), and falling indicates transfer to the slave side (that is, data output). In the first period, A
and B shift registers 21 and 23 perform 64 shift operations, and from data lines 28 and 29, respectively, 3
In addition to sending data to the pre-stage adder of 2, 24 and 25
The output data is sequentially fed back through the self-loop data line. At this time, the 32 pre-stage adders are (a-S4+a-asL(a-ss+a-as)+"
'+(a-r+a-Iza)' is added 64 times, and data is sent one after another to 33 multipliers. 33
The multiplier and 34 accumulators multiply and accumulate the 64 pre-added data and the filter coefficients Vls4 to W1 from the coefficient data storage unit 31 64 times, and b,=
Σ: (a-++a+-+ze-t+)・wl result b
, and sends it to the output register 35.

If CR3 is used as the clock for C register 22, C register 22 will be clocked via 30 data lines by the first four clock pulses of the first period.
First four location data a-a4 from A register 21
+a-ss+a-s□+a-81 are taken in order, and finally, a-64~g, 1
It stops in the state where each is memorized.

In the next second period, the A register 21 shifts the data by 4 words by CR2, and the B register 23 shifts the data by 4 words by CR2.
Shift by 64-4=60 words by R4.

Due to these shift operations, in the A register 21, a
-+~a-s. data is shifted to the 5th to 64th word positions, and in the B register 23, the data from a-+z4 to a-as is shifted to the 1st to 60th word positions via 25 self-loop data lines. Shift to position, a-
The data from Iza to a-+z5 is shifted to the 61st to 64th word positions. When CK3' is used as the clock for the C register, the first four clocks of this second period send the four data a-64 to a-6,
It is possible to import it into the C register 22 in the same way as in the case described above using CR2.

After the above operations are completed, until the next calculation starts, C
4 data a-84 to a-s in register 22
r is transferred by CR6 via 27 parallel transfer means,
It is sent to the 61st to 64th words of the B register 23,
Rewrite the data of a-+□8 to a-+*4. That is,
The fourth .C register 22. Third. Second. From each first word, respectively, the 61st . No. 62. Rewrite transfer is performed to each of the 63rd and 64th word positions so that the subsequent data shift direction is reversed. Next, immediately before the end of this second period, the period in which CKI becomes Low, that is, 2
4 new data a3 to a0 in shift register 0
is stored in the slave side of the first to fourth words, the 26 parallel transfer means transfer the data of a3 to a0 to the first to fourth word positions of the A register 21 by the clock of CR5. and rewrite the data.

By the above series of one calculation cycle operation, a, ~a-+□8
As a new data set for the next operation, as~ao, a-+ ``a-s'' are placed in the 1st to 64th word positions of the A register 21.

The data of a-+z4 to a-6 can be re-stored in the first to sixty-fourth word positions of the B register 23, and data preparation for the next cycle is completed.

By repeating the above operations one after another, a digital filter using the front-stage addition method and having a small number of multiplications and accumulations can be realized.

In the above embodiment, the data unit of one word is 16 bits as an example, but this is the same no matter how many bits there are, and basically it can be applied to all cases where the data unit is 1 bit or more.

FIG. 3 shows an example of a two-channel digital filter used in the audio field as a second embodiment.

Reference numerals 40 and 41 designate data storage units having the same configuration as each of the constituent elements 20 to 27 in the embodiment shown in FIGS. 1 and 2, and each is used for each of the Left and Right channels. 42 control section CKIL-CK6L (
CKI to CK6), and CKIR-CK6R (CKI-C
K6), but the calculation period of the Right channel is 180 times the calculation period of the Left channel.
The control state is controlled by the fourth phase.
As shown in the figure (detailed explanation will be given later).

In FIG. 3, the data lines 51.52 and 53.54 of the data stores 4o and 41 are similar to the data lines 28.29 of the embodiment described above. 44 and 45 are
Clock C from the control section 42 is a selection means.
When K7 is High, the left side data output line 5
1 and 52 are connected to the data input lines for the arithmetic unit (46) of 55 and 56, and when the line is low, the data lines 53 and 54 on the right side are connected to the data input line 55 and 56.

The arithmetic unit 46 is the pre-stage adder 3 of the above embodiment (FIG. 1).
2, multiplier 33, and accumulator 34, and for the data coming from data input lines 55 and 56, the following 1) j, L,
"Σ (a-i, L"al-129411,L)
・W, bJ, ll” Σ (a-i, ll”a
l-1294+1. II) ” Perform the calculation wi and output b,, L+ bj, !1 alternately.

In the above-described embodiment with only one channel, the arithmetic unit performed 64 additions, multiplications, and accumulations in the first period, and paused in the second period, but the arithmetic unit 46 shown in FIG. b...
In the first period of the L calculation period, the calculation of the Left channel is performed, and in the second period of the L calculation period (that is, it is also the first period of b,,R), Rig
Perform calculations on the ht channel. Therefore, the calculation unit 46 can perform calculations on both channels without taking a pause period (and by sharing time efficiently alternately. In FIG. 3, the input data line 4 on the Right channel side
9. The 43 shift registers put in 50 are y/2=
It consists of 2 (y:4) words and is used to correct the phase difference between both channels. That is, as seen from FIG. 4, the calculation timing on the Right side is delayed by hT (180 degrees) compared to the Left side, so that the data a+, * used in the calculation is transferred using the shift register 43. If not, there will be a time difference of y/2:2 words compared to al and L. This time difference is exactly
It looks like a 180 degree phase shift for CK7, which is particularly undesirable for audio applications. Therefore, shift register 4
3, the data input to the data storage unit 41 on the Right side is delayed by y/2=2 words, and data ai, L, al, and II for the actual calculation by the calculation unit 46 are simultaneously sampled. By processing it as data, it is adjusted so that the output bJ, L, and 4.3 become simultaneous sampling data.

Note that similar effects can be obtained in the case of three or more channels. For example, in the case of 3 channels, y/3 words, 2
A y/3 word shift register may be used.

〔Effect of the invention〕

According to the present invention, the FI is small in area and efficient, and in particular can process data of multiple channels in the same phase.
An R-type digital filter can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to realize a digital filter using a single multiplier-accumulator, and FIG. 2 is a block diagram showing each embodiment applied to the embodiment shown in FIG. A diagram showing an example of the timing of a control clock signal. FIG. 3 shows an embodiment in which the present invention is used to realize a two-channel digital filter using a single multiplication and accumulation method using time sharing. Block Diagram. FIG. 4 is a timing diagram of the same embodiment, FIG. 5 is a block diagram showing the configuration of an actual digital decimation filter, and FIGS. 6 and 7 are diagrams showing the configuration of a digital filter according to the prior art. Fig. 6 is a block diagram when performing n-fJ multiplications and accumulations without using pre-stage addition, and Fig. 7 is a block diagram in which pre-stage addition is performed using an n/2 word reversible shift register, and It is a block diagram in the case where /2·f4 times of multiplication and accumulation are sufficient. 1.40.41... input data storage section, 2, 12.
18.31.47... Coefficient data storage unit, 4.36.
42... Control unit, 3.11.19... Multiplier and accumulator, 5.33... Multiplier, 6.34... Accumulator, 17.32... Pre-stage adder, 7 .35...Output register, 8.13.20...Y word or y pit data register, 9...N word shift register, 10.16.44.45...Selection means, 14...・n
/2-word unidirectional shift register, input 15... n/2-word reversible shift register, 21.
...A shift register, 23...B shift register, 22...Y word direction change shift register, 26...Parallel rewrite transfer means 27...Direction change parallel rewrite transfer means, 24, 25 ．．
28.29.30.37.3g, 39.48~59・
...Data line, GKI~CK7. CKIL~CK6L, CKIR~C
K6R...Control signal, 43...Shift register for inter-channel phase adjustment. Figure 2 Figure K7 Figure 84

Claims (1)

[Scope of Claims] 1) A plurality of input data storage units that alternately set and output input data, an arithmetic unit that performs a digital filter operation on the input data, and a cyclic output from each of the plurality of input data storage units. selecting means for extracting input data and supplying it to the arithmetic unit; and input data to at least one of the input data storage units so as to compensate for a phase difference between each input data input to each of the input data storage units. A digital filter comprising: storage means for holding input data for a period of time corresponding to the phase difference.