JP3095395B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital signal train obtained by sampling an analog signal at regular intervals in a field such as audio, communication, and measurement. The present invention relates to a digital filter that performs a filtering process.

[Prior Art] Filter configurations in digital filtering processing include a FIR (finite impulse response) type in which the impulse response is finite and an IIR (infinite impulse response) type infinite. Among them, the FIR filter is IIR
Although the filter order (the number of taps) is larger than that of the type, it has the advantages of no group delay distortion and no limit cycle oscillation, so it has been developed especially for audio applications with the recent miniaturization of LSIs. Have been doing.

This FIR filter also has a sampling frequency of y: 1
Decimation filter to reduce
There is an interpolation filter to increase the value of y, and the former has a high-speed A / D converter (a device that converts analog signals into digital signals) and the latter has a high-speed D /
It is used with an A-converter (a device that converts digital signals into analog signals).

As shown in FIG. 11, the processing performed by these FIR digital filters is performed by multiplying and accumulating the input digital signal a _i by a filter coefficient w _i having desired filter characteristics as an output. Digital signal It is to get. In FIG. 11, the input digital signal a _i is stored in one input data storage unit for the required number of taps, and the coefficient data w _i from the second coefficient data storage unit is stored.
Are sequentially sent to a power-of-three accumulator, and after multiplication and accumulation of several taps, output data b _j is obtained. The output data b _j is output from an output register 7 at a data rate of f _j . Reference numeral 4 denotes control means for the above components 1, 2, 3, and 7.

In the decimation type, in order to prevent aliasing noise from entering the band, and in the interpolation type, to eliminate aliasing components around a position n times the sampling frequency of the original digital data. , but performs a digital filtering, characteristic itself of the filter in any case, y and the number of taps n of the determined by the word length l of the coefficient data w _i. That is, as both n / y and l are larger, better filter characteristics are obtained.

However, the number of times of multiplication / accumulation in one operation cycle for _obtaining one b _j increases in proportion to n, and l
Is larger, the circuit scale of the multiplier-accumulator becomes larger and the multiplier-accumulation speed becomes slower. Therefore, it becomes more difficult to realize a good filter characteristic with a filter having a larger y. Also, from a practical point of view, the 18-bit × 18-bit multiplier required for audio has an operating upper limit speed of about 12 MHz, and its circuit size is about 10 times as large as a 20-bit accumulator. Therefore, when designing an ordinary digital filter, there has been a problem how to efficiently use this single multiplier to extract the maximum filter characteristics.

Meanwhile, as a method of a conventional A / D converter, an input analog signal multi-bit type ones mainly to convert directly into 16-bit PCM signal, twice to four audio sampling frequency of f _s = 32KHz~48KHz The sampling rate was about twice as fast.

Therefore, as the above-mentioned first-generation digital filters, those having a digitization ratio of 2: 1 or 4: 1 have been developed. In this case, the number of taps is about n = 128 to 256, and the number of taps is one. The speed was sufficient for an accumulator (that is, 48 kHz x 256 = 12.288 MHz). The main purpose of the digital filter in this case is to reduce the order of the pre-analog filter to prevent aliasing components from entering the original signal band. For this purpose, a higher decimation ratio is desirable. Since the number of taps increases in proportion to the decimation ratio and the number of multiply-accumulate times increases, it is difficult to directly process with one multiply-accumulator, and it is difficult to improve the speed of the 16-bit A / D converter itself From the point of view and the like, those having a decimation ratio higher than the above are not common.

In recent years, an oversampling noise shaping type A / D converter using a ΔΣ (delta sigma) modulation scheme has attracted attention as compared to the conventional multi-bit A / D converter. This, the input analog signal f _s
Is converted to a high-speed 1-bit PDM signal (pulse density modulation) of about 64 to 256 times of the above, and the quantization noise is shifted to a higher frequency band than the original signal band. In this case, the order of pre-analog filters 1-3 primary and, although is much reduced, sufficiently prevents high frequency shifted quantization noise, high-speed 1-bit 64f _s ~256f _s A second-generation digital filter (with a decimation ratio of about 1/64 to 1/256) is required to convert PDM signal data to 1 _fs multi-bit (16 to 20 bits) PCM signal data. Have been.
At this time, for example, if the decimation ratio is 1/64, the number of taps required for audio needs to be 2000 to 4000 taps, and the multiplier / accumulator requires a speed of 100 to 200 MHz. Was thought to be impossible to achieve.

Therefore, the second-generation digital filter has been realized by means of cascading a plurality of FIR filters in multiple stages. As an example, digital cascading with a total decimation ratio of 1/64 by cascading three-stage FIR filters
An outline of the filter is shown in FIGS. 12A, 12B and 12C.

FIG. 12A is a diagram showing a cascade arrangement of a three-stage filter, 1-bit PDM signal data 64f _s = 3.072 MHz that is input,
The 8 FIR digital filters (FIR1) is 1/8 decimated to become a 18 bit PCM signal data 8f _s = 384KHz, 1 in 9 of the FIR type digital filter (FIR2)
/ 4 is decimated becomes 2f _s = 96KHz, 18-bit data, 1/2 at 10 FIR type digital filter (fir3)
It is decimated output as 16-bit data of 1f _s = 48KHz.

Filter characteristics required for FIR1~FIR3, as shown in FIG. 12B, ± centered on n times 8f _s in FIR1 2
Noise 2 KHz, the noise of ± 22 KHz around the n times of 2f _s in FIR2, is intended to prevent the noise of ± 22 KHz around the n times f _s in fir3, hence F
IR1 is the slowest and FIR3 is the steepest transition region characteristic (± 22 KHz is when the passband of the original signal is up to 22 KHz).

As a result, the required number of taps for each filter is
For example, FIR1 can have 32 taps, FIR2 can have about 64 taps, and FIR3 can have about 128 taps.
32 × 384KHz = 12.228MHz in FIR2, 64 × 96KHz = 1.14 in FIR2
For 4MHz and FIR3, 128 × 48KHz = 6.144MHz. As an actual hardware configuration, as shown in FIG. 12C, 12.28 for FIR1 is used.
It is composed of an 8 MHz multiplier / accumulator 11 and a multiplier 12 that can be used for both FIR2 and FIR3. The multiplier / accumulator 11 has a multiplier 11-a and an accumulator 11-b, and the multiplier / accumulator 12 has a multiplier 12-a and an accumulator 12-b. 13, 14, 15 are data storage units for FIR1, 2, 3; 16, 17, 18 are coefficient data storage units for FIR1, 2, 3; and 19, 20 are selectors. Here, the multiplication unit 11-a is performed the product of the 1-bit data and coefficients w _i of the binary, which is + w _i or -
is to create w _i, which can be realized with a simple selector. Therefore, the 11-th power accumulator is composed of the 11-b accumulator and the selector, and is sufficiently small. Conversely, the 12-a multiplication unit multiplies the 18-bit data output from FIR1 or FIR2 by the same 18-bit coefficient data w _i ,
As described above, the circuit scale needs to be about ten times as large as the accumulator.

The problems with the multistage cascaded digital filter of FIR as described above are as follows: (1) The data word length of the interface between the filters and the filter coefficient word length are limited by the word length of the multiplier after FIR2. It is difficult to expand the dynamic range.

(2) To increase the word length of the multiplier, the circuit scale is squared (for example, if 18 × 18 (bit) is changed to 20 × 20 (bit), the scale becomes (20/18) ² = 1.23 times). ), The operation speed is slowed down, so 12MHz in commercial CMOS process
In order to achieve the speed of about 18 × 18 bits is the limit.

(3) Filters with a small number of taps, such as FIR1 and FIR2, do not provide sufficient passband characteristics and need to be corrected by FIR3, but the correction has an adverse effect on the stopband characteristics at FIR3. Will be given.

And so on.

[Problems to be Solved by the Invention] In each of the first and second generation digital filters described above, in each case, each operation cycle of digital filtering is completed using only a single power accumulator. Therefore, the filter characteristics, coefficient word length, input data word length, etc. are determined according to the operation speed and circuit size of a multiplier that can be practically realized, and the design flexibility is poor. The only way to improve performance was to wait for the multiplier speed and the number of bits to be increased due to advances in process technology.

In particular, since the 2nd generation digital filter for high oversampling data by recent ΔΣ modulation is a multi-stage type in which FIR1 and FIR2 etc. are cascaded just before the 1st generation filter, the interface word length between each filter and each The coefficient word length is limited to at most about 18 bits depending on the performance of the multiplier used in the final stage. Therefore, the high dynamic range of the ΔΣ modulation is reduced. Also,
Due to the multi-stage configuration, the correction of coarse filter characteristics in the first stage is forced to the multi-tap filter in the second stage, which is extremely inefficient in designing the filter characteristics as a whole.

It is an object of the present invention to eliminate a multi-bit multiplier for data from a high oversampling A / D converter such as ΔΣ modulation, realize a high decimation ratio only with a single-stage FIR filter, and achieve a dynamic range. It is an object of the present invention to provide a digital filter which can be expanded and does not require correction of the pre-filter characteristics.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a digital filter which operates on n-word input data and outputs one-word output data, wherein n / 2N (N ≧ 2) words 2N shift registers each having a self-loop for transferring data from the last part of the data string to the front row, N coefficient data storage units, and the same coefficient among the data from the shift register N means for adding two data to be multiplied by N, N operation units for performing an operation on data of the addition result from the addition means and coefficient data from the coefficient data storage unit, and N operation units And an accumulator for accumulating the output of the unit and outputting the one-word output data.

[Operation] According to the present invention, a filter having a large number of taps can be realized by the above configuration. In particular, a digital filter having a high decimation ratio can be realized with only a single-stage filter, and a cascade of conventional multi-stage filters can be realized. The disadvantage in the case can be eliminated. That is, it is possible to provide a high-performance filter that has a wide dynamic range, is not restricted by the speed limit of the multi-bit multiplier, does not require correction of the pre-stage filter characteristics, and is free from the influence of rounding errors due to the limitation of the interface word length between filters.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Specific examples here, 64f _s = 3.072M which is ΔΣ modulated
1/64 decimation is performed on a 1-bit PDM signal with a frequency of 22 kHz with a pass band of 22 kHz and an output rate of 1 _fs = 48 kHz.
A case where the present invention is applied to a digital filter that outputs a bit PCM signal will be described.

Since the decimation ratio is 1/64, the number of taps of the digital filter needs to be about 2,000 to 4,000 for audio, but for simplicity, it is assumed that n = 2048. One operation cycle, that is, one operation cycle Is simply 2048 times, but 1 / 2n = 1048 if the pre-stage addition method (described later) that uses the left-right symmetry of the coefficient, which is a feature of the FIR filter, is used. Become. In other words, it uses the property of w _i = w _{n-i + 1} , Is what you want. Filter coefficient of FIR type filter
w _i , the unit impulse response,
As shown in Fig. 13, the value of the main lobe at the center is large, and decreases toward both ends, and it is symmetric. Here, since it is for 1/64 decimation, the rough filter characteristic is a low-pass filter with a pass band of 0 to 22 KHz and a stop band of 28 KHz or more as shown in FIG. Filter characteristics are, of course, 1/2 × 3.0
It is symmetric around 72MHz = 1.536MHz.

FIG. 1 is a block diagram of a first embodiment of the present invention in which pre-stage addition is not used.

In this embodiment, the operation speed of one multiply-accumulator is set to 1
2.288MHz = and _{256f s, n · f s /} 256f s = 2048/256 = 8 pieces of multiply accumulators (23, 24, 25, ... 30) parallel processing is performed (each multiply accumulator by the Multiplication unit (example: 23-a) and accumulation unit (example;
23-b)). 1 bit data ΔΣ modulated input (a _i), since that represents the binary ± 1, the multiplication of each multiply accumulator is substantially select a + w _i or -w _i selector Is fine. In the coefficient data storage section 21 data output from the always + w _i, if the data of the 2's complement form, -w _i
Can be easily realized by inverting the above and inputting a 1 LSB carry input to the accumulator. Therefore,
Here, the circuit scale of each power accumulator is almost the same as that of a simple accumulator, and it is possible to achieve a sufficiently high speed and multi-bit operation, and therefore a high dynamic range.

The eight accumulators (23, 24, 25,..., 30) share 256 operations each obtained by dividing one operation cycle into eight. That is, the data a _-i from the input data storage unit 21 and the coefficient storage unit 22
Coefficients from the data w _i are respectively divided into eight, Q1 to Q8 and W1
To W8 are supplied in parallel to the first to eighth multiplying accumulators (23, 24, 25,..., 30). Is required. These results are sent to 31 final accumulators, _Obtains and outputs b _j .

The number of bits of the multiplying and accumulating units shown in FIGS. 1 to 8 is not necessarily the same, and can be determined by the value of the filter coefficient of the operation division shared by each. That is, the filter coefficient w _i
Since the median value is large at the center and small at both ends as shown in FIG. 13, for example, if the fourth and fifth multipliers at the center are 28 bits, the first and eighth multipliers at both ends are The device needs only about 20 bits.

FIG. 2 is a block diagram of a second embodiment of the present invention in which pre-stage addition (details will be described later with reference to FIG. 3). In this embodiment, assuming that the operation speed of the multiplier-accumulator is the same as the previous example, (1/2 × 2048) / 256 = 4 multiplier-accumulators may be used. New pre-stage adder (eg 34-a) is ± 1
(Example: Q1, Q8) data (a _-i and
a _{-n + i-1} ) and outputs three values of + 2,0, -2. This can be realized with several gates, and the circuit scale is negligible. The multiplier (eg, 34-b) has a filter coefficient w
_i respect, multiplied by one of the three values, + 2w _i, 0, -2w _i
Of it making any, which is either +1 times or 0 times if as a pre-+ 2w _i the data in the coefficient data storage unit 33,
Only -1 times is selected, and can be realized with a simple selector, and the circuit scale is sufficiently small. Therefore,
As compared with the previous embodiment (FIG. 1), it can be an operation unit having a circuit scale of about half.

The input data a _i from the input data storage unit 32 is divided into eight, and from Q1 to Q8, the coefficient data w _i from the coefficient data storage unit 33
Is divided into four and output from W1 to W4. Where Q1-Q4
The first half portion a _-1 ~a _-1024 of the input data a _i, Q8~Q4 outputs the same second half portion a _-2048 ~a _-1025, moreover Q1 and Q8, Q2 and Q7, Q3
And Q6, Q4 and Q5 simultaneously output the respective symmetrical components (a- _i and a- _{n + i-1} ) and add the pre-stage at each adder 34-a, 35-a, 36-a, 37-a The sum output and W1 from the coefficient data storage unit 33
To W4 are the first to fourth multipliers 34-b, 35-b, 36-b, 37-
b). Therefore, using the 2048 a- _i and 1024 w _i , the first to fourth pre-stage adders (34-a to 37-
a), multipliers (34-b to 37-b) and accumulators (34-c to 37-37)
−c) means that each of the 256 calculations And in the 38 final accumulators Is output.

The number of bits of each of the first to fourth accumulators 34-c to 37-c may be the same as the number of bits of each of the first to fourth accumulators of the previous embodiment. Since the coefficient values are all doubled, the accumulation result itself must be doubled as in the previous embodiment. However, since the LSB of the coefficient value is always 0 due to the doubling, the accumulator itself is also changed. There is no need to calculate the LSB unit, and the practical configuration requires the same number of bits.

Then, the tap number n = 2048 suitable for audio applications, decimation ratio y: 1 = 64: 1, the data output rate f _s = 48KHz
FIG. 3 shows a third embodiment for realizing the two-channel digital filter. This is an extension of the embodiment of FIG. 2 using the pre-stage addition method for two channels, and includes a multiplying accumulator (pre-stage adder (eg: 43-a), a multiplier (eg:
43-b) and the number of accumulators (eg with 43-c) is necessary. Note that each of the two channels is Left and
Right.

The eight accumulators (43, 44,..., 50) perform calculations for each channel by sharing 256/2 = 128 calculations. Therefore, for Left and Right obtained as described below
The data output from the input data storage units 63 and 64 is divided into 2 × 8 = 16 and output from Q1L to Q16L and Q1R to Q16R, and selects Left or Right based on CK17 from the control unit 66. Q1L to Q16L output by selecting means 41
Q1R to Q16R outputs are alternately selected and input to the first to eighth pre-stage adders. The control unit 66 is described below.
The CL11 to CK19 (L, R) clocks are output. The shift register 65 corrects the phase difference between the two channels, and consists of Y / 2 = 32 bits (1 word = 1 bit in this example), and operates at the timing of CK11R from the control unit 66. and, Right data (a _i, R) Left for data (a _i, L) is delayed 32 words from the input to the data storage unit 64, b _jL and b _jR is outputted from the final accumulator 51 Make it simultaneous sampling data.

The coefficient data w _i from the coefficient data storage unit 42 is outputted from the 8 divided by W1 to W8, is input together with the previous stage adder output to the accumulator of the first to eighth. Where the coefficient data
w _i is shared because both channels are equal. That, W1 to W8 are respectively 1024 coefficient data, W1 is w ₁₂₈ ~
w ₁ and W 2 are shared and supplied in parallel, such as w ₂₅₆ to w ₁₂₇ ,..., W 8 are w ₁₀₂₄ to w ₈₉₇ . From each of the 16 output data lines from the data storage units (63, 64) of each channel, 204
Eight of the past data a _-1L ~a _-2048L, is a _-1R ~a _-2048R each 1/2
In 16 parallel to each calculation cycle, at 2048/16 = 128 timing is sent sequentially to each multiply-accumulate unit, supplied with the w _i to each multiplier after the previous stage adder.

Each of the first to eighth pre-stage adders and each multiplication and accumulator are:
128 operations are assigned to each channel in parallel and processed in parallel. , And with the final accumulator of 51, The output data of each channel is obtained and output.

The structure and operation of the 63 left data storage units will be further described below with reference to FIGS. Note that the 64 Right-side data storage unit has the same configuration as 63,
There is only a time delay for the operation cycle. In FIG. 4, the storage means for storing n = 2048 past data is divided into 2N = 16 section registers corresponding to the above-mentioned eight pre-stage addition, multiplication and accumulators. (Indicated by 101 to 116 in the figure). Each of these section registers is a unidirectional shift register of n / (2N) = 128 bits. 100 is an input register for storing the input data for the next calculation cycle _{(a 0 ~a 63), f} j ×
y = 48KHz × 64 = 3.072MHz clock CK11 always D0
The input data _ai is fetched more and the internal shift operation is continued. The direction change register 117 is a- _{n ] 2 to} a- _{(n ).
2) + y-1} , i.e. data from a _{-1024 to} a _-961
The direction is changed by the 19 transfer means and sent to the ninth section register (109), and y = 6 for changing the direction of the data.
This is a 4-bit shift register.

121 to 136 are selection means for switching data lines, 121 to 128 are controlled by CK18, 129 to 136 are controlled by CK19, and control signals (CK18, CK19) are all High.
In this case, the transfer to the next section can be performed, and when it is Low, the transfer can be switched so that the self-loop transfer in each section can be performed. However, the selection means in Section 8
128 connects the output Q8 to the input line D17 of the direction change register 117 when CK18 is high. The selection means of 136 connects Q16 to D16 when CK19 is low, and CK19 is high.
In the case of, Q16 and D16 are released. That is, the selection means 13
6 only needs to have a function for the self-loop and a function for preventing data transfer from the previous (15th) section, and does not require a function for transfer to the next section.

Numeral 118 denotes a parallel rewriting / transferring means of y = 64 bits, which is capable of parallel rewriting / transferring the data of the first to 64th bits of the register 100 to the first to 64th bits of the register 101 by CK15. Reference numeral 119 denotes a y = 64-bit parallel rewriting / transferring means for transferring each of the first to 64-bit data of the register 117 to CK16.
Thereby, parallel rewrite transfer can be performed to the 124th to 65th bits of the register 109 such that the data shift direction is reversed.

FIG. 5 is an example of the timing of each signal in one operation cycle. Here, during the first period, the data Q1L to Q16L are L / R
The period of transmission to the selection means 41, that is, the multipliers 43 to 50
The second period is a period for moving each data (preparation period) for performing the next operation. Each of the first period and the second period is further divided into a and b, and
6 to 9 show the final state in each of the sections -a to 2-b. In the 1-a period, CK18 = High and CK19 = Low, the selection means 121 to 128 are connected to the next section, and the other selection means 129 to 136 set the ninth to sixteenth sections in a self-loop state. I do.

Accordingly, y times CK12～CK14, i.e. by 64 times the clock, from Q1 to Q16 (a _-65 from a _-128), ...,
(A _-1024 to a _-961 ), (a _-1025 to a _-1088 ), ... (a
_-1921 to a _-1984 ) are output, the output data of Q1 to Q7 is shifted into the 64th to 1st bits of Q2 to Q8 in the next section, and the output of Q8 is changed to the direction change register 11
7 is shifted to the 64th to 1st bit, and the output data of Q9 to Q16 are self-looped and input to the 64th to 1st bits of the 9th to 16th section registers. Any data existing in the first to 64th bits of each section register is shifted to the 65th to 128th bits.

The 100 input register, the 16 data a ₀ ~a ₁₅ for the next time the CK11 is shifted into the first 16 first bit. The above results are shown in FIG. The above 1
Since the initial state of the period -a is a result that can be easily understood from the operation within one operation cycle, the description is omitted.

Next, in the 1-b period, as shown in FIG.
18 = Low, CK19 = High, and the selecting means 121 to 128
The eighth section register is set to a self-loop state, and the selection means 129 to 136 connect Q9 to Q15 to D10 to D16, respectively, that is, connect the ninth to sixteenth section registers to the register of the next section. 128-y of CK12 and CK14 = 64
The remaining clocks from Q1 to Q16 (a _-64 to a
_-1), ..., from (a _{-960 -897),} from (a _-1089
a _-1152 ), ... (a _-1985 to a _-2048 ) are output, and the output data of Q1 to Q8 are self-
The feedback is input to the 64th to 1st bits of the 8th section register, and the outputs of Q9 to Q15 are the registers of the next section, that is, the 64th to 64th bits of the 10th to 16th section registers.
The data is shifted into the first bit. The data existing in the 1st to 64th bits of each section register shifts to the 65th to 128th bits in each section. CK13 is stopped, direction change register
Reference numeral 117 denotes the same state as at the end of the period 1-a. In the input register 100, data of a ₀ ~a ₃₁ is input further to 16 times the 32 to the first bit by a clock of CK11 in.
The result of the above operation is as shown in FIG.

Next, in the period 2-a, as shown in FIG. 8, CK18 = Low and CK19 = Low, and all the first to sixteenth section registers enter a self-loop state. Therefore, the 64th clock of CK12 and CK14 transfers the data of the 1st to 64th bits in all section registers to the 65th to 64th clocks.
The data moves to the 128th bit, and the data of the 65th to 128th bits moves to the 1st to 64th bits. CK13 is stopped, and the data content of the direction change register 117 remains unchanged. In the input register 100, data of a ₀ ~a ₄₇ is input further to 16 times the 48 to the first bit by a clock of CK11 in. The above results are as shown in FIG. 8, and the 64-bit shift for the next operation cycle is performed by shifting the first to 64th bits of the first section register and the 65th to 128th bits of the ninth section register. It is completed except.

Finally, in the 2-b period, the direction change register 117 is used.
The 64 data a _{-1024 to} a _-961 of the ninth section register 109 are transferred via the transfer means (119) by the clock of _CK16.
Is transferred in parallel to the 65th to 128th bits. The input data for the shift register 100, the next data a ₀ ~a ₆₃ is input to the 64 to the first bit by a clock of the remaining sixteen CK 11. After a ₀ ~a ₆₃ is aligned to the register 100, data of a ₀ ~a ₆₃ by clock CK15 through transfer means 118 is transferred to the first 64 to the first bit of the first section register (101). The above result is as shown in FIG. 9, and the data in all the section registers are stored again in a form shifted by 64 bits for the next operation cycle. That is, the initial state of the current operation cycle (first-
The first to the 64th bit data of the first to the eighth section registers are respectively transferred to the 65th to the 128th bits of the section register by 64 bits in the same section.
The data is shifted by bits and the data of the 65th to 128th bits of the first to seventh section registers are shifted to the 1st to 64th bits of the next section (second to eighth) registers, respectively. The data of the 65th to 128th bits of the section register is changed in direction and moved to the 128th to 65th bits of the ninth section register, and the 9th to 16th sections
The data of the 65th to 128th bits of the register is shifted by 64 bits in the reverse direction to the 1st to 64th bits of the same section register, and the 1st to 64th bits of the 9th to 15th section registers are respectively shifted. The data in each of the following sections (No.
10th to 16th) Move to the 65th to 128th bits of the register, discard the oldest data a- _{2048 to} a- ₁₉₈₅ of the 1st to 64th bits of the 9th section register, and discard the 1st section register. 64 new data a _{63 to} a ₀ newly input during the current operation cycle are input to the first to 64 bits, and a new data set for the next operation cycle is created.

It can be easily understood that the initial data state used in the above description is created by repeating the above one operation cycle operation.

In the above-mentioned period 2-b, CK15 and CK16 are the last one pulse in the example shown in FIG. 5 for circuit simplification and easy understanding, but actually CK15 is the first section pulse. The timing may be any time when the next data can be written to the first to y-th bit positions of the register, that is, immediately after the shift y in the first period is completed or after the shift y in the second period is completed. CK16 completes the transfer of the y bits from the eighth section register to the ninth section register, and transfers this to the (n / 2N) th to ((n / 2N) -y + 1) bits of the ninth section register. The transfer may be performed at any time, that is, immediately after the end of the ((n / 2N) -y) shifts in the first period or after the end of the ((n / 2N) -y) shifts in the second period.

In the third embodiment, CK13 and CK18 can be at the beginning of the second period, like CK13 'and CK18' shown in FIG.

In the third embodiment, (n / 2N) -y = 64 and y = 64 are equal. However, when these are different, the same can be achieved by controlling at the timing shown in FIG. is there. That is, CK13 (or CK13 ') shifts y times at the beginning of the first period (or the second period) when CK18 = High (or CK18' = High), and advances the first half section register (to the next section register). CK19 fetches the y-bit direction change data into the direction change register at the time of (transfer state), CK19 causes the last y shift operations of the first period to advance the second half section register, and CK12 sets y at the second period. This is possible by causing the first half and second half section registers to perform a self-loop-type shift operation using ((n / 2N) -y) clocks.

The present invention can be applied to a case where the number of taps n is an odd number or a case where n / 2N is not an integer. If the number of taps n is odd, the output b _{j in} one operation cycle is Is determined by That is, the preceding-stage addition is omitted only for the median a− _{(n + 1) / 2} , and the other data a _{−1 to} a
_{− (N−1) / 2} , a− _{(n + 3) / 2 to} a− _n , where (n−
1) It is necessary to carry out (n + 1) / 2 times of accumulative accumulation in total by executing the pre-stage addition twice. As an example of a data storage device for realizing this, in the third embodiment shown in FIG.
Only the register has ((n + 1) / 2N) -1 bits, and all other section registers have (n + 1) / 2N bits, so that the shift operation clock CK14 'of the ninth section register is the tenth to sixteenth bits. CK14 for section register
And can be realized by controlling independently. That is, CK14 'has ((n + 1) / 2N) -1 pulses without the first pulse in the first period, and {(n + 1 / 2N) -1-y} pulses in the second period. The transfer means 119 transfers the data in the first to y-th bits of the direction change register 117 to the ｛(n +
1 / 2N) -1} to {(n + 1 / 2n) -y} bits. Regarding the data output from the data storage device having this configuration, the arithmetic unit sends the data of Q8 to the multiplier without performing the first-stage addition for Q8 and Q9 only in the first time of the first period, or For example, the former-stage addition to the median value can be omitted by a method such as addition of zero and zero.

Next, in the third embodiment, when n / 2n is not an integer, the minimum number exceeding n and a multiple of 2N is defined as n ', and n' is used as the number of taps. A storage device is constructed, and a- ₁ to a- _{(n'-n) / 2} , a at both ends are formed.
_This is realized by not _performing multiplication _/ accumulation on _{−n ′ to} a− _{n ′ + {(n′−n) / 2} −1} . Here, n is considered to be an even number, but when n is an odd number, it is clear that it can be easily realized by combining with the above method.

Since the number of bits of each accumulator is halved, if the maximum eighth accumulator is 27 bits, the first accumulator is about 19 bits.

In each of the above embodiments, the final accumulator was used because the number of taps was n = 2048. However, if the number of taps is slightly reduced, the final accumulation is performed using an extra operation cycle of each power accumulator. It is also possible to do.

In the above description, the number of taps n is set to 2048. However, a high-performance filter having a larger number of taps can be easily coped with by increasing the number of multipliers. The accumulator is, for example, 4 bits
Since it can be realized by a combination of CLAs, unlike a multi-bit multiplier, there is no delay in speed due to an increase in the number of bits. Therefore, it is easy to increase the dynamic range by employing a larger bit word length.

According to the present invention, it is possible to realize a digital filter having a high decimation ratio for high oversampling data such as Δ 高 modulation. Since a conventional multi-bit multiplier (for example, 18 bits × 18 bits) is not required, a higher speed and larger bit word length operation can be realized by a small-scale circuit, and a high-performance filter having a larger number of taps can be realized. be able to.

Further, the performance deterioration due to the correction of the pre-stage filter characteristics and the rounding error of the finite bit word length in the interface between filters, which are disadvantages of the conventional multi-stage FIR cascade system, can be eliminated.

[Brief description of the drawings]

FIGS. 1 to 10 relate to each embodiment of the present invention. FIG. 1 is a block diagram of a filter according to the first embodiment which performs parallel processing in eight arithmetic units without using pre-stage addition. FIG. 2 is a block diagram of a filter for performing parallel processing in four operation units using pre-stage addition, and FIG. 3 is a diagram illustrating parallel processing in eight operation units for two channels using pre-stage addition. FIG. 4 is a block diagram showing an example of one channel portion of the data storage section in the embodiment of FIG. 3 in detail, and FIG. 5 is a block diagram showing each control applied to the example shown in FIG.
FIGS. 6 to 9 show an example of the timing of the clock signal, FIGS. 6 to 9 show the data movement states in each period in FIG. 5, and FIG. 10 shows {(n / 2N) -y} and y. FIG. 11 is a diagram showing an example of the timing when the present invention is applied when is not equal, FIG. 11 is a diagram showing the configuration of a digital filter, and FIG. 12A is a diagram showing a decimation ratio of 1 / FIG. 12B is a diagram showing the filter characteristics of each stage in the filter, FIG. 12C is a block diagram showing the actual configuration of the filter, and FIG. 13 is a filter coefficient w of the FIR filter. _i , that is, a diagram schematically showing a unit impulse response, and FIG. 14 is a diagram showing an example of a filter characteristic for 1/64 decimation. 21: input data storage unit, 22: coefficient data storage unit, 23 to 30: first to eighth power accumulators, 23-a: 1 × n bit multiplier, 23-b: accumulation Container, 31 ... The final accumulator.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-278411 (JP, A) JP-A-63-84313 (JP, A) JP-A-1-233909 (JP, A) JP-A-61-1983 288613 (JP, A) JP-A-61-277216 (JP, A) JP-A-59-22166 (JP, A) JP-A-59-166516 (JP, U) (58) Fields investigated (Int. ⁷ , DB name) H03H 17/00-17/08

Claims (2)

(57) [Claims] 1. A digital filter for calculating input data of n words and outputting output data of one word comprises a data string of n / 2N (N.gtoreq.2) words, wherein 2N shift registers having a self-loop for transferring data to the front row; N coefficient data storage units; and N addition means for adding two data multiplied by the same coefficient among the data from the shift registers. An N number of operation units that operate on data of the addition result from the addition unit and coefficient data from the coefficient data storage unit, and accumulate the outputs of the N number of operation units, and output the one-word output data. A digital filter, comprising: an accumulating unit that outputs. 2. The digital communication device according to claim 1,
A digital filter, wherein the number of bits in the coefficient data storage unit and the number of bits in the arithmetic unit differ depending on the size of a filter coefficient.