JP2022115280A - Analog-digital conversion circuit, analog-digital conversion device, analog-digital conversion method, and program - Google Patents

Abstract

To provide an analog-digital conversion circuit, an analog-digital conversion device, an analog-digital conversion method, and a program, capable of reducing the number of circuit components for a digital filter and increasing calculation processing speed.SOLUTION: An analog-digital conversion circuit 10 of the disclosure includes: a pre-filter 14 for performing band limit for an analog signal; an over-sampling type encoder 15 for quantizing band limited analog signal and outputting a digital signal; a digital filter coefficient storage memory 111 for storing a plurality of digital filter coefficients; a first inverter 112 for receiving a first inverter input filter coefficient selected from among a plurality of digital filter coefficients, and outputting an inverted first filter coefficient whose coefficient is inverted version of the first inverter input filter coefficient; and a first pre-stage adder 113 for outputting an inverted-added first filter coefficient obtained by adding +1 to the inverted first filter coefficient.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to an analog-to-digital conversion circuit, an analog-to-digital conversion apparatus, an analog-to-digital conversion method, and a program. The present invention relates to a digital conversion circuit, an analog-to-digital conversion device, an analog-to-digital conversion method, and a program.

Two's complement arithmetic may be used to suppress overflow calculations. As a result, the stability of the system can be ensured, but the circuit scale becomes large due to the complexity of the processing at the time of minus operation. Specifically, the analog-to-digital conversion circuit 50 (see FIG. 3 described later) includes a prefilter 54 , an oversampled encoder 55 and a digital filter 51 . The digital filter 51 includes a digital filter coefficient storage memory 511 , a first inverter 512 , a first pre-selector 514 , a first pre-adder 515 , a first post-selector 517 and a first post-adder 518 . The output signal of the oversampled encoder 55 is used as a control signal for the first pre-selector 514 and the first post-selector 517 . The output signal of the oversampled encoder 55 is output in "2's complement". When the output signal of the oversampling encoder 55 is "+1", the output signal (filter coefficient) of the digital filter coefficient storage memory 511 is directly used as the output signal of the first post-adder 518 (first pre-adder 515). There is a need to. Further, when the output signal of the oversampling encoder 55 is "-1", the output signal (filter coefficient) of the digital filter coefficient storage memory 511 is inverted by the first inverter 512, and "+1" is added to the value. It should be the output of the first post-adder 518 . In order to do this, the digital filter 51 must be configured with two selectors (first pre-stage selector 514 and first post-stage selector 517) per one tap (TAP). selector is required. As a result, the circuit configuration of the digital filter 51 becomes complicated, and the number of parts used in the circuit increases according to the number of taps (order) of the filter.

In Patent Document 1, "In an oversampling analog/digital converter having an oversampling encoder that quantizes an input signal and outputs a binary output signal consisting of a positive value and a negative value, the oversampling encoder outputs a counter section for counting the number of negative values of the output signal, a storage section for storing n filter coefficients, and the filter coefficients stored in the storage section for output signals from the oversampling encoder. An over-sampling analog/digital converter having a first arithmetic unit that sequentially multiplies and adds the multiplication results, and a second arithmetic unit that adds the number counted by the counter unit to the arithmetic result of the first arithmetic unit. ” is stated.

In Patent Document 2, "In a multiplier, input data is multiplied by a coefficient, and this is supplied to an adder. By this addition, the moving average of the output is calculated.Then, the moving average is obtained by starting the addition result at a predetermined timing in the output register.Here, the calculation after the adder is performed in two's complement. Then, the limiter reduces the output by 1 bit from the number of bits used in the calculation, and clips values exceeding the maximum positive and negative values.The operation is performed in two's complement, and the clipped value has both positive and negative values.Therefore, it is possible to secure a sufficient dynamic range and reduce the adverse effects of clipping on data."

JP-A-4-35417 JP-A-9-238048

As described above, the digital filter of the analog-to-digital conversion circuit is composed of two selectors per one tap (TAP), so a total of the number of filter taps×2 selectors is required. As a result, the configuration of the digital filter circuit becomes complicated, and the number of parts used in the circuit increases according to the number of taps (order) of the filter, resulting in the problem that arithmetic processing takes a long time.

An object of the present disclosure is to provide an analog-to-digital conversion circuit, an analog-to-digital conversion device, an analog-to-digital conversion method, and a program that solve any of the problems described above.

The analog-to-digital conversion circuit according to the present disclosure is
a prefilter for bandlimiting the analog signal;
an oversample encoder that quantizes the band-limited analog signal and outputs a digital signal;
a digital filter coefficient storage memory that stores a plurality of digital filter coefficients;
a first inverter receiving a first inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
a first pre-adder that outputs an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
a first selector that outputs the first selector input filter coefficient selected from the inverse addition first filter coefficient or the plurality of digital filter coefficients based on the digital signal;
Prepare.

The analog-to-digital conversion device according to the present disclosure is
Equipped with an analog-to-digital conversion circuit that converts analog signals to digital signals,
The analog-to-digital conversion circuit is
a prefilter for bandlimiting the analog signal;
an oversample encoder that quantizes the band-limited analog signal and outputs a digital signal;
a digital filter that performs arithmetic processing on the digital signal,
The digital filter is
a digital filter coefficient storage memory that stores a plurality of digital filter coefficients;
a first inverter receiving a first inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
a first pre-adder that outputs an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
a first selector for outputting the inversion addition first filter coefficient or a first selector input filter coefficient selected from among the plurality of digital filter coefficients, based on the digital signal.

The analog-to-digital conversion method according to the present disclosure includes
band limiting an analog signal;
quantizing the band-limited analog signal and outputting a digital signal;
storing a plurality of digital filter coefficients;
receiving a first inverter input filter coefficient selected from among the plurality of digital filter coefficients, and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
outputting an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
outputting the inverse addition first filter coefficient or a first selector input filter coefficient selected from among the plurality of digital filter coefficients based on the digital signal;
Prepare.

The program according to the present disclosure is
band limiting an analog signal;
quantizing the band-limited analog signal and outputting a digital signal;
storing a plurality of digital filter coefficients;
receiving a first inverter input filter coefficient selected from among the plurality of digital filter coefficients, and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
outputting an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
outputting the inverse addition first filter coefficient or a first selector input filter coefficient selected from among the plurality of digital filter coefficients based on the digital signal;
run on the computer.

According to the present disclosure, it is possible to provide an analog-to-digital conversion circuit, an analog-to-digital conversion device, an analog-to-digital conversion method, and a program capable of reducing the number of circuit components of a digital filter and speeding up arithmetic processing. .

1 is a block diagram illustrating an analog-to-digital converter according to an embodiment; FIG. 1 is a block diagram illustrating an analog-to-digital conversion circuit according to an embodiment; FIG. 3 is a block diagram illustrating an analog-to-digital conversion circuit according to a comparative example of the embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same or corresponding elements, and redundant description will be omitted as necessary for clarity of description.

[Embodiment]
<Configuration>
FIG. 1 is a block diagram illustrating an analog-to-digital conversion device according to an embodiment.
FIG. 2 is a block diagram illustrating an analog-to-digital conversion circuit according to the embodiment;

As shown in FIG. 1, an analog-to-digital conversion device 10a according to the embodiment includes an analog-to-digital conversion circuit 10 that converts an analog signal into a digital signal. The analog-to-digital conversion circuit 10 has a prefilter 14 , an oversampled encoder 15 and a digital filter 11 . An oversampled encoder is sometimes called an oversampled A/D encoder.

The prefilter 14 band-limits the analog signal that is the input signal. The oversample encoder 15 quantizes the band-limited analog signal, which is the output signal Y1 of the prefilter 14, and outputs a digital signal as an output signal Y2. The digital filter 11 performs arithmetic processing on the digital signal and outputs an output signal Y3.

As shown in FIG. 2 , the digital filter 11 has a digital filter coefficient storage memory 111 , a first inverter 112 , a first pre-adder 113 and a first selector 114 .

The digital filter coefficient storage memory 111 stores a plurality of digital filter coefficients.

The first inverter 112 receives the output signal of the digital filter coefficient storage memory 111 . The first inverter 112 receives a first inverter input filter coefficient selected from among a plurality of digital filter coefficients, and outputs an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient.

The first pre-adder 113 receives the output signal of the first inverter 112 . The first pre-adder 113 outputs an inverted addition first filter coefficient obtained by adding the inverted first filter coefficient and "+1".

The first selector 114 receives the output signal of the digital filter coefficient storage memory 111 and the output signal of the first pre-adder 113, and further uses the output signal (digital signal) of the oversample encoder 15 as a control signal input. . The first selector 114 outputs an inverted addition first filter coefficient or a first selector input filter coefficient selected from a plurality of digital filter coefficients based on a digital signal (control signal).

The digital filter 11 further includes a first post-adder 115 that outputs the output of the first selector 114 as the output of the first post-adder 115 .

The digital filter 11 further includes a second delay device 126 , a second inverter 122 , a second pre-adder 123 , a second selector 124 and a second post-adder 125 .

A second delay device 126 delays the digital signal that is the output signal of the oversampled encoder 15 .

The second inverter 122 receives a second inverter input filter coefficient selected from among a plurality of digital filter coefficients, and outputs an inverted second filter coefficient obtained by inverting the second inverter input filter coefficient.

The second pre-adder 123 outputs an inverted added second filter coefficient obtained by adding the inverted second filter coefficient and "+1".

The second selector 124 receives the output signal of the digital filter coefficient storage memory 111 and the output signal of the second pre-adder 123, and further uses the output signal of the second delay device 126 as a control signal. That is, the second selector 124 selects a second selector input filter coefficient selected from an inversion-addition second filter coefficient or a plurality of digital filter coefficients based on the digital signal delayed by the second delay device 126. to output

The second post-adder 125 adds the output signal of the second selector 124 and the output signal of the first post-adder 115 .

The digital filter 11 further includes a third delay device 136 , a third inverter 132 , a third pre-adder 133 , a third selector 134 and a third post-adder 135 .

The third delayer 136 further delays the digital signal delayed by the second delayer 126 .

The third inverter 132 receives a third inverter input filter coefficient selected from among a plurality of digital filter coefficients, and outputs an inverted third filter coefficient obtained by inverting the third inverter input filter coefficient.

The third pre-adder 133 outputs an inverted addition third filter coefficient obtained by adding the inverted third filter coefficient and "+1".

The third selector 134 receives the output signal of the digital filter coefficient storage memory 111 and the output signal of the third pre-adder 133, and uses the output signal of the third delay device 136 as a control signal. That is, the third selector 134, based on the digital signal delayed by the third delay device 136, the third selector input filter coefficient selected from the inverted addition third filter coefficient or a plurality of digital filter coefficients to output

The third post-adder 135 adds the output signal of the third selector 134 and the output signal of the second post-adder 125.

<Operation>
Here, the operation of the analog-to-digital conversion circuit 10 will be described.
First, an input signal (analog signal) input to the analog-to-digital conversion circuit 10 is band-limited by the pre-filter 14 .

The band-limited analog signal is input to oversampled encoder 15 . The oversampling encoder 15 is of a noise shaping type, and its output signal is a binary signal of ±1.

A selector (first selector 114, second selector 124, etc.) adds a signal selected from the signals of the digital filter coefficient storage memory 111 based on the output signal (control signal) of the oversampled encoder 15. To go. The digital filter 11 repeats this addition process by the number of delay units (the second delay unit 126 and the like) (by the order of the filter) and performs weighted averaging.

Numerical values and calculations in the digital filter coefficient storage memory 111 are performed using 2's complements. Therefore, when the output signal of the oversampling encoder 15 is "+1", it is necessary to use the numerical value in the digital filter coefficient storage memory 111 as it is. Further, when the output signal of the oversampled encoder 15 is "-1", it is necessary to invert all bits and add "+1".

Therefore, in the embodiment, two types of values are input to the selector when the output signal of the oversampling encoder 15 is "+1" and "-1" with respect to the value of the digital filter coefficient storage memory 111. Then, the selector is used to select one of the two types of values.

This allows two's complement arithmetic to be performed using one selector per degree. As a result, compared to the case of using two selectors (see a comparative example which will be described later), it is possible to simplify and speed up arithmetic processing and reduce the circuit scale.

As a result, according to the embodiments, an analog-to-digital conversion circuit, an analog-to-digital conversion device, an analog-to-digital conversion method, and a program that can reduce the number of circuit components of a digital filter and speed up arithmetic processing are provided. can do.

Features of the embodiment are as follows.
By reducing the number of selectors per one tap number (order) of the digital filter and reviewing the configuration of the adder, the number of parts of the digital filter is reduced and the arithmetic processing speed is increased.

[Comparative example]
FIG. 3 is a block diagram illustrating an analog-to-digital conversion circuit according to a comparative example of the embodiment;

As shown in FIG. 3, the process is the same as the embodiment up to the time when the analog signal is input to the oversampled encoder 55 . When the analog signal is quantized from the oversampling encoder 55, the output signal is a 1-bit signal. Since the noise shaping method is used, the spectrum of the quantization noise concentrates on the high frequency side. have The digital filter 51 has a role as a low-pass filter for removing quantization noise concentrated on the high frequency side. The digital filter 51 removes quantization noise and outputs an output signal with a high S/N ratio.

The digital filter 51 has a filter configuration called a non-recursive type. The output signal of the over-sampling encoder 55 is a 1-bit signal and takes two values of ±1. The digital filter coefficient storage memory 511 stores filter coefficients. Arithmetic operation in the digital filter 51 is executed by 2's complement arithmetic, so the filter coefficients are stored in 2's complement notation. The digital filter 51 multiplies and adds the filter coefficients of the digital filter coefficient storage memory 511 through the second delay device 526, the third delay device 536, etc., one after another (by the order of the filter), and averages them.

The output signal of the oversampled encoder 55 is used as a control signal for the first pre-selector 514 and the first post-selector 517 . The output signal of the oversampled encoder 55 is output in "2's complement". When the output signal of the oversampling encoder 55 is "+1", the output signal (filter coefficient) of the digital filter coefficient storage memory 511 is directly used as the output signal of the first post-adder 518 (first pre-adder 515). do. When the output signal of the oversampling encoder 55 is "-1", the output signal (filter coefficient) of the digital filter coefficient storage memory 511 is inverted by the first inverter 512, and the value obtained by adding "+1" is the first value. It is the output signal of post-adder 518 .

In this way, the digital filter 51 is composed of two selectors (for example, the first pre-selector 514 and the first post-selector 517) per one tap (TAP), so the total number of filter taps×2 selectors is Is required. Therefore, the number of selectors is doubled compared to the digital filter 11 according to the embodiment, and the number of parts is large.

As a result, according to the comparative example, an analog-to-digital conversion circuit, an analog-to-digital conversion device, an analog-to-digital conversion method, and a program capable of reducing the number of circuit components of a digital filter and speeding up arithmetic processing are provided. difficult.

Although the present invention has been described as a hardware configuration in the above embodiment, the present invention is not limited to this. The present invention can also be implemented by causing a CPU (Central Processing Unit) to execute a computer program to process each component.

In the above embodiments, the programs can be stored and delivered to computers using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (specifically flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (specifically magneto-optical discs), CD-ROMs (Read Only Memory ), CD-R, CD-R/W, semiconductor memory (specifically, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM)), flash ROM, and RAM (Random Access Memory). The program may also be delivered to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired channels, such as wires and optical fibers, or wireless channels.

Further, although acts have been depicted in a particular order, this does not mean that such acts are performed in the specific order or sequential order shown, or It should not be understood as requiring that all actions be performed. Multitasking and parallelism can be advantageous in certain situations. Similarly, while details of several specific embodiments have been included in the above discussion, these should not be construed as limitations on the scope of this disclosure, but as illustrations of features unique to those particular embodiments. should. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable combination.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

It should be noted that the present invention is not limited to the above embodiments, and can be modified as appropriate without departing from the scope of the invention.

10: analog-digital conversion circuit 10a: analog-digital conversion device 11, 51: digital filter 111, 511: digital filter coefficient storage memory 112, 512: first inverter 113, 515: first pre-adder 114: first selector 115, 518: First post-stage adder 514: First pre-stage selector 517: First post-stage selector 122, 522: Second inverter 123, 525: Second pre-stage adder 124: Second selector 125, 528: Second post-stage adder 126 , 526: second delay device 524: second pre-stage selector 527: second post-stage selector 132, 532: third inverter 133, 535: third pre-stage adder 134: third selector 135, 538: third post-stage adder 136 , 536: third delay unit 534: third pre-stage selector 537: third post-stage selector 14, 54: pre-filter 15, 55: oversample encoder Y1, Y2, Y3: output signal

Claims (8)

a prefilter for bandlimiting the analog signal;
an oversample encoder that quantizes the band-limited analog signal and outputs a digital signal;
a digital filter coefficient storage memory that stores a plurality of digital filter coefficients;
a first inverter receiving a first inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
a first pre-adder that outputs an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
a first selector that outputs the first selector input filter coefficient selected from the inverse addition first filter coefficient or the plurality of digital filter coefficients based on the digital signal;
An analog-to-digital conversion circuit. further comprising the first post-adder that outputs the output of the first selector as the output of the first post-adder;
2. The analog-to-digital conversion circuit according to claim 1. a second delay device for delaying the digital signal;
a second inverter receiving a second inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted second filter coefficient obtained by inverting the second inverter input filter coefficient;
a second pre-adder that outputs an inverted addition second filter coefficient obtained by adding +1 to the inverted second filter coefficient;
a second filter coefficient for outputting a second selector input filter coefficient selected from the inversion addition second filter coefficient or the plurality of digital filter coefficients based on the digital signal delayed by the second delay device; a selector;
a second post-adder that adds the output of the second selector and the output of the first post-adder;
further comprising
3. The analog-to-digital conversion circuit according to claim 2. a third delay device for further delaying the digital signal delayed by the second delay device;
a third inverter receiving a third inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted third filter coefficient obtained by inverting the third inverter input filter coefficient;
a third pre-adder that outputs an inverted addition third filter coefficient obtained by adding +1 to the inverted third filter coefficient;
a third for outputting the third selector input filter coefficient selected from the inversion addition third filter coefficient or the plurality of digital filter coefficients based on the digital signal delayed by the third delay device; a selector;
a third post-adder that adds the output of the third selector and the output of the second post-adder;
further comprising
4. The analog-to-digital conversion circuit according to claim 3. wherein the oversampled encoder is noise shaping;
5. The analog-to-digital conversion circuit according to claim 1. Equipped with an analog-to-digital conversion circuit that converts analog signals to digital signals,
The analog-to-digital conversion circuit is
a prefilter for bandlimiting the analog signal;
an oversample encoder that quantizes the band-limited analog signal and outputs a digital signal;
a digital filter that performs arithmetic processing on the digital signal,
The digital filter is
a digital filter coefficient storage memory that stores a plurality of digital filter coefficients;
a first inverter receiving a first inverter input filter coefficient selected from the plurality of digital filter coefficients and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
a first pre-adder that outputs an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
a first selector that outputs the first selector input filter coefficient selected from the inverse addition first filter coefficient or the plurality of digital filter coefficients, based on the digital signal;
Analog-to-digital converter. band limiting an analog signal;
quantizing the band-limited analog signal and outputting a digital signal;
storing a plurality of digital filter coefficients;
receiving a first inverter input filter coefficient selected from among the plurality of digital filter coefficients, and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
outputting an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
outputting the inverse addition first filter coefficient or a first selector input filter coefficient selected from among the plurality of digital filter coefficients based on the digital signal;
An analog-to-digital conversion method comprising: band limiting an analog signal;
quantizing the band-limited analog signal and outputting a digital signal;
storing a plurality of digital filter coefficients;
receiving a first inverter input filter coefficient selected from among the plurality of digital filter coefficients, and outputting an inverted first filter coefficient obtained by inverting the first inverter input filter coefficient;
outputting an inverted addition first filter coefficient obtained by adding +1 to the inverted first filter coefficient;
outputting the inverse addition first filter coefficient or a first selector input filter coefficient selected from among the plurality of digital filter coefficients based on the digital signal;
A program that makes a computer run

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