JPH03228283A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To clear a memory at a high speed and with small power consumption without increasing the chip size, the bit line capacity, etc., by providing a means which controls the activation of the 1st and 2nd internal control signals with a 1st external input signal and the output signal of a 1st latch circuit. CONSTITUTION:A sense amplifier part (a) is provided together with a memory cell part (b), a bit line balance part (c), a timing generator (d), and a row decod er (f). The generator (d) is provided with a D type flip-flop 30, a NOR gate 34, the OR gates 32 and 33, the delay circuits 35 and 36, and an AND gate 31. Then a 1st latch circuit 31 fetches a 1st external input signal, the inverse of RAS and the logic level of a 2nd external input signal phiEXT at the reset edge of the 1st input signal, the inverse of RAS. Then the control of activation is applied to the 1st and 2nd internal control signals phia and phip by means of the 1st external signal, the inverse of RAS and the output signal phi1 of the circuit 31. Thus it is possible to clear a memory at a high speed and with small power consumption without increasing the chip size and the bit line capac ity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a high-speed clearing function of memory cell data.

[Conventional technology]

When a semiconductor memory is used as an image memory, it is necessary to change all the data in the memory cells to a certain logic state, that is, logic "o" or logic "1" when clearing the screen, and this rewrite time takes a long time. is affecting the image drawing speed. Therefore, it is desired to speed up the rewriting of data in memory (hereinafter referred to as memory clear).

FIG. 6 shows a circuit diagram of a semiconductor memory having a memory clear function for explaining such a conventional example. 6th
In the figure, this conventional example includes a sense amplifier section a, a memory cell section, a bit line balance section C, and a clear data loading section e for bit lines.

The sense amplifier section a includes a P-channel MOS transistor 1
, 2, 5.6 and N-channel MO8) Runsistor 3, 4
, 7.8, and an inverter 9. Memory cell section Suba, N channel MO8) Run transistors 10, 12, 14 .
16 and a capacity of 11°13.15.17. Bit line balance section C is N-channel MO8) transistor 1
It has 8°19.20, 21, 22.23. The clear data load section e is an N-channel MO8) run sister 24
, 25, 26, 27 and an inverter 28. The operation will be explained below using the timing chart shown in FIG.

In FIGS. 6 and 7, control signals ① and φext are signals for controlling the memory from the outside. Control signal φ
, 8, is captured at the falling edge of the control signal ■. In this case, when the signal ■ falls, the signal φ,. When the level of , is high (“High”), it is a memory clear cycle, and when it is low (“Low”), it is a normal write/read (Write/Read) cycle. The bit line is precharged to the reference potential v,at via the MOS transistors 19 and 20 by the bit line balance signal φ2 before the signal 2 is activated.

After the signal ① is activated and the signal φ is set, the word line WLI selected by the external address data is activated. After that, the clear data load section φ is activated, and the bit line signal BL/BL and the clear data φ are activated. /T
c are connected via MOS) run transistors 24 and 25, respectively. Clear data φ. is set in advance and sets the data to be written to the bit line. A sense amplifier activation signal φ is activated after a certain period of time after the selected word line signal WLI is activated, and clear data is written into the selected memory cells 11 and 15.

[Problem to be solved by the invention]

The conventional semiconductor device with memory clear function mentioned above (-!
J C. In order to achieve the memory clear function, it is necessary to provide a clear data loading section e to the bit line, as shown in FIG. For this reason, there are drawbacks such as an increase in cost due to an increase in the semiconductor chip area and a decrease in sense margin due to an increase in human line capacitance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory which solves the above-mentioned drawbacks and allows memory clearing to be performed at high speed and with low power consumption without increasing the semiconductor chip area or bit line capacitance.

[Means to solve the problem]

In the configuration of the present invention, memory cells are arranged at each intersection of a plurality of word lines and a plurality of bit lines, and a first internal control signal controls the connection between each bit line and an output node of a reference potential generation circuit. In a semiconductor memory having a plurality of transistors and a plurality of sense amplifiers arranged for each bit line pair whose activation is controlled by a second internal control signal, a first external input signal and the first input signal The first input signal takes in the logic level of the second external input signal at the reset edge of the first input signal.
A latch circuit, and means for controlling the activation of the first and second internal control signals based on the first external input signal and the output signal of the first latch circuit. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory according to an embodiment of the present invention. In FIG. 1, the semiconductor memory of this embodiment includes a sense antenna 7'' section a and a memory cell section.

It is configured to include a bit line balance section C, a timing generator d, and a row decoder f. The timing generator d is a timing generator that receives the memory cell array section and the external control signals ① and φ08 as inputs, and generates an internal control signal. As an example of the timing generator d in FIG. 1, a logic circuit diagram thereof is shown in FIG. In FIG. 2, timing generator d includes a D-type flip-flop 30. NOR game) 34. OR gate 32.33, delay circuit 35°36
, AND gate 31. Signal φ, EiR'A
S is input, and the signal φ2. Outputs φ,, φWL.

Hereinafter, FIG. 1 will be explained using the timing diagram of FIG. 3 as well. In FIG. 3, switching between the normal write/read cycle and the memory clear cycle is determined by the rising edge of the external control signal (2). In this example, ■The level of the external control signal φext at the rising edge is °'High''
When , the next cycle will be a memory clear cycle, and conversely, when it is Low', the next cycle will be a normal write/read cycle. During the memory clear cycle, the internal flag signal φ1 is activated, and after the signal πXX reset, the bit line balance signal φ is kept in the reset state and the sense amplifier activation signal φ1 is kept in the activated state. Therefore, data read or written in the previous cycle is latched by the sense amplifier and remains on the bit line.

In the memory clear cycle, after the signal ■ is activated, the load line signal WL2 selected by the external address or internal refresh counter output is activated, and the data latched in the previous cycle is written into the capacity 13.17 of the selected memory cell. .

Similarly, by selecting all word lines, all memory cell data can be cleared at high speed.

When the signal πAS rises, the signal φ,. By setting the level to Low, the internal flag signal φ1 is reset, and after the signal ① is reset, the bit line balance signal φ is activated and the sense amplifier activation signal φ is also set. As a result, the bit line signal BL/100 is transmitted to the reference signal V1. ．． is tangent to, and is in a state of balance.

FIG. 4 is a logic circuit diagram showing a timing generator of a semiconductor memory according to another embodiment of the present invention.

This embodiment has the timing generator d' of FIG. 4, and is otherwise the same as that of FIG. 1. In FIG. 4, this timing generator d' includes a D-type flip-flop 40 and an AN
D Kate 41. NOR gate 42. OR Kate 43. Delay circuits 44 and 45 are provided. FIG. 5 is a timing diagram showing the operation of this embodiment. 4 and 5, in this embodiment, during the memory clear cycle, after the signal ① is reset, only the bit line balance signal φ remains in the reset state, and the sense amplifier activation signal φ remains in the reset state.

has been reset. Even in such a state, the data of the previous cycle can be held in a high impedance state by maintaining the bit line in the set state with the signal φ. Generally, the human line capacitance is about 5 to 10 times larger than the memory cell capacitance, so during the next memory clear cycle, the data of the previous cycle is refreshed by activation of the sense amplifier. As a result, the data of the previous cycle is written into the capacitance 13.17 of the selected memory cell, as in the previous embodiment. This embodiment has the advantage that when clearing the memory, it is only necessary to control the bit line balance signal φP, and the control system can be simplified.

〔Effect of the invention〕

As explained above, the semiconductor memory of the present invention achieves memory clearing by controlling the bit line balance signal and the sense amplifier activation signal. There is no need to provide it in the cell array section, which has the effect of reducing the amount of increase in chip size and bit line capacitance to zero. Further, the present invention has the effect that power consumption and peak current can be reduced and speed can be increased because there is no need to charge and discharge the power line during a memory clear cycle.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the timing generator of FIG. 1, FIG. 3 is a timing diagram showing the operation of FIG. 1, and FIG. The figures are a circuit diagram showing a semiconductor memory according to another embodiment of the invention, FIG. 5 is a timing diagram showing the operation of another embodiment of the invention, FIG. 6 is a circuit diagram showing a conventional semiconductor memory, and FIG. The figure is a timing diagram showing the operation of FIG. 6. a...Sense amplifier section, b...Memory cell section, C...Bit line balance section, d...
...Timing generator, e...Clear data load section, 1 to 8 degrees 18 to 27...Mo 10. 12. 14. 16°S transistor, 9, 28... 13.15.17... Capacity, flip-flop. Inverter, 11°30.40...

Claims (2)

[Claims] (1) A memory cell is arranged at each intersection of a plurality of word lines and a plurality of bit lines, and a plurality of transistors control the connection between each bit line and the output node of the reference potential generation circuit using a first internal control signal. and a first external input signal and a reset edge of the first input signal in a semiconductor memory having a plurality of sense amplifiers arranged for each bit line pair whose activation is controlled by a second internal control signal. And the second
a first latch circuit that takes in the logic level of an external input signal, and controls the activation of the first and second internal control signals by the first external input signal and the output signal of the first latch circuit. What is claimed is: 1. A semiconductor memory characterized in that it is provided with means for performing. (2) The semiconductor memory according to claim (1), wherein the first external input signal is a control signal (2).