JPH03227529A - Semiconductor device structure using gaas - Google Patents
Semiconductor device structure using gaasInfo
- Publication number
- JPH03227529A JPH03227529A JP2411290A JP2411290A JPH03227529A JP H03227529 A JPH03227529 A JP H03227529A JP 2411290 A JP2411290 A JP 2411290A JP 2411290 A JP2411290 A JP 2411290A JP H03227529 A JPH03227529 A JP H03227529A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- barrier
- type
- amorphous
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＧａＡｓを材料に用いた半導体デバイスの構
造、更に詳しくはショットキ障壁の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor device using GaAs as a material, and more particularly to the structure of a Schottky barrier.
（従来の技術）
ＧａＡｓを材料に用いたＭＥＳＦＥＴ（金属・半導体接
合電界トランジスタ）は、従来、（１００）基板上に作
成されてきたが、（ｉｏｏ）基板にはトランジスタ特性
がゲート方向によって変わってしまうという難点がある
。基板方位として（１００）の代わりに（１１１）を用
いることによりこの問題が解消されうろことは、すでに
指摘されている（Ｋ、 Ｕｅｎｏ （上野）他、アイ・
イ町ディーーエム予稿集（Ｔｅｃｈｎｉｃａｌ Ｄｉｇ
ｅｓｔ ｏｆ ＩＥＤＭ） １９８８（Ｓａｎ Ｆｒａ
ｎｃｉｓｃｏ）８４６）、この異方性の解消はＭＥＳＦ
ＥＴの集積化において大きな利点となる。(Prior art) MESFETs (metal-semiconductor junction field transistors) using GaAs as a material have conventionally been fabricated on (100) substrates, but (ioo) substrates have transistor characteristics that vary depending on the gate direction. There is a problem with storing it away. It has already been pointed out that this problem can be solved by using (111) instead of (100) as the substrate orientation (K, Ueno et al., I.
Technical Dig Proceedings
est of IEDM) 1988 (San Fra
ncisco) 846), this anisotropy can be resolved by MESF
This is a great advantage in ET integration.
（発明が解決しようとする課題）
一方、ＭＥＳＦＥＴ製作においては、ショットキ障壁を
高くすることが望まれる。しかし、ＧａＡｓ（１１１）
面と金属との界面に形成されるショットキ障壁に関する
知見は少ない。(Problems to be Solved by the Invention) On the other hand, in MESFET manufacturing, it is desired to increase the Schottky barrier. However, GaAs(111)
There is little knowledge regarding the Schottky barrier formed at the interface between a surface and a metal.
本発明の目的は、ＧａＡｓ（１１１）基板上に高い障壁
高（バリアハイド）を持つショットキ障壁を形成するた
めの半導体デバイス構造を提供することである。An object of the present invention is to provide a semiconductor device structure for forming a Schottky barrier with a high barrier height (barrier hide) on a GaAs (111) substrate.
（課題を解決するための手段）
本発明では、高い障壁高を持つショットキ障壁を形成す
るため、ｎ型ＧａＡｓ（１１１）Ａ面上にｐ型アモルフ
ァスＳｉ薄層を堆積した構造を作製する。ｐ型ドーパン
トとしてはＢ、 ＡＩ、 Ｇａなどが考えられる。(Means for Solving the Problems) In the present invention, in order to form a Schottky barrier with a high barrier height, a structure in which a p-type amorphous Si thin layer is deposited on an n-type GaAs (111) A plane is fabricated. Possible p-type dopants include B, AI, and Ga.
ＧａＡｓを構成する元素であるＧａをドープすると耐熱
性が向上する。Doping Ga, which is an element constituting GaAs, improves heat resistance.
（作用）
２種の（１１１）面のうちＡ面（Ｇａ）を用いることに
より、界面過剰Ａｓの生成を抑制する。ｎ型ＧａＡｓ表
面のショットキ障壁の形成に関して、確定的な機構の理
解はなされていないが、界面過剰Ａｓは高い障壁を実現
する上で障害となると考えられる。本発明では、さらに
、（１１１）Ａ面上にアモルファスＳｉ薄層を形成する
。アモルファスＳｉ薄層の形成により、過剰Ａｓの生成
はさらに抑制され、ショットキ障壁の耐熱性を高めるこ
とが可能になる。Ｓｌは、結晶性にした場合には障壁の
耐熱性が劣るのでアモルファスとした。アモルファスＳ
ｉ薄層をｐ型とすることによりショットキ障壁が高くな
ることは、本発明者の実験により見出された事実である
。この機構としては、界面でのｐｎ接合形成、アモルフ
ァスＳｉ中のアクセプター準位によるＧａＡｓ表面ポテ
ンシャルのピンニング等が考えられる。また、ＱａＡｓ
上に直接電極金属を堆積するのではないため、電極金属
堆積によるＧａＡｓ表面の欠陥生成が抑制されることも
、本発明の有効性につながっていると考えられる。(Function) By using the A-plane (Ga) of the two types of (111) planes, the generation of excess As at the interface is suppressed. Regarding the formation of a Schottky barrier on the n-type GaAs surface, the mechanism is not definitively understood, but excess As at the interface is considered to be an obstacle to realizing a high barrier. In the present invention, an amorphous Si thin layer is further formed on the (111)A plane. Formation of the amorphous Si thin layer further suppresses the generation of excess As, making it possible to improve the heat resistance of the Schottky barrier. Since the heat resistance of the barrier would be poor if Sl was made crystalline, it was made amorphous. Amorphous S
It is a fact discovered through experiments by the present inventors that the Schottky barrier becomes higher by making the i-thin layer p-type. Possible mechanisms for this include formation of a pn junction at the interface and pinning of the GaAs surface potential due to acceptor levels in amorphous Si. Also, QaAs
Since the electrode metal is not directly deposited on the GaAs surface, the generation of defects on the GaAs surface due to the electrode metal deposition is suppressed, which is also thought to contribute to the effectiveness of the present invention.
また、アモルファスＳｉ薄層にＧａをドープすると、Ｇ
ａＡｓからのＧａ拡散、積層構造の界面の熱的劣化が抑
制されて耐熱性が向上すると考えられる。Also, when doping Ga into an amorphous Si thin layer, G
It is thought that heat resistance is improved by suppressing Ga diffusion from aAs and thermal deterioration of the interface of the laminated structure.
（実施例）
本実施例においては、ＬＰＥ（液相エピタキシャル成長
）法によりｎ＋基板上に成長した（１１１）Ａｎ型Ｇａ
Ａｓ層（キャリア濃度ｎ＝２Ｘ１０１７ｃｍ−３）を用
いた。洗浄、化学的エツチング後、ＧａＡｓ基板をＣＶ
Ｄ（化学気相成長）反応管に導入した。ＣＶＤ装置はＨ
２圧０．１気圧で運転され、基板温度制御はカーボンサ
セプタの誘導加熱によって行われた。Ｈ２中で基板を５
００°Ｃに昇温し、５ｉ２Ｈ６（ジシラン）およびＢ２
Ｈ６（ジボラン）を供給してｐ型アモルファスＳｉ層（
不純物濃度３ Ｘ １０１９１０ｌ９を２ｎｍ形成した
。(Example) In this example, (111) An-type Ga grown on an n+ substrate by LPE (liquid phase epitaxial growth) method
An As layer (carrier concentration n=2×10 17 cm −3 ) was used. After cleaning and chemical etching, CV
D (chemical vapor deposition) was introduced into a reaction tube. CVD equipment is H
It was operated at 2 pressures and 0.1 atm, and the substrate temperature was controlled by induction heating of the carbon susceptor. 5. Place the substrate in H2
5i2H6 (disilane) and B2
H6 (diborane) is supplied to form a p-type amorphous Si layer (
An impurity concentration of 3×101910l9 was formed to a thickness of 2 nm.
アモルファスＳｉ層を堆積した基板に、ＷＳｉｘ（けい
化タングステン）を１１００ｎ厚スパッタ蒸着し、イオ
ンエツチングにより４００ｐｍ径の円形電極を形成した
。裏面にＡｕＧｅを蒸着し４５０°Ｃで基板をアニール
して、オーミック接触を形成した。ショットキダイオー
ドの電流−電圧特性から求めた接合の障壁高は０．９６
ｅＶであり、ｐ型アモルファスＳｉ層を含まない場合（
０，８７ｅＶ）に対し向上が認められた。On the substrate on which the amorphous Si layer was deposited, WSix (tungsten silicide) was sputter-deposited to a thickness of 1100 nm, and a circular electrode with a diameter of 400 pm was formed by ion etching. AuGe was deposited on the backside and the substrate was annealed at 450°C to form an ohmic contact. The junction barrier height determined from the current-voltage characteristics of the Schottky diode is 0.96.
eV and does not include a p-type amorphous Si layer (
0.87 eV).
ドーパントとしてＡ１を用いる場合は上述のＢ２Ｈ６の
代ワリにＴＭＡ（）リメチルアルミニウム）を用いて同
様にｐ型アモルファスＳｉ層（不純物濃度Ｉ Ｘ １０
’ｃｍ−３） ｔ ２ｎｍ形成する。Ｂをドープした場
合と同様にして接合を形成して障壁高さを測定したとこ
ろ、Ｂの場合と同じ＜ ０．９６ｅＶであり向上が認め
。When A1 is used as a dopant, TMA (remethylaluminum) is used in place of B2H6 mentioned above, and a p-type amorphous Si layer (impurity concentration I x 10
'cm-3) t 2nm is formed. When a junction was formed in the same manner as when B was doped and the barrier height was measured, it was <0.96 eV, the same as in the case of B, indicating an improvement.
られな。Rarena.
またドーパントとしてＧａを用いる場合は上述のＢ２Ｈ
５の代わりにＴＭＧ（）リメチルガリウム）を用いて同
様にｐ型アモルファスＳｉ層（不純物濃度２刈０１９ｃ
ｍ−３）を２ｎｍ形成する。Ｂをドープした場合と同様
にして接合を形成して障壁高さを測定したところ０．９
７ｅＶであり向上が認められた。耐熱性評価のため、Ｎ
２Ｈ４（ヒドラジン）・ＴＭＡ（トリメチルアルミニウ
ム）を原料とするＣＶＤ法によりＡＩＮ（窒化アルミニ
ウム）表面保護膜を３５０°Ｃで１１００ｎ堆積し、Ｈ
２中５００°Ｃから８５０°Ｃにおいて２０分間熱処理
を行った。熱処理後ＡＩＮ膜をＨＦ（弗酸）で除去し、
ショットキダイオードの電流−電圧特性を測定した。シ
ョットキ障壁高の劣化は７００°Ｃまでは認められず、
７５０’Ｃにおいて０．８０ｅＶとなった。この障壁高
が０．８０ｅＶまで劣化する温度は、アモルファスＭへ
のドープ原子種をＡＩ（アルミニウム）、Ｂ（はう素）
等にした他の場合にくらべ５０’Ｃ以上高くなった。In addition, when using Ga as a dopant, the above-mentioned B2H
Similarly, a p-type amorphous Si layer (impurity concentration 2, 019c
m-3) with a thickness of 2 nm. When a junction was formed and the barrier height was measured in the same manner as when B was doped, it was 0.9.
It was 7 eV, and an improvement was recognized. For heat resistance evaluation, N
A 1100 nm AIN (aluminum nitride) surface protective film was deposited at 350°C by the CVD method using 2H4 (hydrazine) and TMA (trimethylaluminum) as raw materials, and H
Heat treatment was performed at 500°C to 850°C for 20 minutes in No. 2. After heat treatment, remove the AIN film with HF (hydrofluoric acid),
The current-voltage characteristics of a Schottky diode were measured. No deterioration of Schottky barrier height was observed up to 700°C.
It became 0.80 eV at 750'C. The temperature at which this barrier height deteriorates to 0.80 eV is the temperature at which the doping atomic species to amorphous M are AI (aluminum) and B (boron).
The temperature was more than 50'C higher than in other cases where the temperature was set to 1.
上記３つの実施例では、高融点金属でありＭＥＳＦＥＴ
の自己整合形成のため一般に用いられているという理由
でＷＳｉｘを用いたが、ｐ型アモルファスＳｉ層形成に
よるショットキ障壁高の改善は、ＷＮ−（ｍ化タングス
テン）、Ａ１等の電極金属に対しても認められた。これ
により、本発明が電極金属種に依らないことは明らかで
ある。In the above three embodiments, the high melting point metal is MESFET.
WSix was used because it is commonly used for the self-aligned formation of a p-type amorphous Si layer. was also recognized. From this, it is clear that the present invention does not depend on the type of electrode metal.
（発明の効果）
本発明により、高い障壁高を持つショットキ障壁をＧａ
Ａｓ（１１１）基板上に形成することができ、例えばＧ
ａＡｓ（１１１）基板上のＭＥＳＦＥＴの動作向上が可
能になる。(Effect of the invention) According to the present invention, a Schottky barrier with a high barrier height can be
It can be formed on an As(111) substrate, for example, G
It becomes possible to improve the operation of MESFETs on aAs (111) substrates.
Claims (1)
ｉ薄層を形成した半導体デバイス構造。p-type amorphous S on n-type GaAs(111)_A surface
Semiconductor device structure with i thin layer formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2411290A JPH03227529A (en) | 1990-02-01 | 1990-02-01 | Semiconductor device structure using gaas |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2411290A JPH03227529A (en) | 1990-02-01 | 1990-02-01 | Semiconductor device structure using gaas |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03227529A true JPH03227529A (en) | 1991-10-08 |
Family
ID=12129247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2411290A Pending JPH03227529A (en) | 1990-02-01 | 1990-02-01 | Semiconductor device structure using gaas |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03227529A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182574A (en) * | 1983-04-01 | 1984-10-17 | Nippon Telegr & Teleph Corp <Ntt> | Field-effect transistor |
| JPS61129878A (en) * | 1984-11-29 | 1986-06-17 | Fujitsu Ltd | Semiconductor device |
-
1990
- 1990-02-01 JP JP2411290A patent/JPH03227529A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182574A (en) * | 1983-04-01 | 1984-10-17 | Nippon Telegr & Teleph Corp <Ntt> | Field-effect transistor |
| JPS61129878A (en) * | 1984-11-29 | 1986-06-17 | Fujitsu Ltd | Semiconductor device |
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