JPH03225845A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPH03225845A
JPH03225845A JP2020250A JP2025090A JPH03225845A JP H03225845 A JPH03225845 A JP H03225845A JP 2020250 A JP2020250 A JP 2020250A JP 2025090 A JP2025090 A JP 2025090A JP H03225845 A JPH03225845 A JP H03225845A
Authority
JP
Japan
Prior art keywords
terminal
lsi
floating
state
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020250A
Other languages
Japanese (ja)
Inventor
Hiroyuki Miyazaki
浩行 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2020250A priority Critical patent/JPH03225845A/en
Publication of JPH03225845A publication Critical patent/JPH03225845A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a floating state without removing an integrated circuit such as an LSI from a substrate by bundling enable input terminals from each buffer into one terminal for forming a floating terminal and then by controlling this floating terminal. CONSTITUTION:A three-state control buffer part 5 is connected to an output part 4 within an LSI 1, it is at Low level normally within the LSI 1, and it performs normal operation when the power is turned on. A floating terminal 7 is set to High level through a cable 12 of an emulator connector 9 to set a floating state. Thus, each enable input of a three-state control buffer 6 at the buffer part 5 is set to High level and an output terminal 8b of the LSI 1 is in floating state. Thus, by setting the floating terminal 7 to High level, operation of the LSI 1, etc., can be turned into insulation state easily, thereby enabling operation check, etc., of a hardware to be performed without removing the LSI 1, etc.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はLSI等の集積回路に関する。[Detailed description of the invention] Industrial applications The present invention relates to integrated circuits such as LSIs.

従来の技術 近年、半導体技術の進歩は目ざましく、AV機器、OA
機器、HA機器等の分野における小型高性能で低価格の
ハイテク商品が続々と登場している。これらハイテク商
品の実現を可能としたのがLSI等の集積回路である。
Conventional technology In recent years, advances in semiconductor technology have been remarkable, and AV equipment, OA
Small, high-performance, low-priced high-tech products in the field of equipment, HA equipment, etc. are appearing one after another. Integrated circuits such as LSIs have made it possible to realize these high-tech products.

従来、この種のLSIは、他の電子部品とともに基板上
に実装されて使用され、VCC端子やGND端子に電圧
を付加することにより無条件で動作状態になるように設
計されていた。
Conventionally, this type of LSI has been used by being mounted on a board together with other electronic components, and has been designed to become operational unconditionally by applying a voltage to a VCC terminal or a GND terminal.

発明が解決しようとする課題 しかしながら、このようなLSIでは、ハードウェアの
動作チエツク等でLSIを絶縁状態にしたい場合、その
LSIを基板上から取り除くかまたは電源端子を遮断し
なければ絶縁状態にすることができないという問題があ
った。さらに、ハードウェア上のCPU等と同じ動作を
するエミュレータを接続する場合、基板上からCPUを
取り外さなければならないという問題があった。
Problems to be Solved by the Invention However, in such an LSI, when it is desired to make the LSI in an insulated state for checking the operation of the hardware, etc., the LSI must be removed from the board or the power supply terminal must be cut off to make it in the insulated state. The problem was that I couldn't do it. Furthermore, when connecting an emulator that operates in the same way as a CPU on the hardware, there is a problem in that the CPU must be removed from the board.

本発明はこのような従来の問題を解決するものであり、
LSI等の集積回路を基板上から取り外さずにフローテ
ィング状態にすることのできる優れた集積回路を提供す
ることを目的とするものである。
The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent integrated circuit that can be placed in a floating state without removing the integrated circuit such as an LSI from a substrate.

課題を解決するための手段 本発明は前記目的を達成するために、LSI等の集積回
路内部の各出力部にスリーステート制御バッファを設け
るとともに、各スリーステート制御バッファの各イネー
ブル入力を−っにまとめてフローティング端子としたも
のである。
Means for Solving the Problems In order to achieve the above object, the present invention provides a three-state control buffer at each output section inside an integrated circuit such as an LSI, and also connects each enable input of each three-state control buffer to -. They are collectively used as floating terminals.

作用 したがって、本発明によれば、フローティング端子をH
ighレベルにすることによって、LSI等の動作を容
易に絶縁状態にする二とができ、ハードウェアの動作チ
エツク等をLSl等を取り除かずに行なうことができる
という効果を有する。
Operation Therefore, according to the present invention, the floating terminal is
By setting it to the high level, the operation of the LSI etc. can be easily brought into an insulated state, and the operation of the hardware can be checked without removing the LSI etc., which is advantageous.

実施例 第1図は本発明の一実施例の構成を示すものである。第
1図において、■はLSIであり、2はLS11内部の
入力部、3は一1?a部、4は出力部である。5はLS
ll内部の出力信号を制(社)するスリーステート制御
バッフ76を備えたバッフ7部である。7は各スリース
テート制都バッファ6の各イネーブル人力を−っにまと
めてバッファ部5を制御することによりフローティング
状態にするフローティング端子である。8aは入力端子
、8bは出力端子である。
Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, ■ is an LSI, 2 is an input section inside LS11, and 3 is -1? Section a, 4, is an output section. 5 is LS
The buffer section 7 includes a three-state control buffer 76 that controls the output signal inside the ll. Reference numeral 7 designates a floating terminal which collects each enable force of each three-state capital control buffer 6 into a floating state by controlling the buffer unit 5. 8a is an input terminal, and 8b is an output terminal.

フローティング端子7は、第2図に示すようにLSI1
の上部中央部に設けられており、このフローティング端
子7に、ICE(インサーキットエミュレータ)のコネ
クタ9が上から被せられて接続される。そしてフローテ
ィング端子7をHighレヘル(5V)にすることによ
りLSllはフローティング状態となる。
The floating terminal 7 is connected to the LSI 1 as shown in FIG.
A connector 9 of an ICE (in-circuit emulator) is placed over the floating terminal 7 and connected to the floating terminal 7 . Then, by setting the floating terminal 7 to High level (5V), LSll becomes a floating state.

次に前記実施例における接続方法について説明する。第
3図に示すように、LSIIは基板10上に取り付けら
れている。そしてこのLSIIの上部にエミュレータコ
ネクタ9を被せる。エミュレータコネクタ9の裏面には
、LSllのフローティング端子7に接続可能なフロー
ティング接続ピン11が設けられており、この接続ピン
11をLSIIのフローティング端子7に接続した後、
ケーブル12を通じて70−テインク端子7をH1gh
レベルにすることにより、LSllはその出力端子8b
から出力信号を出力せず、絶縁状態となる。なお、エミ
ュレータコネクタ9の裏面側部内側にはピン接触端子1
3がLSIIの各入出力端子ピン8に接触するようにな
っている。
Next, the connection method in the above embodiment will be explained. As shown in FIG. 3, the LSII is mounted on a substrate 10. Then, the emulator connector 9 is placed on top of this LSII. A floating connection pin 11 that can be connected to the floating terminal 7 of LSII is provided on the back side of the emulator connector 9. After connecting this connection pin 11 to the floating terminal 7 of LSII,
Connect the 70-teink terminal 7 to H1gh through the cable 12.
By setting the LSll to its output terminal 8b
It does not output any output signal and becomes insulated. Note that there is a pin contact terminal 1 on the inside of the back side of the emulator connector 9.
3 comes into contact with each input/output terminal pin 8 of the LSII.

次に前記実施例の動作について説明する。LS11内部
の出力部4にはスリーステート制御バッファ部5が接続
されており、通常はLS11内部でLowレベルになっ
ており、電圧投入時に通常動作を行なう。フローティン
グ状態にする場合は、エミュレータコネクタ9のケーブ
ル12を通じてフローティング端子7をHighレベル
にすることにより、バッファ部5のスリーステート制御
バッファ6の各イネーブル入力がHighになり、LS
rlの出力端子8bが70−ティング状態となる。
Next, the operation of the above embodiment will be explained. A three-state control buffer section 5 is connected to the output section 4 inside the LS 11, and is normally at a low level inside the LS 11, and performs normal operation when the voltage is turned on. To set the floating state, by setting the floating terminal 7 to High level through the cable 12 of the emulator connector 9, each enable input of the three-state control buffer 6 of the buffer unit 5 becomes High, and the LS
The rl output terminal 8b is in the 70-ting state.

このように、前記実施例によれば、LSIIに70−テ
ィング端子7を設けることにより、LSI出力信号を容
易にフローティング状態にすることができる。このため
、ハードウェアの動作チエツク等で出力信号どうしが重
なっている場合など、各LSIを順次70−ティング状
態にすることによって、どのLSIの信号が原因なのか
を見極めることができる。さらに、ハードウェア上のC
PU等と同じ動作をするエミュレータを接続スる場合、
基板10上のCPUを外さずに+5vのフローティング
接続ピン11を持つエミュレータコネクタ9をLSll
に被せることにより、LSllをフローティング状態に
させ、エミュレータを通して仮想動作を行なわせること
ができるという利点を有する。
As described above, according to the embodiment, by providing the 70-ting terminal 7 in the LSII, the LSI output signal can be easily brought into a floating state. Therefore, when output signals overlap each other due to a hardware operation check, etc., by sequentially setting each LSI to the 70-ting state, it is possible to determine which LSI's signal is the cause. Furthermore, C on the hardware
When connecting an emulator that operates in the same way as a PU, etc.,
Connect the emulator connector 9 with +5V floating connection pin 11 to LSll without removing the CPU on the board 10.
This has the advantage that the LSll can be placed in a floating state and virtual operations can be performed through an emulator.

発明の効果 本発明は前記実施例から明らかなように、集積回路内部
の各出力部にスリーステート制御バッファを設け、これ
ら各バッファのイネーブル入力を一つの端子にまとめて
フローティング端子としたので、このフローティング端
子を制御することにより、基板上からLSI等の集積回
路を取り外さずにフローティング状態にすることができ
ると第1図は本発明の一実施例におけるLSIの概略ブ
ロック図、第2図は同LSIとエミュレータコネクタの
外観斜視図、第3図は同LSIとエミュレータコネクタ
との接続例を示す概略断面図である。
Effects of the Invention As is clear from the embodiments described above, the present invention provides three-state control buffers at each output section inside the integrated circuit, and combines the enable inputs of these buffers into one terminal as a floating terminal. By controlling the floating terminals, integrated circuits such as LSIs can be placed in a floating state without removing them from the substrate. Fig. 1 is a schematic block diagram of an LSI according to an embodiment of the present invention, and Fig. 2 is the same. FIG. 3 is a perspective view of the external appearance of the LSI and the emulator connector, and FIG. 3 is a schematic cross-sectional view showing an example of the connection between the LSI and the emulator connector.

1・・・LSI、2・・・入力部、3・・・制御部、4
・・・出力部、5・・・スリーステート制御バッファ部
、6・・・スリーステート制御バッファ、7・・・70
−ティング端子、8・・・入出力端子ピン、8a・・・
入力端子、8b・・・出力端子、9・・・エミュレータ
コネクタ、10・・・基板、11・・・フローティング
接続ピン、12・・・ケーブル、13・・・ピン接触端
子。
1... LSI, 2... Input section, 3... Control section, 4
... Output section, 5... Three-state control buffer section, 6... Three-state control buffer, 7... 70
-Ting terminal, 8... Input/output terminal pin, 8a...
Input terminal, 8b... Output terminal, 9... Emulator connector, 10... Board, 11... Floating connection pin, 12... Cable, 13... Pin contact terminal.

Claims (1)

【特許請求の範囲】[Claims] 集積回路内部の各出力部にスリーステート制御バッファ
を設け、前記各スリーステート制御バッファの各イネー
ブル入力を一つの端子にまとめてフローティング端子と
し、前記フローティング端子を制御することにより制御
動作を絶縁状態可能とした集積回路。
A three-state control buffer is provided in each output section within the integrated circuit, each enable input of each of the three-state control buffers is combined into one terminal as a floating terminal, and control operations can be isolated by controlling the floating terminal. integrated circuit.
JP2020250A 1990-01-30 1990-01-30 Integrated circuit Pending JPH03225845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020250A JPH03225845A (en) 1990-01-30 1990-01-30 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020250A JPH03225845A (en) 1990-01-30 1990-01-30 Integrated circuit

Publications (1)

Publication Number Publication Date
JPH03225845A true JPH03225845A (en) 1991-10-04

Family

ID=12021953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020250A Pending JPH03225845A (en) 1990-01-30 1990-01-30 Integrated circuit

Country Status (1)

Country Link
JP (1) JPH03225845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09145793A (en) * 1995-11-27 1997-06-06 Nec Corp Surface mount type semiconductor integrated circuit device and socket for connecting emulator socket to it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09145793A (en) * 1995-11-27 1997-06-06 Nec Corp Surface mount type semiconductor integrated circuit device and socket for connecting emulator socket to it

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