JPH03224052A - Data transfer system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time by providing a state reading part and a direct memory access controller DMAC and ordering the state reading part to always read the transfer preparatory state of an input/output part with hardware and to perform the DMA transfer of data. CONSTITUTION:A state reading part 6 starts with a start instruction given from a computer (CPU) and always reads the transfer preparatory state of an input/output part 4 with hardware. Then the part 6 sends a DMA request signal to a DMAC 5 when reading a fact that the preparation is completed for transfer of n-bit data. Thus the DMAC 5 detects the request signal and performs the DMA transfer of data between the part 4 and a memory part 3. When this transfer is through, the DMAC 5 sends a transfer end signal to the part 6. Both the part 6 and the DMAC 5 repeat these operations to repeat the DMA transfer of data. Then the part 6 informs the CPU of the end of the transfer when it reads a fact that the transfer of all data is over. Then the CPU ends the operation of the part 6. Thus the data transfer time is shortened.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a data transfer method used when image data is processed and transferred at high speed, the transfer data is written and read in order to shorten the data transfer time. The memory section and n bits of data to be transferred are written.

An input device including a status register that stores a data memory section to be read, a first status indicating whether the data memory section is ready for transfer, and a second status indicating whether the final data has been transferred. A data transfer comprising an output section and a control section for controlling operations of necessary parts, and transferring data between the memory section and the input/output section until the second status indicates final data transfer. In the method, data is transmitted between a status reading unit that always automatically reads a first status and a second status stored in the status register and performs corresponding processing, the memory unit, and the input/output unit. A DMAC is provided to control the transfer.
Each time the status reading unit determines that the read first status is ready for transfer, the status reading unit reads the DMAC.
A DMA request signal is sent to the DMAC, and upon detecting the DMA request signal, the DMAC is configured to transfer data between the memory section and the input/output section.

[Industrial application field]

The present invention relates to, for example, a data transfer method used when image data is processed and transferred at high speed.

In recent years, there has been a demand for large amounts of data, such as image data, to be processed at high speed by an input/output unit and transferred to a memory unit, and along with this, it is necessary to shorten the data transfer time.

[Conventional technology]

FIG. 6 is a block diagram of a conventional example, FIG. 7 is an explanatory diagram of the operation of FIG. This shows the case where data is transferred from the section to the input/output section. The operation shown in FIG. 6 will be explained below with reference to FIG.

(1) Data transfer from the input/output section to the memory section First, the input/output section (hereinafter abbreviated as 10) 13 is provided with a status register 131 and a data memory 132. The former stores status A indicating whether data to be transferred has been written to the data memory, and status B indicating whether the transferred data is the final data.

Then, when status A is "1", there is data to be transferred,
It is assumed that when the status B is "0", there is no transferred data, when the status B is "1", it is the final data, and when the status B is "O", it is not the final data. It is also assumed that data transfer is performed every 8 bits.

Now, after the computer (hereinafter abbreviated as CPU) 11 sends a data transfer request to the I10 section 13, it checks the status of the status register 131 in order to check whether or not this 110 section is ready for transfer. Read A.

When status A is "1", it is in a readable state, so the CPU reads the 8-bit data stored in the data memory, temporarily stores it in an internal memory (not shown), and then transfers this data over the data bus. Memory part 1 through
Write to the predetermined address part of 2. However, when the status A is "0", data transfer is not possible yet, so the process returns to the state immediately after the start (see FIG. 7(a)-------).

If the CPU reads out the status B and it is "0", there is still data to be transferred, so it repeats the same operation as above and transfers the data stored in the data memo January 32 to the memory section 12. Forward. However, when the status B becomes "1", all data has been transferred, and the CPU ends the data transfer operation (see Figure 7(a)).
-See ■, ■).

(2) Data transfer from memory section to 110 section CPU is I
After sending a data transfer request to the 10 section 13, the status A of the status register in the 110 section is read. If the status A is "0", it is in a writable state, so data is read from the memory section and written to the data memo 32 in section 110 via the data bus (Fig. 7(b)-■ to [ F]).

The CPU repeatedly transfers data from the memory section to the 110 section, but ends the data transfer operation when the status B becomes "1" (see FIG. 7(b)-@).

[Invention or problem to be solved]

When the CPU transfers data between the memory section and the 110 section, as shown in FIG. 7(a)-■ and FIG. 7(b)-■, each time the CPU transfers 8-bit data, After taking out the data and checking whether it is ready for transfer, the data is sent to the transfer destination via the data bus.
There is a problem that data transfer takes time.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 3 is a memory section to which transfer data is written and read, 4 is a data memory section to which n-bit data to be transferred is written and read, and whether the data memory section is ready for transfer. It is an input/output unit including a status register that stores a first status indicating whether the final data has been transferred, and a second status indicating whether or not the final data has been transferred, and 2 is a control unit that controls operations of necessary parts.

In addition, 6 is the first value stored in the status register.
5 is a status reading unit that always automatically reads the status of the first status and the second status and performs corresponding processing, and 5 is a DM that controls data transfer between the memory unit and the input/output unit.
It is AC.

Each time the status reading unit determines that the read first status is ready for transfer, it sends a DMA request signal to the DMAC, and the DMAC sends a DMA request signal to the DMAC.
When the MA request signal is detected, data transfer is performed between the memory section and the input/output section.

[Effect]

The present invention is based on the first data stored in the status register. A status reading unit and a DMAC are provided to automatically read the second status and perform corresponding processing.

This status reading section is activated by a startup command from the CPU,
The transfer preparation state of the input/output unit is always read by hardware, and when it is read that the transfer preparation for n bits of data is completed, a DMA request signal is sent to the DMAC.

The DMAC detects this request signal, performs DMA transfer of data between the memory section and the input/output section, and when the transfer is completed, sends a transfer end signal to the status reading section.

The status reading unit and DMAC repeat the above operations to repeat the DMA transfer of data, but when the former reads that all data transfer has been completed, it notifies the CPU of the completion of the transfer, and the CPU reads the status reading unit’s DMA transfer. Terminate the operation.

That is, a status reading unit and a DMAC are provided, and the former reads the transfer preparation status of the input/output unit using hardware, and when the transfer preparation is completed, the data to be transferred is transferred to the DMA.
Since data is transferred, data transfer time is shortened.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of the status reading section in FIG. 2, FIG. 4 is an explanatory diagram of the operation of FIG. 2, and FIG. D to the memory section
When performing MA transfer, see Figure 4 (bl is 110 from the memory section).
This is a case of DMA transfer to a portion.

Here, the CPU 21 is a component of the control unit 2, switches 42, 43 . The transmitting/receiving buffer 44.110 part 41 is a component part of the input/output section 4, the status reading part 61, the status determining part 62. A DRQ signal generation section 63 shows a component of the status reading section 6. Incidentally, statuses A and B correspond to the first claims. Corresponds to the second status.

Also, the same reference numerals indicate the same objects throughout the figures. Hereinafter, the operation of FIG. 2 will be explained with reference to FIGS. 3 and 4, assuming that data is transferred by DMA every 8 bits.

Note that the switches 42 and 43 are normally in the solid line state, so the status reading section 6 is not used, and data transfer between the memory section 3 and the section 110 is performed under the control of the CPU (contrary to the conventional example). same).

(1) DMA transfer from section 110 to memory section First, the CPU 21 activates the status reading section 6 and the DMAC 5. Therefore, the status reading section 61 in the status reading section shown in FIG. ) is read and sent to the status determination unit 62.

Since the status A is "1", the status determination unit knows that the transfer preparation is complete, and sends a DMA request signal (hereinafter abbreviated as DRQ signal) requesting DMA transfer to the DMAC 5 (4th (a) −■～■).

Therefore, the DMAC 5 obtains the right to use the common bus from the CPU 2 and transfers 8 bits of data from the 110 section to the memory section 3 via the transmission/reception buffer 44, but when the transfer is completed, it sends a transfer end signal (ACK). ) is sent to the status reading section 6.

When the status reading unit receives ACK, it repeats the above operation again, but when it learns that status B has become “1”, it notifies the CPU 21 that the data transfer has ended, and
The PU 21 stops the operation of the status reading unit (see FIG. 4(a)-■ and ■).

(2) DMA transfer from memory section to section 110 This DM
The A transfer operation is performed in the same manner as in section (1), but since data is transferred from the memory section to the section 110, the status reading section 6 reads the DMAC 5 when the status A stored in the status register 41I is "0". The DRQ signal is sent to

As a result, 8 bits of the data written in the memory section to be transferred are transferred to the data memory 412 (see FIG. 4(b)----@).

Thereafter, the DMA transfer is repeated in the same way as in item (1), and once all the data has been transferred, the CPU stops the operation of the status reading section.

Next, FIG. 5 is a block diagram of another embodiment.
In the figure, the DMAC performs 8-bit DMA transfer, but in the case of FIG. 5, 16-bit DMA transfer is performed. In addition, the capacity of data memo 1J411 in part 110 is the second
Both FIG. 5 and FIG. 5 are 8 bits.

(3) DMA transfer from section 110 to memory section Now, the status reading section 6 reads the status A stored in the status register 411 in the same way as above, and since it indicates that the transfer preparation is complete, it sends a DRQ signal to the DMAC. At the same time, send a data transfer command to the data memory,
The 8-bit data is read out from here and latched into the buffer 48 as the lower 8 bits.

When it learns that the status A is ready for the second transfer, it reads out 8-bit data from the data memory and sends it to the buffer 46. Therefore, DM
AC5 transfers 16 bits of data including the 8 bits latched in buffer 48 to memory 3. When the transfer is completed, an ACK is sent from the DMAC 5 to the status reading unit 6.
The same operation as above is repeated.

(4) When the DMA transfer status reading unit 6 from the memory section to the 110 section learns that the I10 section is ready for transfer, it sends a DRQ signal to the DMAC, so the (8+8) bits are transferred from the memory section. The upper 8 bits are transferred to the data memory 412 in the 110th section via the buffer 45, while the lower 8 bits are latched into the buffer 47.

Therefore, the status reading section transfers the lower 8 bits to the data buffer the next time transfer preparation is completed. In this case, 16 bits are transferred to the common bus, so the common bus occupancy rate is % compared to items (1) and (2).

Here, the common bus exclusive time in the case of item (3) is the period from the time when the status reading section recognizes the completion of the first transfer preparation and sends out the DRQ signal until the end of the 16-bit transfer. However, if the status reading unit sends the DRQ signal when it learns that the preparation for the second transfer is complete, the exclusive time of the common bus can be further reduced.

The advantage of reducing the exclusive time of the common bus increases as the amount of data to be transferred increases.

That is, a status reading section and a DMAC are provided so that the former always reads the transfer preparation state of the input/output section using hardware, and the data to be transferred is transferred by DMA, so that the data transfer time is shortened.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that data transfer time can be shortened.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of the status reading section in Fig. 2, and Fig. 4 is a block diagram of the embodiment of the present invention. 2 is an explanatory diagram of the operation, FIG. 5 is a block diagram of another embodiment of the present invention, FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an explanatory diagram of the operation of FIG. 6. In the figure, 2 is a control section, 3 is a memory section, 4 is an input/output section, 5 is a direct memory access controller, and 6 is a status reading section. Fig. 70.17 of the cold cultivation example of the present invention Fig. 2 Aronoff diagram of most of moxibustion diagrams Conventional example of flow / blade Z diagram (α) ('0) Figure 6 explanatory picture

Claims (1)

[Claims] Memory unit (3) into which transfer data is written and read out.
and a data memory section into which n bits (n is a positive integer) of data to be transferred are written and read, a first status indicating whether the data memory section is ready for transfer, and final data. an input/output unit (4) that includes a status register that stores a second status indicating whether or not the data has been transferred; and a control unit (2) that controls the operations of necessary parts.
and a data transfer method in which data is transferred between the memory unit and the input/output unit until the second status indicates final data transfer, the first status stored in the status register a status reading unit (6) that always automatically reads the status and the second status and performs corresponding processing; and a direct controller that controls data transfer between the memory unit and the input/output unit.
A memory access controller (5) is provided, and each time the status reading unit determines that the read first status is ready for transfer, the status reading unit sends a message to the direct memory access controller (DMAC). A direct memory access request signal (DMA request signal) is sent, and when the direct memory access controller detects the direct memory access request signal, it transfers data between the memory section and the input/output section. A data transfer method characterized by allowing data transfer to occur.