JPH03223106A - Method for etching si - Google Patents
Method for etching siInfo
- Publication number
- JPH03223106A JPH03223106A JP1487690A JP1487690A JPH03223106A JP H03223106 A JPH03223106 A JP H03223106A JP 1487690 A JP1487690 A JP 1487690A JP 1487690 A JP1487690 A JP 1487690A JP H03223106 A JPH03223106 A JP H03223106A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- etching
- porous layer
- time
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000002253 acid Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000003487 electrochemical reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- JVJQPDTXIALXOG-UHFFFAOYSA-N nitryl fluoride Chemical compound [O-][N+](F)=O JVJQPDTXIALXOG-UHFFFAOYSA-N 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Silicon Compounds (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えばＳｉ（シリコン）ダイヤフラムの形
成などに好ましく用いることができるＳＬのエツチング
方法に間する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of etching SL, which can be preferably used, for example, for forming a Si (silicon) diaphragm.
従来、Ｓｉダイヤフラムを作るエツチング方法としてケ
ミカルエツチングがある。このケミカルエツチングは化
学反応によってＳｉをエツチングするものである。Conventionally, chemical etching has been used as an etching method for producing Si diaphragms. This chemical etching etches Si through a chemical reaction.
上記のような従来のＳｉのエツチング方法は化学反応に
よるものであるため、時間がかかるという問題点があっ
た。また用いる液体の濃度等の変化によってエツチング
の厚さにばらつきが生じ、厚さの制御が難しいという問
題点があった。Since the conventional Si etching method as described above is based on a chemical reaction, it has the problem of being time consuming. Furthermore, there is a problem in that the etching thickness varies due to changes in the concentration of the liquid used, making it difficult to control the thickness.
この発明はこのような従来技術の問題を解消するために
なされたもので、エツチングの時間を短縮した制御の容
易なＳｉのエツチング方法を得ることを目的とする。The present invention has been made to solve the problems of the prior art, and aims to provide a Si etching method that shortens the etching time and is easy to control.
この発明に係るＳｉのエツチング方法は、Ｓｉ基板に多
孔質層を形成した後、エツチングするように構成したも
のである。The Si etching method according to the present invention is configured such that a porous layer is formed on a Si substrate and then etched.
この発明における多孔質層はＳｉ基板の表面より基板の
厚さ方向に形成され、その後のＳｉのエツチングを容易
にし、エツチングに要する時間を短縮する。The porous layer in this invention is formed from the surface of the Si substrate in the thickness direction of the substrate to facilitate subsequent etching of Si and shorten the time required for etching.
以下、この発明の一実施例としてｐ−３ｉダイヤフラム
形成におけるＳｉのエツチングについて図を参照して説
明する。Hereinafter, as an embodiment of the present invention, etching of Si in forming a p-3i diaphragm will be explained with reference to the drawings.
第１図において、（１）はｐ−Ｓｉ基板、（２）はこの
Ｓｉ基板（１）の表面に形成された不溶性の窒化膜、（
３）はＳｉ窓であり、Ｓｉ基板（１）の表面を露出させ
た部分である。In FIG. 1, (1) is a p-Si substrate, (2) is an insoluble nitride film formed on the surface of this Si substrate (1), (
3) is a Si window, which is a portion where the surface of the Si substrate (1) is exposed.
第２図は第１図のＳｉ基板（１）の所定部に多孔質層を
形成する装置を説明する図である。Ｓｉ基板（１）には
電極（図示省略）がモールドされている。（４）はｐｔ
電極、（５）は直流電源、（６）は容器、（７）はフッ
酸水溶液である。なお、この実施例においてはフッ酸の
濃度は約４９％、温度は２０〜３０℃とした。FIG. 2 is a diagram illustrating an apparatus for forming a porous layer on a predetermined portion of the Si substrate (1) of FIG. 1. Electrodes (not shown) are molded on the Si substrate (1). (4) is pt.
The electrode, (5) is a DC power supply, (6) is a container, and (7) is a hydrofluoric acid aqueous solution. In this example, the concentration of hydrofluoric acid was approximately 49%, and the temperature was 20 to 30°C.
第２図の装置において、電流密度１０〜１００―＾／Ｃ
ｌＩ２の電流を４〜６０分間通流し、Ｓｉ基板（１）の
窓（３）に多孔質層（８）を形成した。このとき、電流
密度と時間の関係については一例として、深さ３０μｍ
の多孔質層の孔を形成するのに１００−＾／Ｃｌ１２の
とき４分程度、５０ｍ＾／ ｃ ｍ ２のとき９分程度
であった。また、時間と孔の深さとの関係については、
−例として電流密度５０ｍＡ／ｃｍ２のとき、９分で約
３０ａｍ、２０分で約６０μｍ、６０分で約１００μｍ
の多孔質層が形成された。In the device shown in Figure 2, the current density is 10 to 100-^/C.
A current of lI2 was passed for 4 to 60 minutes to form a porous layer (8) in the window (3) of the Si substrate (1). At this time, as an example, the relationship between current density and time is as follows:
It took about 4 minutes to form pores in the porous layer at 100-^/Cl12 and about 9 minutes at 50 m^/cm2. Also, regarding the relationship between time and hole depth,
- For example, when the current density is 50 mA/cm2, about 30 am in 9 minutes, about 60 μm in 20 minutes, and about 100 μm in 60 minutes
A porous layer was formed.
このようにしてＳｉ基板に形成された多孔質層は基板の
厚さ方向に形成される。なお、電流の大小によって後で
述べるダイヤフラムの形成を速くしたり遅くしたりでき
る。The porous layer thus formed on the Si substrate is formed in the thickness direction of the substrate. Note that the formation of the diaphragm, which will be described later, can be made faster or slower by changing the magnitude of the current.
次に多孔質層を形成したＳｉｔ極からモールド電極をは
ずし、そして窒化膜をとりのぞいたものが第３図である
。Ｓｉ基板（１）上にＳｉ多孔質層（８）が形成された
状態となっている。Next, the molded electrode was removed from the Sit electrode on which the porous layer was formed, and the nitride film was removed, as shown in FIG. A Si porous layer (8) is now formed on the Si substrate (1).
第４図は上記のように多孔質層（８）を形成したＳｉ基
板（１）をフッ硝酸溶液に浸漬し、多孔質層をエツチン
グする状態を示す説明図である。図において、（９）は
エツチングのためのフッ硝酸溶液、（１０）はエツチン
グによって形成されたダイヤフラム部である。FIG. 4 is an explanatory diagram showing a state in which the Si substrate (1) on which the porous layer (8) is formed as described above is immersed in a fluoro-nitric acid solution and the porous layer is etched. In the figure, (9) is a fluoro-nitric acid solution for etching, and (10) is a diaphragm portion formed by etching.
なお、フッ酸と硝酸の混合比は約１：３〜１：５の範囲
で行った。Note that the mixing ratio of hydrofluoric acid and nitric acid was in the range of approximately 1:3 to 1:5.
第５図は上記した一連の工程を概念的に示した説明図で
ある。第５図（ａ＞はＳｉ基板（１）の横断面図、第５
図（ｂ）は第２図の装置によりＳｉ基板（１）に多孔質
層を形成した状態を説明する断面図である。多孔質層（
８）はＳｉ基板（１）の結晶軸に関係なく基板（１）の
厚さ方向に形成される。FIG. 5 is an explanatory diagram conceptually showing the series of steps described above. Figure 5 (a> is a cross-sectional view of the Si substrate (1),
Figure (b) is a cross-sectional view illustrating a state in which a porous layer is formed on a Si substrate (1) using the apparatus shown in Figure 2. Porous layer (
8) is formed in the thickness direction of the Si substrate (1) regardless of the crystal axis of the Si substrate (1).
第５図（ｃ）は第４図のエツチングにより除去される部
分を示す断面図であり、図の破線部分が除去される。第
５図（ｄ）はエツチング後の状態を説明する断面図であ
る。FIG. 5(c) is a cross-sectional view showing the portion removed by etching in FIG. 4, and the broken line portion in the figure is removed. FIG. 5(d) is a sectional view illustrating the state after etching.
上記のようにこの発明の実施例によれば電気化学反応に
よって、強制的に基板の厚さ方向に深い孔を形成した後
、多孔質層の山（凸部）をエツチングする方法なので、
結果的にみれば結晶軸の違いを無視するかの如く基板の
厚さ方向のみにエツチングできる。従って、従来の方法
に比ベエッチングの処理時間を短くすることができる。As described above, according to the embodiment of the present invention, deep holes are forcibly formed in the thickness direction of the substrate by electrochemical reaction, and then the peaks (projections) of the porous layer are etched.
As a result, etching can be performed only in the thickness direction of the substrate, as if ignoring the difference in crystal axes. Therefore, the etching time can be reduced compared to conventional methods.
なお、上記実施例では多孔質層の形成とエツチングを各
１回ずつ行ったが、これらを２回以上繰り返してもよい
。電気化学反応によって形成された多孔質層の孔の深さ
と時間とは比例せず、形成される孔の深さに対する所要
時間は指数関数的に増えるので、上記のように操作を反
復することは時間を短縮する上で好ましいことである。In the above example, the formation of the porous layer and the etching were performed once each, but these steps may be repeated two or more times. The depth of the pores in the porous layer formed by the electrochemical reaction is not proportional to the time, and the time required for the depth of the pores formed increases exponentially, so it is not possible to repeat the operation as described above. This is preferable in terms of reducing time.
また、エツチングにフッ硝酸を用いたが、例えばフッ硝
酢酸、王水、フッ酸など他の混酸、酸を用いても差し支
えない、混酸を用いる場合、その混合比は特に限定され
ない、さらに、電流密度、酸の濃度、時間、温度などを
適宜変更し得ることは言うまでもない。これらファクタ
ーの１つまたは２以上を制御することによりエツチング
の厚さを任意に制御することができる。In addition, although fluoronitric acid was used for etching, other mixed acids and acids such as fluoronitric acid, aqua regia, and hydrofluoric acid may also be used. When a mixed acid is used, the mixing ratio is not particularly limited. It goes without saying that the density, acid concentration, time, temperature, etc. can be changed as appropriate. By controlling one or more of these factors, the etching thickness can be controlled as desired.
例えば電流と時間を制御することでエツチングの厚さ（
多孔質層の厚さと同等）を制御できる。For example, by controlling the current and time, the etching thickness (
(equivalent to the thickness of the porous layer) can be controlled.
エツチング制御つまりエツチングするＳｉの厚さの制御
方法はＳｉ電極に流れる電流と電流を流した時間とで多
孔質層の厚さを設定し、フッ硝酸でエツチングする方法
である。このＳｉ電極に流れる電流の大小によって反応
を速くしたり遅くしたりできるのでダイヤフラムの形成
を速くすることができる。Etching control, that is, a method for controlling the thickness of Si to be etched, is to set the thickness of the porous layer by the current flowing through the Si electrode and the time for which the current is passed, and then etching with hydrofluoric nitric acid. Since the reaction can be made faster or slower depending on the magnitude of the current flowing through the Si electrode, the formation of the diaphragm can be made faster.
このようなこの発明のＳｉのエツチング方法は、特にＳ
ｉダイヤフラム形成におけるＳＬのエツチングに好まし
く用いることができる。The Si etching method of the present invention is particularly suitable for etching S
It can be preferably used for etching SL in forming an i-diaphragm.
ところで、上記実施例ではｐ−３ｉのときを述べたが、
ｎ−３ｉの場合は通電時に光を照射するとよい、また、
上記実施例ではＳｉダイヤフラム形成のＳｉエツチング
についても述べたが、ＩＣや機能デバイスのＳｉエツチ
ングに用いてもよい。By the way, in the above example, the case of p-3i was described, but
In the case of n-3i, it is recommended to irradiate light when energizing, and
In the above embodiment, Si etching for forming a Si diaphragm was also described, but it may also be used for Si etching for ICs and functional devices.
以上のようにこの発明によれば、８１基板に多孔質層を
形成した後、エツチングするように構成したので、エツ
チングの時間を短縮した制電の容易なＳｉのエツチング
方法を得ることができるという効果がある。As described above, according to the present invention, since the porous layer is formed on the 81 substrate and then etched, it is possible to obtain a Si etching method that shortens the etching time and easily suppresses static electricity. effective.
第１図〜第５図は何れもこの発明の一実施例を説明する
図であり、第１図は一実施例に用いるＳｉ基板を示す平
面図、第２図はＳｉ多孔質層を形成するための装置の概
要図、第３図はＳｉ多孔質層を形成したＳｉ基板の平面
図、第４図はＳｉ多孔質層をエツチングする装置を示す
側面図、第５図は一連の工程による８１基板へのダイヤ
フラムの形成を示す説明図である。
図において、（１）はＳｉ基板、（８） ハｓ ｉ 多
孔質層、（１０）はダイヤフラム部である。
なお、図中、同一符号は同一、又は相当部分を示す。1 to 5 are diagrams explaining one embodiment of the present invention, in which FIG. 1 is a plan view showing a Si substrate used in one embodiment, and FIG. 2 is a plan view showing a Si porous layer formed thereon. 3 is a plan view of a Si substrate with a porous Si layer formed thereon, FIG. 4 is a side view showing the device for etching the porous Si layer, and FIG. It is an explanatory view showing formation of a diaphragm on a substrate. In the figure, (1) is a Si substrate, (8) is a Si porous layer, and (10) is a diaphragm part. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
を特徴とするＳｉのエッチング方法。A method for etching Si, which comprises forming a porous layer on a Si substrate and then etching it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1487690A JPH03223106A (en) | 1990-01-26 | 1990-01-26 | Method for etching si |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1487690A JPH03223106A (en) | 1990-01-26 | 1990-01-26 | Method for etching si |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03223106A true JPH03223106A (en) | 1991-10-02 |
Family
ID=11873217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1487690A Pending JPH03223106A (en) | 1990-01-26 | 1990-01-26 | Method for etching si |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03223106A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1179842A3 (en) * | 1992-01-31 | 2002-09-04 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
-
1990
- 1990-01-26 JP JP1487690A patent/JPH03223106A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1179842A3 (en) * | 1992-01-31 | 2002-09-04 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
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