JPH0322300A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To test a redundant memory cell at the same timing as the time of normal memory cell selection by controlling an redundant relief address detecting means by an external signal and switching selection from a normal memory cell array to a redundant memory cell array. CONSTITUTION:The inverse of an external control signal CE is made active and an internal signal phi is activated. At such a time, when an external control signal A is set to 'H', an internal signal R is forcibly set to the 'H' level even in case a fuse in a redundant address detecting circuit 7 is not cut. Thus, an internal signal phiR is set to the 'H' level by a selector 5 and a redundant memory cell array 2 is selected. Accordingly, even when the fuse in the circuit 7 is not cut, the redundant memory cell can be tested at the same timing as the time of the normal memory cell selection.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device having redundant memory cells.

2. Description of the Related Art In recent years, the capacity of semiconductor memory devices has increased, and memory cell arrays within chips have also become extremely dense and highly integrated. In addition, when there is a defective memory cell in a chip, a method is frequently used to salvage the chip as a good product by switching to a redundant memory cell prepared in advance in the chip. This method is called the ``redundancy relief method'').

One of the redundancy relief methods is to use a ROM using a fuse as a redundancy relief address detection circuit. This is a method in which an address corresponding to a defective bit in a memory cell array is stored by cutting a fuse, and when that address is selected, the selected memory cell is switched to a redundant memory cell.

Problems to be Solved by the Invention As mentioned above, when fuses are used as redundant relief address detection circuits, there has been a conventional problem in that in order to use redundant memory cells, it is necessary to use fuses in the redundant address detection circuits. At this time, if there is even one bit of defective cell in the redundant memory cell, the fuse cannot be salvaged as a good chip even if the fuse is cut, and the fuse cutting process is wasted. There was a problem that the process would be complicated.

The present invention solves the above-mentioned conventional problems, and can forcibly switch from a normal memory cell to a redundant memory cell by simply applying an external signal without cutting the fuse in the redundant address detection circuit. An object of the present invention is to provide a semiconductor memory device capable of performing a test on a redundant memory cell at the same timing as a normal memory operation.

Means for Solving the Problems In order to achieve this object, the semiconductor memory device of the present invention controls the redundant relief address detection circuit by the output of the address buffer (internal address signal) and a second external control signal. The output is used as a control signal for a selector, and in the selector, a first internal signal for driving an address decoder for normal memory cell selection and a second internal signal for redundant memory cell array selection are generated by a driving signal from a clock generator. It has a structure for switching.

Effect With this configuration, the output of the redundant relief address detection circuit can be forcibly controlled by the second external control signal without cutting the fuse in the redundant relief address detection circuit, and the output of the redundant relief address detection circuit can be forcibly controlled by the selector. The selection can be switched from the normal memory cell array to the redundant memory cell array.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 1 is a memory cell array, 2 is a redundant memory cell array, 3 is an address decoder for selecting a specific address within the memory cell array, 4 is an address buffer, 5 is a selector, 6 is a clock generator, and 7 is an address decoder for selecting a specific address within the memory cell array. is a redundant relief address detection circuit,
CE and A are external control signals, and φIRIφ- and φR are internal signals. The operation timing of the semiconductor memory device shown in FIG. 1 is shown in FIGS. 2 to 4.

The operation of the semiconductor memory device of this embodiment configured as described above will be described below.

FIG. 2 shows an example of the timing of normal operation of the semiconductor memory device of the present invention, in which the external control signal A is always “L”.
When the external control signal CE becomes active, the internal signal R becomes the "L" level. When the signal CE becomes active, the internal signal φ is activated by the clock generator 6. At this time, since the internal signal R is at the “L” level, the internal signal φM goes to the “H” level through the selector 5, and the internal signal φR remains at “L” level (
Selector 5 is driven by internal signal φ, and internal signal R
If R is “L” level, use φSagi, and if R is “H” level, use φR.
(set to “H”). When the internal signal φ goes to the "H" level, address decoder 3 selects a specific address in memory cell array 1 and accesses the memory.

Next, FIG. 3 shows the operation when a redundant relief address is programmed by the redundant relief address detection circuit 6. At this time, external control signal A is always at "L" level. As in normal operation, when the external control signal CE becomes active, the internal signal φ goes to the "H" level, but at this time, the external address signal matches the address programmed in the redundancy relief address detection circuit 7. In this case, the internal signal R remains at the "H" level, the internal signal φR is selected through the selector 6, and the redundant memory cell array is selected (operation indicated by the broken line in the timing chart of FIG. 3). If the external address signal does not match the address programmed in the redundancy relief address detection circuit 7, the internal signal K goes to "L" level, and as in normal operation, the selector 5 causes the internal signal φ- to go to "H" level. Then, an access operation for a specific memory cell of the memory cell array 1 is performed (operation indicated by the solid line in FIG. 2).

As described above, the redundant relief address detection circuit 7 and the selector 5 switch a normal memory cell to a redundant memory cell for access.

Further, FIG. 4 shows an operation for forcibly switching a selected memory cell to a redundant memory cell without programming a rescue address into the redundant rescue address detection circuit 7. By activating the external control signal CE, the internal signal φ
is activated, but at this time, by setting the external control signal A to the "H" level, the internal signal R is forced to the "H" level, the internal signal φR becomes the "H" level, and the redundant memory cell is activated. selected.

As described above, the output R of the redundancy relief address detection circuit is forced to the "H" level by the external signal A, and a redundant memory cell can be easily selected.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 5, 1 is a memory cell array, 2 is a redundant memory cell array, 3 is an address decoder, 4 is an address buffer, CE, A are external control signals, φIR+φM, φR are internal signals, and the above is the configuration of FIG. It is similar to Ao=A1,AO
-Ai are mutually contradictory internal address signals.

7 is a redundant relief address detection circuit, and FOI~Fil
and FO2 to Fi2 are redundant relief address program fuses, Qo+ to Q;+. Qo2~Q;2. To + ~
T ; + + T O2 to T ; 2 are N-channel MOSFETs. 71 is a circuit for precharging the internal signal R.

The operation of the semiconductor memory device of this embodiment configured as described above will be described below.

External control signal CE, A, external address manual input Ao~Ai,
The operation timing of internal signal φIRIφ old φR is the same as in FIGS. 2 to 4. The internal signal R is precharged by a precharge circuit 71 in advance.

First, in the normal operation shown in FIG. 2, the external control signal A is at the "L" level, and the FETs Qo+ to Q;z QO2 to Q12 are always on.

Also, the output signal A. of the address buffer 4 is output from the address buffer 4. ~Ai,Ao
-Ai are mutually contradictory signals, TOI and T 0
2 ,"'"'Bear's F of T i I and T i 2
One of the FETs is always on, and the precharged internal signal R becomes “L”.
Discharged to the level. After this, the internal signal φ
When activated, internal signal φ- is activated through selector 5, and address decoder 3 selects a specific address within memory cell array 1.

Next, the operation when the redundant relief address is programmed will be explained (operation shown in FIG. 3).

The redundant relief address program includes FOI and FO2.・
...Fil and F. This is done by cutting one of the two pairs of fuses. When a normal address is selected, the pre-precharged internal signal R is discharged through a series circuit of a fuse and two transistors, and becomes the "L" level. However, when a redundant relief address is selected, the fuse is disconnected. All discharge paths are closed and remain at the "H" level, and when the internal signal φ is activated, it is switched to the internal signal φR by the selector 5, and the redundant memory cell array is selected.

Furthermore, when the external control signal A is set to high level as in the operation shown in FIG. 4, the FETs Qo+ to Q;
, Qo2 to Q;2 are turned off, and the pre-charged internal signal R is kept at "H" level. When the internal signal φ is activated, the internal signal φ is activated by the selector 5.
R is selected, and a redundant memory cell array is selected.

As described above, according to this embodiment, the redundant relief address detection circuit 7 is configured as a series circuit of a fuse and two FETs as shown in FIG. By controlling the redundant memory cell array, the redundant memory cell array can be forcibly selected and the redundant memory cell array can be tested.

Effects of the Invention The present invention controls a redundancy relief address detection circuit by an external control signal, uses the output signal of the redundancy relief address detection circuit as a control signal of a selector, and uses the selector as a signal for selecting a normal memory cell array and a redundancy memory cell array. By switching the configuration, the redundant memory cell array is forcibly selected without cutting the fuse in the redundant relief address detection circuit, and the redundant memory cells are tested at the same timing as when normal memory cells are selected. This makes it possible to realize an excellent semiconductor memory device that can perform the following steps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention, FIGS. 2, 3, and 4 are operation timing diagrams of the semiconductor memory device of FIG. 1, and FIG. 5 is a diagram of the present invention. FIG. 2 is a configuration diagram of a semiconductor memory device in a second embodiment of the present invention. 1...Memory cell array, 2...Redundant memory cell array, 3...Address decoder,
4...address buffer, 5...selector, 6...clock generator, 7...
...Redundant relief address detection circuit, CE, A...
・External control signal, φ old φR. R, φ...Internal signal.

Claims (1)

[Claims] A memory cell array and a redundant memory cell array, an address decoder for selecting a specific address of the memory cell array, an address buffer for latching an external address signal and outputting it to the address decoder, and driving the address decoder. a first internal signal, a second internal signal for selecting the redundant memory cell array, a selector for switching between the first and second internal signals, and a first external control signal. a clock generator for driving the selector;
A semiconductor memory device comprising a redundancy relief address detection circuit for outputting an internal control signal to a selector based on the output of the address buffer and a second external control signal.