JPH03220832A - Clock delivery system - Google Patents

Abstract

PURPOSE:To attain synchronization transmission of a high frequency signal by generating an operating standard clock in an equipment with a high frequency from a synchronization reference clock and allowing each package to generate a high frequency transmission line clock from the operating standard clock in the equipment. CONSTITUTION:An in-equipment operation standard clock generating section 3 receiving a bipolar synchronization reference clock CLKL in 64kHz+8kHz from the outside of the equipment applies 405 multiple to the frequency to generate the in-equipment operating standard clock CLKM in 25.92MHz. The in-equipment operating standard clock CLKM is distributed respectively to plural blocks 5-1-5-N being final distribution destinations through a distribution circuit 4. A PLO section 52 provided in its own package in a transmission line interface block 5-2 sending a data pulse to a 100Mb/s or over of high speed digital transmission line receives the standard block to generate the transmission line clock CLKM at a required maximum frequency such as 155.52XnMHz and gives the clock to a load 53 to apply prescribed data processing.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock distribution method that supplies a high-speed clock to each part of the device in, for example, a digital transmission device, a high-speed clock that is synchronized with a low-speed synchronous reference clock without increasing the hardware cost. In a device with multiple blocks, a high-speed operating clock synchronized with a low-speed synchronous reference clock supplied from outside the device can be supplied to the required locations within the device. In this method, a synchronous reference clock reception section receives a synchronous reference clock from outside the device, and an in-device standard clock generation section synchronizes with the synchronous reference clock and controls data transmission and reception between each block within the device. Generating an internal operating standard clock of the required frequency, distributing the standard clock to the plurality of blocks via a distribution circuit, and transmitting a higher frequency than the standard operating clock within each block as necessary. Configure the computer to run a road clock.

[Industrial application field]

The present invention relates to a clock distribution method for supplying high-speed clocks to various parts of a digital transmission device, for example.

In recent synchronous networks in digital synchronous multiplex communication systems, a low-speed synchronous reference clock (68 KHz + 8 KHz) is distributed from the main station through a Cronk branch.
) is created within the device, but the conventional clock distribution method cannot cope with the increasing speed of the synchronous network, and a new lock distribution method is required.

[Conventional technology]

A multiple transmission line interface package in a digital transmission device requires a synchronized clock equal to the bit rate of the transmission line. Therefore, in conventional devices, a synchronous reference clock receiver receives a reference synchronous clock with a low frequency (64K tz + 8KHz) supplied from the outside, and generates a high-speed synchronous clock signal equal to the pin rate of the high-speed digital transmission line. This was then distributed to the transmission line interface package via a distribution circuit.

The conventional network synchronization system in Japan uses digital quadratic group (6,
312 Mb/s) are synchronized. Therefore, the highest frequency required for the synchronization clock in the transmission device is the frequency corresponding to the above transmission bit rate, and T
Since the operating speed was within the operating speed of the TL logic element, it was possible to distribute without any problem using a distribution circuit using the above general-purpose and inexpensive logic element.

However, SDH (Synchronous Digiea), a newly standardized synchronous interface,
l Hierarchy), the ink face speed is standardized to 156 Mb/s, and the synchronization network is made to have a higher frequency, so the bit rate of the transmission path increases accordingly, and the highest frequency of the synchronization clock required within the transmission equipment is increased. The speed will also be increased to 100M7 order.

[Problem to be solved by the invention]

If you try to distribute a high-speed clock of 100 MHz or more using the conventional clock distribution method, which generates all types of synchronized clocks required in a device in one place and distributes them to the necessary locations, ambient noise in the distribution path will occur. etc., the distributed clock pulse waveform deteriorates, making it impossible to perform correct processing at the end. Furthermore, it is not possible to use a general-purpose logic TTL for transmitting and receiving clocks, and the technology relies on technologies such as ECL, resulting in a rapid increase in power consumption.

In order to prevent the distribution path from being affected by ambient noise, mounting conditions such as sufficiently covering the distribution board with a shield become strict, and the device for transmitting and receiving clock signals requires a high-speed ECL logic element. This results in problems such as increased hard costs and increased power consumption.

The present invention was created in view of the above problems, and it is an object of the present invention to enable a high-speed clock synchronized with a low-speed synchronous reference clock to be supplied to necessary locations within a device without increasing hardware costs.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the clock distribution system of the present invention.

The above problem, as shown in FIG. 1, requires that a high-speed operating clock synchronized with a low-speed synchronization reference clock supplied from outside the device be used in a device having a plurality of blocks 5-1 to 5-N. In this method, the synchronous reference clock receiving section 2 receives the synchronous reference clock CLKL from outside the device, and the internal standard clock generating section 3 receives the synchronous reference clock CLKL from outside the device.
, create an internal operating standard clock CLK that is synchronized with the synchronous reference clock CLKL and has a frequency necessary for data transmission and reception between each block in the device, and
LK, through the distribution circuit 4 to the plurality of blocks 5-
This problem is solved by the clock distribution method of the present invention, which is characterized in that a transmission line clock CLK having a higher frequency than the standard operating clock CLKM is created as necessary within each block. Ru.

[Operation] Since the medium-speed internal operating standard clock CLK is distributed to each block within the device, the distribution circuit 4 can be configured with TTL logic elements, and high-speed logic elements such as ECL, which consumes a large amount of power and are expensive, can be used. do not need.

Furthermore, since the high-speed clock is not distributed, shielding of the distribution circuit, etc. becomes simple, and the mounting conditions are relaxed.

〔Example〕

The present invention will be explained in detail below with reference to the accompanying drawings.

FIG. 2 shows the blocks of the clock distribution system according to the present invention. Note that the symbols are the same as in FIG. 1.

Reference numeral 2 denotes a synchronous reference clock receiving section which receives a 64 KHz+8 kHz bipolar synchronous reference clock CL KL from outside the device and converts it into a TTL level. This output 64KHz TTL level clock signal CLKL?
is input to the internal operating standard clock generation section 3. The in-device operating standard clock creation unit 3 multiplies the frequency by 405 to create an in-device operating standard clock CL of 25.92 MHz.
It consists of a phase-locked oscillator (PLO) 31 that generates K, and an output Halafah gate 32, and outputs the generated internal operation standard clock CLK9 through multiple routes. This internal operating standard clock CLK is a synchronous clock with the minimum necessary frequency for transmitting and receiving data between each block within the device, and must be distributed to each block without phase difference. This internal operating standard clock CLK is distributed to a plurality of blocks 5-1 to 5-N, which are final distribution destinations, through a distribution circuit 4 comprising an input buffer gate 41, an output buffer gate 42, internal wiring, etc. These blocks include the channel switching block (cross connect block) 5-1, which sets channels by exchanging data pulse trains, and the block 5-1 that adds control pulses to data pulse trains and synchronizes them with the transmission line clock to connect digital transmission lines. These are blinks 5-2 and the like for transmission line interfaces for sending out, and each of them is housed in a package. In the channel switching block 5-1, the standard Chromeno C received at the input Halafah gate 51
LK is supplied as it is to the load 54 and used as a synchronization clock. On the other hand, the transmission line ink face block 5-2 that sends data pulses to a high-speed digital transmission line of 100 Mb/s or more requires a high-speed transmission line clock corresponding to this pin rate. The internal operating standard clock received by the device is manually input to the PLO unit 52 provided in the own package to create a transmission line clock CLK of the required highest frequency, for example, 155.52X n MHz, and supply it to the load 53. Predetermined data processing is performed.

In this way, the low-speed synchronous reference clock from outside the device is multiplied by the internal operating standard clock generator into a medium-speed internal operating standard clock, and this standard clock is distributed to multiple blocks within the device, and then For blocks that require high-speed transmission line clocks, each block has an individual PLO and generates a high-speed clock within its own package based on the distributed medium-speed standard clock.
The distribution circuit can be configured using TTL elements that are relatively inexpensive and consume little power, and since the transmission to the blocks is carried out by medium-speed pulses, implementation conditions such as noise countermeasures are eased, reducing equipment costs. It can be avoided.

Since a high-speed clock with the highest frequency is created within the final distribution destination pancage, high-frequency synchronous transmission becomes possible.

〔Effect of the invention〕

As explained above, according to the present invention, the in-device operating standard clock creation section creates a higher frequency in-device operating standard clock from the synchronous reference clock, and distributes this in-device reference clock to the final distribution destination package. However, since each package creates a transmission line clock with a higher frequency than the internal operating standard clock, there is no need to use a high frequency transmission line clock to send and receive clock signals inside the device, and the distribution circuit can be configured using TTL logic elements. It can be configured with relaxed mounting conditions, and even if the transmission line is to be synchronized to a high bit rate in the future, the performance of the transmission equipment can be maintained as it is now, realizing equipment that requires a high-speed synchronized clock. can do.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the clock distribution system of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, l...Digital transmission device, 2...Synchronization reference clock receiving unit, 3...In-device standard clock production unit, 31--PLo, 32--Output buffer gate, 4--Clock distribution. Circuit, 41--Input buffer gate, 42-Output buffer gate, 5-1 to 5-N-Block, 51--Manual buffer gate, 2 PLO. 53--Load, is. Hontaku Hizuki's 70...7 Bamboo Curtain Method 1 loaf Y Rim92
．． The block diagram 1 is also indicated by the clear diagram name (millet distribution 4i date/month 0 Jitsukatamurasaku/J).
2 figure

Claims (1)

[Claims] Device (1) having a plurality of blocks (5-1 to 5-N)
In this method, a high-speed operating clock synchronized with a low-speed synchronous reference clock supplied from outside the device is supplied to the plurality of blocks, wherein the synchronous reference clock receiving section (2) receives the synchronous reference clock from outside the device. (CLK_L) is received, and the in-device standard clock generation unit (3) receives the synchronization reference clock (CLK_L).
internal operating standard clock (CLK_M) that is synchronized with L) and has the frequency necessary for data transmission and reception between each block within the device.
and distribute the standard clock (CLK_M) to the distribution circuit (
4) to the plurality of blocks (5-1 to 5-N), and create a transmission line clock (CLK_M) with a higher frequency than the standard operating clock (CLK_M) as necessary within each block. A clock distribution method that is characterized by: