JPH03220676A - Wiring delay time calculating system - Google Patents
Wiring delay time calculating systemInfo
- Publication number
- JPH03220676A JPH03220676A JP2016872A JP1687290A JPH03220676A JP H03220676 A JPH03220676 A JP H03220676A JP 2016872 A JP2016872 A JP 2016872A JP 1687290 A JP1687290 A JP 1687290A JP H03220676 A JPH03220676 A JP H03220676A
- Authority
- JP
- Japan
- Prior art keywords
- delay time
- calculation
- calculation rule
- wiring
- rule group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004364 calculation method Methods 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 230000010365 information processing Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は情報処理装置を使用したプリント配線板や集積
回路等の配線遅延時間算出方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring delay time calculation method for printed wiring boards, integrated circuits, etc. using an information processing device.
従来の配線遅延時間算出方式は、遅延時間を算出しよう
としている一製品分の配線構成データを構成している配
線の最小構成単位の長さや幅、抵抗値等のデータである
最小構成要素に対応した計算式等の遅延時間算出計算ル
ール（以後、計算ルールと記す〉を含んだ遅延時間算出
用プログラムにより算出されていた。The conventional wiring delay time calculation method corresponds to the minimum component, which is data such as the length, width, resistance value, etc. of the minimum component unit of the wiring that constitutes the wiring configuration data for the one product for which the delay time is to be calculated. The calculation was performed using a delay time calculation program that included delay time calculation calculation rules (hereinafter referred to as calculation rules) such as calculation formulas.
上述した従来の配線遅延時間算出方式は、遅延時間算出
用プログラムが一製品分の配線構成データにのみ対応し
ているので、配線構成データが変る度に計算ルールの対
応を変更して新たな遅延時間算出用プログラムを情報処
理装置に入力しなければならないという問題点がある。In the conventional wiring delay time calculation method described above, the delay time calculation program only supports one product's wiring configuration data, so each time the wiring configuration data changes, the calculation rule correspondence is changed and a new delay is calculated. There is a problem in that the time calculation program must be input into the information processing device.
また、計算ルールの対応を変更して情報処理装置に入力
するには時間がかがるので、新たな遅延時間算出用プロ
グラムによる遅延時間がすぐに算出できないという問題
点がある。Furthermore, since it takes time to change the correspondence of the calculation rules and input them into the information processing apparatus, there is a problem that the delay time cannot be immediately calculated using a new delay time calculation program.
本発明の目的は、遅延時間算出計算ルールの入力が容易
に行え、また新たな遅延時間算出計算ルールで遅延時間
を算出できるまでの期間が短縮できる配線遅延時間算出
方式を提供することにある。An object of the present invention is to provide a wiring delay time calculation method that allows easy input of delay time calculation calculation rules and shortens the period until delay time can be calculated using a new delay time calculation calculation rule.
本発明の配線遅延時間算出方式は、遅延時間の算出対象
となる配線の配線構成データを最小構成要素ごとに記憶
する第１の記憶手段と、前記配線構成データの前記最小
構成要素に対応する単位の遅延時間算出計算ルールの複
数個を計算ルール群として記憶する第２の記憶手段と、
前記計算ルール群を切分ける条件を入力する第１−の手
段と、前記計算ルール群を前記第２の記憶手段がら読出
ず第２の手段と、前記第２の手段が読出した前記計算ル
ール群を前記第１−の手段がらの切分は条件に基づいて
遅延時間算出計算ルールの単位に切分ける第３の手段と
、前記配線構成データを前記第１の記憶手段から読出ず
第４の手段と、前記第３の手段からの前記計算ルールお
よび前記第４の手段からの前記配線構成データに基づい
て配線遅延時間を算出する演算手順（プログラム）を作
成する第５の手段と、前記第５の手段により作成された
前記演算手順に従って配線遅延時間を算出する第６の手
段とを備えて構成されている。The wiring delay time calculation method of the present invention includes a first storage means for storing wiring configuration data for each minimum component of a wiring whose delay time is to be calculated, and a unit corresponding to the minimum component of the wiring configuration data. a second storage means for storing a plurality of delay time calculation calculation rules as a calculation rule group;
a first means for inputting a condition for dividing the calculation rule group; a second means for not reading the calculation rule group from the second storage means; and the calculation rule group read by the second storage means. A third means separates the wiring configuration data from the first storage means into units of delay time calculation rules based on conditions, and a fourth means does not read the wiring configuration data from the first storage means. and a fifth means for creating a calculation procedure (program) for calculating a wiring delay time based on the calculation rule from the third means and the wiring configuration data from the fourth means; and sixth means for calculating the wiring delay time according to the calculation procedure created by the means.
次に、本発明の実施例について図面を参照し説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１−図は本発明の一実施例のブロック図である。同実
施例の情報処理装置は、各種制御や処理を行う制御装置
］−と、磁気ディスク装置やフレキシブルディスク装置
等の記憶装置２，３と、キーボード等の入力装置４とか
ら構成されている。FIG. 1 is a block diagram of an embodiment of the present invention. The information processing apparatus of this embodiment includes a control device for performing various controls and processing, storage devices 2 and 3 such as a magnetic disk device or a flexible disk device, and an input device 4 such as a keyboard.
記憶装置２は遅延時間の算出対象となる配線の配線構成
データ２０を最小構成要素２０ａごとに記憶している。The storage device 2 stores wiring configuration data 20 of the wiring whose delay time is to be calculated for each minimum component 20a.
配線構成データ２０の内容は、アセンブリレベル（ＬＳ
Ｉ、ＭＣＰなど〉などの全体テークと、論理的・物理的
な品種名やりビジョンおよび座標などの部品データと、
信号名や始点および終点のピン名やロケーションやファ
ンクションタグや線長や線種や線材の太さや階層などの
配線データと、端子容量や端子抵抗や層の単位面積当り
の容量や層のシート抵抗などの容量・抵抗データなどで
ある。The contents of the wiring configuration data 20 are assembly level (LS
I, MCP, etc., and parts data such as logical and physical product name, vision, and coordinates,
Wiring data such as signal names, pin names and locations of start and end points, function tags, line lengths, line types, wire thicknesses, and layers, as well as terminal capacitance, terminal resistance, capacitance per unit area of layers, and sheet resistance of layers. Capacitance/resistance data, etc.
記憶装置３は配線構成データ２０を含め、今後遅延時間
を計算するであろうすべての配線の最小構成要素と対応
する単位の複数個の計算ルール３０ａで構成されている
遅延時間算出計算ルール群（以後、計算ルール群と記す
）３０を記憶している。制御装置１−は計算ルール群３
０を切分ける条件を入力する計算ルール群切分は条件入
力手段１１と、計算ルール群３０を計算ルール３０ａに
切分ける計算ルール群切分は手段１３と、配線構成デー
タ２０を記憶装置２から読出す配線情報読出し手段１４
と、計算ルール３０ａと配線構成データ２０から遅延時
間算出用プログラムを作成する遅延時間算出用プログラ
ム作成手段１５と、遅延時間算出用プログラム作成手段
１５が作成したプログラムにより遅延時間を算出する遅
延時間算出手段１６とを有して構成されている。The storage device 3 stores a delay time calculation calculation rule group (including wiring configuration data 20) that is composed of a plurality of calculation rules 30a of units corresponding to the minimum components of all wirings for which delay time will be calculated in the future. 30 (hereinafter referred to as a calculation rule group) are stored. Control device 1- is calculation rule group 3
The calculation rule group separation for inputting the conditions for separating 0 is performed by the condition input means 11, the calculation rule group separation for dividing the calculation rule group 30 into calculation rules 30a is performed by the means 13, and the wiring configuration data 20 is sent from the storage device 2. Wiring information reading means 14 to read
, a delay time calculation program creation means 15 that creates a delay time calculation program from the calculation rule 30a and the wiring configuration data 20; and a delay time calculation that calculates the delay time using the program created by the delay time calculation program creation means 15. means 16.
遅延時間を算出する場合は、入力装置４から配線構成デ
ータ２０の最小構成要素２０ａに対応した配線種や端子
数などから成る計算ルール群切分は条件を計算ルール群
切分は条件入力手段１１により人力する。次に、計算ル
ール群読出し手段１２が記憶装置３より計算ルール群３
０を読出す。計算ルール群切分は条件と計算ルール群３
０とから計算ルール群切分は手段１３が、計算ルール群
３０を計算ルール３０ａに切分ける。配線情報読出し手
段１４が記憶装置２から配線構成データ２０を読出し、
遅延時間算出用プログラム作成手段１−５が配線構成デ
ータ２０と計算ルール３０ａとから遅延時間算出用プロ
グラムを作成する。When calculating the delay time, input means 11 inputs the conditions for dividing the calculation rule group consisting of the wiring type, the number of terminals, etc. corresponding to the minimum component 20a of the wiring configuration data 20 from the input device 4. More human power. Next, the calculation rule group reading means 12 reads the calculation rule group 3 from the storage device 3.
Read 0. Calculation rule group separation is condition and calculation rule group 3
The calculation rule group division means 13 divides the calculation rule group 30 into calculation rules 30a from 0. The wiring information reading means 14 reads the wiring configuration data 20 from the storage device 2,
The delay time calculation program creation means 1-5 creates a delay time calculation program from the wiring configuration data 20 and the calculation rule 30a.
遅延時間算出手段Ｌ６が遅延時間算出用プログラム作成
手段１５が作成した遅延時間算出用プログラムで遅延時
間を算出する。The delay time calculation means L6 calculates the delay time using the delay time calculation program created by the delay time calculation program creation means 15.
なお、同実施例では配線構成データ２０と遅延時間算出
計算ルール群３０とは２つの記憶装置に分けて記憶され
ているが、記憶装置に能力があれば１一つの記憶装置に
両方とも記憶させることも可能である。Note that in the same embodiment, the wiring configuration data 20 and the delay time calculation rule group 30 are stored separately in two storage devices, but if the storage device has the capacity, both can be stored in one storage device. It is also possible.
また、同実施例では遅延時間算出プログラムの作成から
遅延時間の計算まで１台の情報処理装置で行っているが
、１台の情報処理装置で遅延時間算出プログラムを作成
し、オンラインまたはフレキシブルディスク等の記憶媒
体による移動により他の情報処理装置で遅延時間を算出
することも可能である。In addition, in the same embodiment, one information processing device performs everything from creating the delay time calculation program to calculating the delay time, but the delay time calculation program can be created with one information processing device, and It is also possible to calculate the delay time with another information processing device by moving the data using the storage medium.
以上説明したように本発明は、計算ルール群切分は条件
を入力することで計算ルール群を自動的に切分は遅延時
間算出用プログラム作成手段が遅延時間算出用プログラ
ムを自動的に作成することにより、遅延時間算出計算ル
ールの入力が容易に行え、また新たな遅延時間算出計算
ルールで遅延時間を算出できるまでの期間が短縮できる
効果がある。As explained above, the present invention automatically divides a calculation rule group by inputting a condition, and the delay time calculation program creation means automatically creates a delay time calculation program. This makes it possible to easily input the delay time calculation calculation rule, and has the effect of shortening the period until the delay time can be calculated using the new delay time calculation calculation rule.
第↓図は本発明の一実施例のブロック図である。
ｌ・・・、−制御装置、２・・・・・・記憶装置、３・
・・・・・記憶装置、４・・・・・・入力装置、１１−
・・・・・・計算ルール群切分は条件入力手段、１２・
・・・・・計算ルール群読出し手段、１３・・・・・・
計算ルール群切分は手段、］−４・・−・・・配線情報
読出し手段、■５・・・・・・遅延時間算出用プログラ
ム作成手段、１６−・・・・・遅延時間算出手段、
２０・・・
・・配線構成データ、
２０ａ−・・・・最小槽
戒要素、
３０・・・
・・計算ルール群、
３０ａ・・・・・・計算
ルール。Figure ↓ is a block diagram of one embodiment of the present invention. l..., -control device, 2... storage device, 3.
...Storage device, 4...Input device, 11-
...... Calculation rule group division is a condition input means, 12.
...Calculation rule group reading means, 13...
Calculation rule group division means, ]-4... Wiring information reading means, ■5... Delay time calculation program creation means, 16-... Delay time calculation means, 20... Wiring configuration data, 20a-... Minimum tank precept element, 30... Calculation rule group, 30a... Calculation rule.
Claims (1)
最小構成要素ごとに記憶する第１の記憶手段と、前記配
線構成データの前記最小構成要素に対応する単位の遅延
時間算出計算ルールの複数個を計算ルール群として記憶
する第２の記憶手段と、前記計算ルール群を切分ける条
件を入力する第１の手段と、前記計算ルール群を前記第
２の記憶手段から読出す第２の手段と、前記第２の手段
が読出した前記計算ルール群を前記第１の手段からの切
分け条件に基づいて遅延時間算出計算ルールの単位に切
分ける第３の手段と、前記配線構成データを前記第１の
記憶手段から読出す第４の手段と、前記第３の手段から
の前記計算ルールおよび前記第４の手段からの前記配線
構成データに基づいて配線遅延時間を算出する演算手順
（プログラム）を作成する第５の手段と、前記第５の手
段により作成された前記演算手順に従って配線遅延時間
を算出する第６の手段とを備えることを特徴とする配線
遅延時間算出方式。 ２、前記第１および第２の記憶手段が同一記憶手段内に
存在することを特徴とする請求項１記載の配線遅延時間
算出方式。[Scope of Claims] 1. A first storage means for storing wiring configuration data of a wiring whose delay time is to be calculated for each minimum component; and a unit of delay corresponding to the minimum component of the wiring configuration data. a second storage means for storing a plurality of time calculation calculation rules as a calculation rule group; a first means for inputting conditions for dividing the calculation rule group; and a second storage means for storing the calculation rule group from the second storage means. a second means for reading; and a third means for dividing the calculation rule group read by the second means into units of delay time calculation calculation rules based on the separation condition from the first means; a fourth means for reading the wiring configuration data from the first storage means; and calculating a wiring delay time based on the calculation rule from the third means and the wiring configuration data from the fourth means. A wiring delay time calculation characterized by comprising: a fifth means for creating a calculation procedure (program) for calculating a wiring delay time; and a sixth means for calculating a wiring delay time according to the calculation procedure created by the fifth means. method. 2. The wiring delay time calculation method according to claim 1, wherein the first and second storage means exist in the same storage means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016872A JPH03220676A (en) | 1990-01-25 | 1990-01-25 | Wiring delay time calculating system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016872A JPH03220676A (en) | 1990-01-25 | 1990-01-25 | Wiring delay time calculating system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220676A true JPH03220676A (en) | 1991-09-27 |
Family
ID=11928286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016872A Pending JPH03220676A (en) | 1990-01-25 | 1990-01-25 | Wiring delay time calculating system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220676A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5761081A (en) * | 1995-04-28 | 1998-06-02 | Matsushita Electric Industrial Co., Ltd. | Method of evaluating signal propagation delay in logic integrated circuit |
| US8756545B2 (en) | 2011-08-17 | 2014-06-17 | Fujitsu Limited | Delay time calculating apparatus and method |
-
1990
- 1990-01-25 JP JP2016872A patent/JPH03220676A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5761081A (en) * | 1995-04-28 | 1998-06-02 | Matsushita Electric Industrial Co., Ltd. | Method of evaluating signal propagation delay in logic integrated circuit |
| US8756545B2 (en) | 2011-08-17 | 2014-06-17 | Fujitsu Limited | Delay time calculating apparatus and method |
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