JPH0322031A - Optimizing processing system for branch instruction - Google Patents

Abstract

PURPOSE:To shorten the processing time by holding an optimizing branch instruction, the relative address of the branch destination, optimizing branch instruction between this optimizing branch instruction and its branch destination, optimizing branch instructions interposed between other optimizing branch instructions and their destinations, and their branch destinations and temporary addressed to determine and optimum branch instruction. CONSTITUTION:A central processing unit 1, an optimizing branch instruction table part 2, an optimizing branch instruction relation table part 3, a symbol table part 4, and a source program file 5 are provided to constitute a system. An optimizing branch instruction, the relative address of its branch destination and optimizing branch instructions existing between this optimizing branch instruction and its branch destination are recognized and held, and optimizing branch instructions interposed between other optimizing branch instructions and their branch destinations, branch destinations, and temporary addresses are held to determine an optimum branch instruction. Thus, the optimizing processing of a branch instruction is quickly performed only with the table operation without increasing the number of busses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a branch instruction optimization processing method, and particularly to a branch instruction optimization processing method in a translation program.

[Conventional technology]

Some translation programs that target microprocessors that have branch instructions with different code lengths depending on the branch instruction and the relative address of the branch destination of that branch instruction automatically There is a translation program that has a function of selecting a branch instruction with a short code length (hereinafter, this selection process will be referred to as branch instruction optimization processing).

Optimization processing of branch instructions involves replacing them with an optimal branch instruction (hereinafter, this instruction is referred to as an optimized branch instruction).
Assuming that the branch instruction has the longest (or shortest) code length, calculate the relative address of the branch instruction and its branch destination, and then calculate the value that allows the relative address to branch with a branch instruction with a shorter code length than the branch instruction that has been temporarily determined. (or if the relative address cannot be branched with the temporarily determined branch instruction), this is done by replacing it with a branch instruction with a shorter (or longer) code length.

If a branch instruction with a different code length is substituted, the relative address will change, and the optimal branch instruction among other optimized branch instructions may change.

In order to solve this problem, conventionally, a temporary address is given from the beginning to the end of the source program, and this temporary address is used to calculate the relative address of the branch instruction and its branch destination from the optimized branch instruction at the beginning of the source program. are calculated in order, and if the optimized branch instruction is replaced with a branch instruction that differs from the temporarily determined code length, the subsequent temporary addresses are changed and the relative address of the next optimized branch instruction and its branch destination is calculated. This procedure optimizes the source program up to the last branch instruction.

In this method, by replacing the branch instruction with a branch instruction having a different code length, there is a possibility that the relative address of the branch instruction whose relative address has already been calculated and the branch destination thereof will change. For this reason, even if you optimize the source program to the end,
Furthermore, similar processing is performed to select the optimal branch instruction from the optimized branch instructions at the beginning of the source program, and the process is continued until all branch instructions can no longer be optimized. It was necessary to repeatedly input and process a compressed program file from beginning to end.

[Problem to be solved by the invention]

As mentioned above, conventional translation programs require many passes for optimization, and the disadvantage is that it takes a long time to assemble, especially when processing a source program with a variety of optimization branch instructions. was there.

[Means to solve problems]

The branch instruction optimization processing method of the present invention includes means for recognizing and retaining an optimized branch instruction and the relative address of its branch destination;
A means for recognizing and retaining an optimized branch instruction that exists between an optimized branch instruction and its branch destination, and a means for recognizing and retaining an optimized branch instruction that exists between an optimized branch instruction and its branch destination. It has a structure for determining an optimal branch instruction, and includes means for holding a branch destination and its temporary address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a block diagram of hardware and a flowchart for explaining the operation of the first embodiment of the present invention, respectively.

The hardware of this embodiment includes a central processing unit 1, an optimized branch instruction table section 2, an optimized branch instruction relationship table section 3, and symbol table sections 4 and 5 containing source program files. be confused.

The first example of the source program applied to this embodiment is
Shown in the table.

Table 1 in the margin below In this source program, the optimized branch instructions are BR,
There are two types of branch instructions: BRSSBRL. BRS allows branching to up to a relative address of 4, and BRL allows branching to all addresses. BRS has a code length of 1, and BRL has a code length of 3. In addition to branch instructions, there is an instruction DS that secures an area, and "DS 3" secures an area with a code length of 3.

The operation and structure of this embodiment will be explained using this source program.

Flow F1: First, a temporary address is given to the entire source program. The temporary address is calculated on the assumption that the optimized branch instruction has the same code length as the branch instruction with the shortest code length. At this time, the symbol and its temporary address are shown in Figure 2 (a
), the ident of the optimized branch instruction, its temporary address, and its branch destination are stored in l4 and 15 of the symbol table section 4 of FIG.
Store in.

In FIGS. 3(a) and (b), 6 is an identifier that uniquely indicates an optimized branch instruction in the source program,
7 is the temporary address of the optimized branch instruction, 8 is the branch destination, 9 is the relative address of the optimized branch instruction and the branch destination, 10 is the optimal branch instruction to replace the optimized branch instruction, 11 is the optimized branch instruction of 6 An example of an ident of an optimized branch instruction (hereinafter referred to as an inter-optimized branch instruction) located between and its branch destination is shown. The identifiers of optimized branch instructions are numbered starting from "1" in the order in which they appear in the source program. In the example in Table 1, the optimized branch instruction gives a tentative address with the same code length as BRS, "1", "L1" to 14 in FIG. 2(a), tentative address "0" to 15, " B
Figure 3 (a) with the ident of “R L2” set to “1”.
6, the temporary address "5" is stored in 7 in FIG. 3(a), and the branch destination "L2" is stored in 8 in FIG. “BR L3”
Similarly, 14 and 15 in Figure 2 and 6 in Figure 3 (a) are shown below.
, 7, 8.

Flow F2: Next, regarding the optimized branch instruction stored in the optimized branch instruction table section 2 in FIG. Figure 3 shows an optimized branch instruction with a temporary address of
It is detected from the optimized branch instruction table section 2 in a) and stored in 11 as an inter-optimized branch instruction, and the inter-optimized branch instruction is stored in 12 of the optimized branch instruction relation table section 3 in FIG. 4 as an inter-optimized branch instruction. The optimized branch instruction 6 in FIG. 3(a) is stored in the branch instruction 13.

In FIG. 4, l2 is an optimized branch instruction, and 13 is an optimized branch instruction in which an optimized branch instruction and its branch destination exist with the optimized branch instruction in between (hereinafter referred to as a narrow optimized branch instruction). Here is an example. At this time, if there is already a same-duration optimized branch instruction in 12, the optimized branch instruction of 6 is not stored in 12, but is stored in 13 of the same-duration optimized branch instruction. In the example in Table 1, 6 in FIG. 3(a), branch instruction "1"
The temporary address “5” of the branch destination “L2” and the temporary address “9” of the branch destination “L2”
” is detected from the temporary address 7 in FIG. 3. Optimized branch instruction “2” with temporary address “6” and optimized branch instruction “2” with temporary address “7” Since the branch instruction "3" can be detected, the optimized branch instructions "2" and "3" as the optimized branch instruction 12 and the optimized branch instruction "1" as the narrowly optimized branch instruction 13 in FIG. Similarly, the temporary address 6 in FIG. 8> is detected from the temporary address "7".

Since the optimized branch instruction "3" with the temporary address "7" can be detected, the optimized branch instruction "3" which is already stored as the optimized branch instruction 12 in FIG. , stores the optimized branch instruction "2".

Flow-F: Calculates the relative address between the optimized branch instruction and the branch destination and stores it in FIG. 3(a>9).

In the example in Table 1, the temporary address of the optimized branch instruction "1" is #5" and the temporary address of the branch destination "L2" is "9", so the relative address 9 is "4".

Flow F4: Next, the optimum branch instruction is selected from the optimized branch instruction (temporarily referred to as optimized branch instruction A) and the relative address 9 of its branch destination, and is stored in 1o. In the example in Table 1,
The relative address of both optimized branch instructions “l” and “2” is “4”
The following note: Since the branch instruction BRS with a short code length can be selected, and the relative address of the optimized branch instruction "3" is "7", the branch instruction BRL with a long code length can be selected.

(Shape B in Figure 3(a)).

Flow 1 Fs: At this time, if the code length of the optimized branch instruction assumed for optimized branch instruction A and the code length of the selected branch instruction 1o are different, the same optimized branch instruction as optimized branch instruction 8 is 4, the optimized branch instruction (temporarily referred to as optimized branch instruction B), which is the same as the optimized branch instruction 13 of optimized branch instruction A, is the same as the optimized branch instruction in FIG. 3(a). The difference between the temporarily determined code length of the optimized branch instruction A and the code length of the IO is increased or decreased in the relative address 9 of the branch destination. Since the code length of the optimized branch instruction was assumed to be ``bi'', which is the shortest code length of the branch instruction, the first
In the example in the table, the assumed code length of optimized branch instructions “1” and “2” is the same as the code length of the selected branch instruction BRS, but the optimized branch instruction “3” has the assumed code length. Since the code length of the selected branch instruction BRL is different,
Figure 4 Optimized branch instruction “3” between optimized branch instructions
Regarding l "2", the assumed code length "l" is specified in the optimized branch instruction and the relative address 9 of the branch destination in Figure 3 (a).
The difference between the code length “3” and the selected branch instruction BRL is “2”.
” is added. Therefore, the optimized branch instruction “1”. “2”
The relative addresses of are changed from "4" to "6" and from "2" to "4", respectively.

Flow F6: If the optimal branch instruction for optimized branch instruction B has been selected, it is determined whether the optimal branch instruction for B needs to be changed. That is, if the optimal branch instruction for the relative address 9 of B whose difference has been increased or decreased is not the branch instruction lO selected by the optimized branch instruction B in FIG. 3(a), the optimal branch of the optimized branch instruction B is Reconsider the order. Since the optimal branch instructions for the optimized branch instructions 1 and 2 have already been selected, it is determined whether the optimal branch instructions need to be changed. The relative address of optimized branch instruction “l” is #
6", branching is no longer possible with the selected BRS, so for the optimized branch instruction "1", flow F4 is executed.
reprocess from The relative address of the optimized branch instruction "2'" has become "4", but since branching is possible with the selected BRS, no reprocessing is performed.

After completing the processing of the above-mentioned flows F4, F5, and F6 for all the optimized branch instructions 6 in the table in FIG. 3(a) (state in FIG. 3(b)), source・Determine the actual address from the beginning of the program and end the optimization process.

FIG. 5 is a flowchart of a second embodiment of the present invention.

The processing of 7 mouths F, , F2 is the same as the processing of the first embodiment.

Flow F3 Second, the optimum branch instruction is selected from the temporary address 7 of the optimized branch instruction (temporarily referred to as optimized branch instruction 8) and the temporary address 15 of its branch destination 8, and stored in 10. In the example in Table 1, the relative address is "4" from the temporary address "5" of the optimized branch instruction "1" and the temporary address "9" of the branch destination "L2'", so BRS is selected.Optimized branch instruction Similarly, BRS is selected for "2".The optimized branch instruction "3" has a temporary address "7" and a branch destination "L".
Since the temporary address of B is “0”, the relative address is “7”, and the branch instruction BRL with the long code length is selected (6th
The state shown in Figure (a) and Figure 2 (a)! I4).

Flow F4: At this time, if the code length of the optimized branch instruction assumed for optimized branch instruction 8 and the code length of the selected branch instruction 10 are different, the 6th temporary address larger than the temporary address 7 of optimized branch instruction A is Regarding the temporary addresses 7 of all the optimized branch instructions in the figure and the temporary addresses 15 of all the symbols in FIG. 2, the difference between the code length of the temporarily determined optimized branch instruction 8 and the code length of the selected branch instruction 10. increase or decrease. Since the code length of the optimized branch instruction was assumed to be "1", which is the shortest code length of the branch instruction, in the example in Table 1, the code length of the optimized branch instructions "1" and "2" are the assumed codes. The length and the code length of the selected branch instruction BRS are the same, but
Since the assumed code length of the optimized branch instruction "3" differs from the code length of the selected branch instruction BRL, all tentative addresses after the tentative address "7" of the optimized branch instruction "3" are changed. That is, the temporary addresses of symbols L3 and L2 in FIG. 2 are "8" changed to "10" and "9" changed to "1", respectively.
It will be changed to 1”.

Flow F: If the same optimized branch instruction as optimized branch instruction A is at l2 in FIG. ) has already selected the optimal branch instruction, and if so, determines whether it is necessary to change the optimal branch instruction of the optimized branch instruction B.

In other words, if the optimal branch instruction for the temporary address 7 of B whose difference has been increased or decreased and the branch destination temporary address 15 does not become the selected branch instruction 10 of the optimized branch instruction B in FIG. Reconsider B's optimal branch instruction. From FIG. 4, the optimization branch instructions narrower to the optimization branch instruction “3” are the optimization branch instructions “12,” “2”. The optimization branch instructions “l”, “2”
Since the optimal branch instructions have already been selected for each of ``, it is determined whether it is necessary to change the optimal branch instructions.

The temporary address of optimized branch instruction 1 remains unchanged at "5", but
The temporary address of the branch destination L2 of the optimized branch instruction “l” is “l”
1", the relative address becomes "6" and branching is no longer possible with the selected BRS, so the optimized branch instruction "1" is reprocessed from flow F. Optimized branch instruction " The temporary address of ``2'' remains unchanged at ``6'', and the temporary address of branch destination L3 is now ``10'', but the relative address is ``4'' and branching is possible with the selected BRS, so no reprocessing is performed.

After completing the processing of the above-mentioned flows F3, F4, and Fs for all the optimized branch instructions 6 in the table of FIG. 6(a) (states of FIG. 6(b) and FIG. 2(b)), Finish the optimization process.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to perform branch instruction optimization processing at high speed only by table manipulation without increasing the number of buses.

[Brief explanation of the drawing]

Figure 1(a). 2(b) is a block diagram of the hardware of the first embodiment of the present invention and a flowchart for explaining the operation, and FIG. 2(a). (b) is a data layout diagram showing the state during processing and the state at the end of processing of the symbol table section of the first embodiment of the present invention, respectively;
Figures (a) and (b) are data layout diagrams showing the state during processing and the state at the end of processing of the optimized branch instruction table section of the first embodiment of the present invention. FIG. 5 is a flowchart for explaining the operation of the second embodiment of the present invention, and FIGS. 6(a) and 6(b) are FIG. 7 is a data arrangement diagram of a state during processing and a state at the end of processing, respectively, of the optimized branch instruction table section according to the second embodiment of the present invention. ■... Central processing unit, 2... Optimized branch instruction table section, 3... Optimized branch instruction relation table section, 4... Symbol table Part, 5
...Source program file, 6...
...Optimized branch instruction, 7...Temporary address, 8
...Branch destination, 9...Relative address, 1
0...Selected branch instruction, 11.12...
... Optimized branch instruction, 13... Optimized branch instruction, 14... Symbol, l5... Temporary address of symbol. S4 a)

Claims (1)

[Claims] A means for recognizing and retaining the relative address of an optimized branch instruction and its branch destination, a means for recognizing and retaining an optimized branch instruction existing between an optimized branch instruction and its branch destination, and a means for recognizing and retaining an optimized branch instruction existing between an optimized branch instruction and its branch destination, and a means for recognizing and retaining the relative address of an optimized branch instruction and its branch destination, and A branch characterized by comprising means for holding an optimized branch instruction in which another optimized branch instruction and its branch destination exist, and means for holding the branch destination and its temporary address, and determining an optimal branch instruction. Instruction optimization processing method.