JPH03219713A - Buffer amplifier - Google Patents

Abstract

PURPOSE:To enhance a constant current performance, to improve the characteris tic and to reduce number of components by making a drain current of a source follower constant through the use of a junction FET. CONSTITUTION:FETs Q1, Q2 form a source follower and junction FETs Q6, Q7 are a constant current load. A drain current ID1 of a FET Q1 in the buffer amplifier is kept constant by a resistor R9 connecting between the gate and source of a FET Q6 regardless of the gate-drain voltage of the FET Q6. Similar ly, the drain current of the FETQ2 is kept constant by a resistor R10.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention improves the characteristics and reduces the number of parts for a buffer amplifier used for impedance conversion mainly in the field of audio amplifiers. It's something you get.

[Prior Art] Generally, as this type of buffer 7 amplifier, a source follower stage complementary buffer 7 amplifier shown in FIG. 4 is known. In FIG. 4, Ql and Q2 are FETs (field effect transistors) in which a source follower is formed and are connected in a complementary manner. R1 and R2 are resistors, one end of which is connected to the sources of the FETs Q1 and Q2, the other ends of which are connected to each other, and this connection point is the output terminal 1.
It is connected to the. 2 is an input terminal, and the input terminal is connected to the gates of the FETs Ql and Q2, respectively. Q3 and Q4 are transistors that serve as constant current loads, and their bases are connected to dividing resistors R3 and R4 that divide the power supply voltages +Vcc and -Vcc (their terminals are indicated by the symbol 3.4) to the output terminal l. and the connection point of dividing resistors R5 and R6, respectively.

The collectors of the transistors Q3 and Q4 are connected to the FE, respectively.
T Ql, to the drain of Q2, and the emitter is connected to the resistor R
7, connected to the terminal 3.4 via R8.

In the buffer amplifier configured as above, the FET
The operating currents of Ql and Q2 are transistor Q3 and resistor R3.
, R4, R7, transistor Q4, resistors R5, R6,
Determined by R8.

In the above buffer amplifier, if we consider DC operation by grounding input terminal 2 and setting the gate currents of FETs Q+ and Q2 and the base currents of transistors Q3 and Q4 to zero, in this case, the The potential V8 is given as follows, and the emitter potential VE of the transistor Q3 is
is given as Vε:V[l+VllE. At this time, the drain current 1 of Ql (1 is determined by the voltage across the resistor R7 and the resistance value of the resistor R7. Now assuming that the power supply voltage fluctuates by ΔV, F
The variation ΔID of the drain current of ET Q+ is as follows.

[Problems to be Solved by the Invention] As described above, in the buffer amplifier described with reference to FIG.

It is easy to fluctuate the drain current of transistor Q.
A variation in VIE of 3 also causes the drain current to vary.

In this way, transistors Q3 and Q4 and resistors R3 and R4
, R5, R6, R? , R8 in the buffer amplifier shown in FIG. 4 has a low constant current property.
The operation of the FETs Q+ and Q2 is unstable, which adversely affects the characteristics of the buffer amplifier.

The present invention eliminates the drawbacks of the conventional buffer amplifier described above, improves constant current performance, improves characteristics, and reduces the number of parts.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a complementary buffer amplifier having a transistor configuration including a source follower, in which the drain current of the source follower is controlled by a junction FET. It is characterized by using a constant current.

[Function] In the buffer amplifier configured as described above, the drain current of the source follower is made constant using a junction FET, so that the constant current property can be enhanced and the characteristics can be improved.

Incidentally, in a junction FET, when VGS is kept constant and Vos is increased, the channel width becomes narrower due to the reverse bias between the drain and gate, and the current that can pass through is limited, and the drain current 1o becomes equal to VDS. It remains constant regardless of the increase.

Figure 5 shows a constant current circuit using the above junction FET,
The symbol Q5 indicates a FET, and R indicates a resistor connected to its source. In the constant current circuit shown in Fig. 5, the FET
VGS of Q5 is given by Vcs=Io number R, and if Io is constant, VCS is also constant,
Further, as described above, ID remains constant even if V[lS changes.

This invention uses the constant current circuit shown in FIG. 5 as a constant current circuit for a buffer amplifier.

[Example] A first example of the present invention will be described below with reference to FIG. FIG. 1 shows a complementary buffer amplifier in a source follower stage, and in FIG. 1, the same reference numerals as in FIG. 4, which describes the conventional example, indicate the same components.

Symbols Ql and Q2 are the aforementioned FETs, which form a source follower. Qe and Ql are junction FETs serving as constant current loads. The source of the FET Qa is connected to the drain of the FET Ql via a resistor R9, and the gate of the FET Qs is connected to the drain of the FET Qt. The drain of FET Qe is connected to the terminal 3 described above. On the other hand, the drain of FETQ7 is connected to the terminal 4 via a resistor RIG, and the drain of FETQ7 is
The gate of Qv is connected to the terminal 4. Further, the source of FET Qv is connected to the drain of FET Q2.

In the buffer 7 amplifier configured as shown in Figure 1 above, F
The drain current Io+ of ET Q+ is
F regardless of the gate-drain voltage V GD3 of s
It is kept constant by the resistor R9 connected between the gate and source of ET Qe, and its value is given by: Similarly, the drain current I02 of FET Q2 is kept constant by the resistor R1[l.

If the same FETs are used as the above FETs Q+, Qa, and Ql, and a FET that forms a complementary pair with the above FET Q+ etc. is used as FET Q2, the resistances R1, R2, R9, and RIG can be made to have the same resistance value. .

FIG. 2 shows a second embodiment, and the same reference numerals as in FIG. 1 indicate the same effects. The difference between the buffer amplifier in Fig. 2 and the one in Fig. 1 is that instead of the N-channel FET Q7 that constitutes the constant current circuit, a P-channel FE
TQs, and instead of the resistor RIG connected between the drain of FET Qv and terminal 40, a FET
The point is that a resistor R11 is used, which is connected between the source of Qe and the drain of FET Q2. Furthermore, FET Qa
The gate of is connected to the drain of FET Q2.

Even if configured like the buffer amplifier in Figure 2 above, the FET
The drain currents Io1 and ID2 of Q+ and Q2 can be kept constant. Further, by configuring it as shown in FIG. 2, there is an advantage that it can be vertically symmetrical.

FIG. 3 shows a third embodiment, and the same reference numerals as the buffer amplifiers in FIG. 1 indicate the same effects. The buffer amplifier in Fig. 3 has a two-stage configuration: a source follower formed by FETs Ql and Q2, and an emitter follower formed by transistors Q9 and Q+o.
to Q+, transistor Q+o emitter to FET Q
Bootstrap to 2. FET Qe,
Ql is a constant current load as described above, and DI, D
2 is a light emitting diode for voltage shifting to bias the transistors Q9 and Q+o.

Even with a buffer amplifier configured as shown in Figure 3 above, the FE
The drain currents ICII and ID2 of TQ+ and Q2 can be kept constant.

[Effects of the Invention] As described above, the present invention can make the operating current of the buffer amplifier stable and less likely to fluctuate due to the power supply voltage and other factors, thereby improving the power supply voltage fluctuation rejection ratio, distortion rate, and S A buffer amplifier with excellent characteristics such as /N ratio and a small number of parts can be obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a buffer amplifier showing a first embodiment of the present invention, Fig. 2 is a circuit diagram of a buffer amplifier showing a second embodiment, and Fig. 3 is a circuit diagram of a buffer amplifier showing a third embodiment. 4 is a circuit diagram of a conventional buffer amplifier, and FIG. 5 is a circuit diagram of a constant current circuit for explaining the present invention. Ql, Q2, Qa, Ql, Qs: FET, Q(
1, Q+a: transistor, 1: output terminal, 2: input terminal.

Claims (1)

Claims: A complementary buffer amplifier having a transistor configuration including a source follower, characterized in that the drain current of the source follower is made constant using a junction FET.