JPH03218552A - Memory control circuit and information processor - Google Patents

Abstract

PURPOSE:To reduce the number of the signal lines of a memory control circuit by setting a part of or all the address lines of a first semiconductor memory element and a part of the address lines of a second semiconductor memory element to be common. CONSTITUTION:The memory control circuit 1 outputs a part of or all address signals for the first semiconductor memory element 3 and a part of the address signals of the second semiconductor element 4 from the common sign1al line. When a microprocessor 2 accesses the first semiconductor memory element 3, an address signal obtained by multiplexing a row address and a column address for the first semiconductor memory 3 is outputted from the common signal line, and an address signal which is not multiplexed for the second semi conductor element 4 is outputted when the microprocessor accesses the second semiconductor memory element 4. Thus, the number of the signal lines in the memory control circuit 1 is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device and an improvement of a memory control circuit therein. The present invention relates to a technique for reducing the number of signal lines in a memory control circuit by sharing memory address signal lines and control signal lines.

[Conventional technology]

Usually, in information processing devices such as personal computers,
DRAM (dynamic random access memory) is used as the main memory. Also, B I O S
(basic Input Output system
The firmware called ea+ is stored in an EPROM (erasable programmable read-only memory). In some cases, SRAM (static random access memory) may be used.

In conventional personal computers and the like (1), when memory elements with different address signals and control signals are used together, the address signal and control signal are separately output to each memory element.

An example of the configuration of a conventional information processing device is shown in FIG. 3(A). As the microprocessor (MPU) 2, Intelligent's 8088 is used, but this is a microprocessor with an internal data path of 16 bits and an external data path of 8 bits. The address has 20 bits, and the lower 8 bits of the address and the 8 bits of data are multiplexed.

AD7~0 is this address/data node, and AI
9 to 8 are the upper 12 bits of the address bus. D
In this example, RAM 3 has a capacity of 256 kilobytes (hereinafter referred to as KB).

FIG. 4 shows DRAM 3 in more detail. IM with 256K words x 4 and soto configuration
DRAM3 1 is 256Kx8 DRA
It constitutes M3. DMA8-0 are nine address lines for DRA-13, which are divided into 18-bit addresses or 9 bits of row address and 9 bits of column address, which are multiplexed and input. DM7~0 is D
This is an 8-bit data path for RAM3, and RAS, CA
S, WE, and OE are control signals for DRAMB. In addition, RAS (row address
strobe) is a control signal for loading the row address into DRAM3, and CAS (column add
ress strobe) sets the column address to DRAM3.
This is a control signal for importing into WE (write
enable) is a pulse for writing data, and OE (Output enable) is a signal for controlling data output. In this configuration example, the OE terminal is always a roll bell (hereinafter referred to as L).

In FIG. 3(A), the capacity of the EPORM 4 is 32 KB, the details of which are shown in FIG. This is an EPORM with a 32KX8 configuration, with SMA14-0 being the address bus of the EPROM4, and SMD7-0 being the data path. OE
, CE are control signals of EFROM4, and O
E (outputenable) is a data output enable signal, and C E (chip enable) is a data output enable signal.
) is the chip selection signal.

Fuzo Ii5. Separately, L is rich, UL
The data readout is controlled by the other party.

In FIG. 3(A), data paths DM7 to DRAM3
0 and the data buses SMD7-0 of the EPROM 4 are connected to a common bus, which is connected via a data path buffer 5 to the address/data bus AD7-0 of the CPU.

The memory control circuit 11, which is related to the point of the present invention, uses the address signals A19-8 and AD7-0 issued by the microprocessor 2 to control the DRAM 3 and EPROM 4.
It creates address buses DMA8-0 and SMA14-0 for It also generates control signals for DRAM3 and EPROM4.

FIG. 3(B) shows the configuration of this memory control circuit 11 in more detail. The latch 12 is activated by an ALE signal (address latch enable signal) indicated by reference numeral 14.
Address signal issued by microprocessor 2 (
A19 to A8, AD7 to ADO) are latched. The lower 15 bits of the latched 20-bit address are used as the address signal (SMA) for EFROM4.
14~SMAO). Furthermore, the lower 18 bits are multiplexed by the multiplexer 13 by 9 bits, and the address signal for DRAMB (DMA
8 ~ DMAO). MPX indicated by code 15
is a multiplex control signal which, when accessing the DRAM 3, is at low level at the beginning of the cycle, becomes high level in the middle, and returns to L at the end of the cycle. When MPX-L, the lower 9 bits of the following 18 bits of the latched address are output to DMA8-0, and when MPX-H, the upper 9 bits are output.

The control signal generation circuit 18 generates MEM R (meI
Ioryread) signal and MEMW (meI
Ilory write) signal and the upper 5 bits of the latched address (this is referred to as LA19 to LA15)
, the control signals RAS, CAS, WE for DRAMB
It also generates a control signal OE for the EPROM 4 and a multiplex signal (MPX) 15. The control signal generation circuit 18 is shown in more detail in FIG. 3(C). In this configuration example, the address area of the DRAM 3 is OOOOOH~3FFFFH (the last H indicates hexadecimal notation), and the address area of the EPROM 4 is F8000H~FFFFFFH. NOR gate 19 and NAND gate 20 are each D
It decodes addresses in the RAM area and EFROM 6i area.

In the delay line 21, outputs B and C are signals delayed by a certain period of time with respect to input A. When microprocessor 2 reads (a) DRAM3, (b)
When DRAM3 is written, and (c) EPROM4
FIG. 3(D) shows the timing of each part of FIG. 3(C) for each when reading. In this specification, two ways of writing signal names, RAS and -RAS, are used, but it should be noted that they refer to exactly the same thing.

[Problem to be solved by the invention]

As explained in FIGS. 3(A) to 3(D), when different types of memory elements (DRAM3 and EFROM4 in this configuration) are used in a conventional information processing device,
A separate address line (DM
A8~0 and SMA14~0, total 14) and control signal lines (RAS, CAS, WE, OE, total 4), so many signal lines (28 in this configuration example) were required. It happened.

Recently, memory control circuits and the like are often made of gate arrays, and the number of pins in a gate array is limited, and the more signal lines there are, the fewer the number of pins that can be used for other circuits. Also, when considering the artwork of a circuit board, the more signal lines there are, the more difficult it becomes to wire the circuit.

Therefore, an object of the present invention is to reduce the number of signal lines in a memory control circuit. Another object of the present invention is to provide an information processing device with a reduced number of signal lines.

[Means to solve the problem]

Therefore, in the present invention, the first semiconductor memory element (DR
AM) address signal and the second semiconductor memory element (EP
A common signal line is used as the address signal for ORM). Further, the DRAM control signal and the EPROM address signal are also made to use a common line.

That is, the memory control circuit according to the present invention includes a first semiconductor memory element such as a DRAM whose address input is a signal obtained by multiplexing a row address and a column address;
In a circuit that controls a second semiconductor memory element such as an EFROM that receives an ordinary address signal that is not multiplexed as an address input, a part or all of the address line of the first semiconductor memory element and the second semiconductor memory element are controlled. It is characterized by having a part of the address line in common with the address line.

Further, an information processing device according to the present invention includes a microprocessor, a first semiconductor memory element whose address input is a signal obtained by multiplexing a row address and a column address,
A memory control circuit comprising: a second semiconductor memory element whose address input is an address signal that is constant during a cycle and is not multiplexed; and a memory control circuit that controls the first semiconductor memory element and the second semiconductor memory element. outputs part or all of the address signal for the first semiconductor memory element and part of the address signal for the second semiconductor memory element from a common signal line, and the microprocessor outputs part or all of the address signal for the second semiconductor memory element from the common signal line. When the microprocessor accesses the first semiconductor memory device, an address signal in which the row address and column address for the first semiconductor memory device are multiplexed is output, and when the microprocessor accesses the second semiconductor memory device, the second semiconductor memory device is accessed. A non-multiplexed address signal for a semiconductor memory device is output.

[Effect]

According to the present invention, since DRAM (first semiconductor memory element) and EFROM (second semiconductor memory element) are never accessed at the same time, the function of each signal corresponds to which memory element is accessed. By switching between them, a common signal line can be used for DRAM and EPROM.

〔Example〕

Hereinafter, the present invention will be explained in detail based on Examples.

FIG. 1(A) shows an information processing apparatus according to a first embodiment of the present invention, and FIG. 1(B) shows the memory control circuit 1 of FIG. 1(A) in more detail. When comparing FIG. 1(A) and FIG. 3(A), the memory control circuit 1 is different from the memory control circuit 11, and the difference is that a control signal buffer 6 is added, but everything else is different. It's the same. That is, the part of the memory control circuit 1 shown in FIG. 1(B) and the control signal buffer 6 shown in FIG. 3(B) are different,
This FIG. 1(B) and the control signal buffer will be explained in detail.

In FIG. 1(B), latch 12 and ALE signal 1
4 is the same as that in FIG. 3(B). The output of the latch 12, that is, the address latched by the ALE signal is assumed to be LA19-0.

Multiplexer 13 and M P
lex ) signal 15 is also the same as in FIG. 3(B).

SMA14 to SMA12 in Figure 1 (B) are EPROM4
This is a dedicated address, and the output of latch 12 (LA14~
12), and these three signals are shown in Figure 3 (
This is the same as SMA14 to SMA12 in B). but,
SMAII to SMAO in FIG. 3(B) are not present in FIG. 1(B). NAND gate 16 decodes the address area of EPROM 4. In this example, EFR
Set the address area of OM4 to F8000H-FFFFH (
H is a symbol indicating hexadecimal representation), and when the EFROM 4 is accessed, the output of the NAND gate 16 becomes L. At this time, the output of the AND gate 17 becomes "If", and the output of the multiplexer 13 becomes LA8.
~LAO is output. That is, when accessing EFROM4, SMA8/DMA8 to SMAO/D
A non-multiplexed address signal (LA8 to LAO) for EPROMJ is output to AMO.

In addition, the DRAM area (in this example, ooooooH to 3F
When accessing FFFH (DRAM area), the output of the NAND gate 16 becomes H and the output of the AND gate 17 becomes equal to MPX, so the multiplexer 13 operates exactly the same as the multiplexer 13 in FIG. 3(B). do. That is, when accessing the DRAM area, multiplexed address signals for DRAMB are output to SMA8/DMA8 to SMAO/DMAO. When accessing DRAM, MPX-L
When , LA8 to LAO are output, and when MPX-H, LA17 to LA9 are output. Therefore, S
Nine signals AM8/DMA8 to SMAO/DMAO can be used as addresses for DRAMB. The details of the control signal generation circuit 18A are shown in FIG. 1(C). When compared with the control signal generation circuit 18 shown in FIG. 3(C), FIG.
The only difference is that an OR gate 22 is added. EN-DRA of the output of the NOR gate 22
The M (ENABLE DRAM) signal 7 is a signal that controls enable/disable of the control signal buffer 6 (Fig. 1 (A)).
-DRAM7 becomes L to enable the buffer 6, and becomes H to disable the buffer 6 except when accessing the DRAM.

Although not shown in the figure, when the buffer in FIG. 1(A) is at H, all outputs of the buffer 6 are at H.

All Xs are the same as the corresponding signals in FIG. 3(C), including the timing. RAS, CAS, WE are DRAM
OE is a control signal for EPROM4. MPX is a signal that controls multiplexing of the row address and column address of the DRAM3.

The timing of each signal in FIG. 1(C) is shown in FIG. 1(D). The selector 23 in FIG. 1(B) selects between control signals RAS, CAS, WE for DRAMB and addresses SMA9 to SMA11 for EPROM4. When accessing EPROM, the output of NAND gate 16 becomes L, and SMA9
.about.11 are selected and output. When accessing DRAM, the output of NAND gate 16 becomes H, and RAS, CAS
, WE are selected and output. That is, RAS/S
MA9, CAS/SMAIO, WE/SMAIL is D
The control signal for RAMB and the address signal for EFROM4 are shared.

The embodiments of the present invention have been described above with reference to FIGS. 1(A) to 1(D), but they can be summarized as shown in FIG. 1(E). SMA8/DMA8~SMAO/
DMA O shares the address signal for EPROM4 (M number and address signal for DRA Fv13), and also uses WE/SMAII, DAS/SMA10,
RAS/SMA9 is the address signal for EPROM4 and D
Control signals for RAMB are shared. These signals are transmitted to EPROM4 and DRAM as shown in Figure 1(E).
In response to access to each of the three memories, the functions are switched and necessary signals are output to each memory. S
MA14 to SMA12 and OE are used only in EPROM4 and not in DRAM3.

EPROMs and DRAMs have considerably different address signals and control signals, and conventionally, address signals and control signals have been sent out on separate signal lines for each memory element. Therefore, the number of memory-related signal lines became extremely large, which was a big problem. In particular, when creating a memory control circuit using a gate array, etc., there is a limit to the number of input/output terminals of the gate array, and as the number of required signal lines increases,
Since a large-scale gate array must be used, the cost has increased significantly. In contrast, the present invention proposes a new technique for outputting address signals and control signals for different types of memory elements from a common signal line, and has succeeded in reducing the number of signal lines. In the case of this embodiment, the output of the memory control circuit is reduced by 11 from 28 in the conventional circuit (Fig. 3 (B)) to 17 in the circuit of Fig. 1 (B). .

FIG. 2 shows a second embodiment of the present invention, in which (A) is a block diagram of an information processing device, and (B) is a block diagram of a memory control circuit 1. In FIG. As is clear from comparing these with FIGS. 1(A) and 1(B), only the memory control circuit 1 and the selector 23 are provided in this second embodiment. As is clear from Figure 2 (B), EFROM4
By sharing the address lines for S
9 pieces of MAO/DMAO to SMA8/DMA8 and SM
It has been reduced to 6 pieces (A9 to SMA14).

〔Effect of the invention〕

As explained in detail above, in the present invention, the DRAM (first
Since the EFROM (second semiconductor memory device) and EFROM (second semiconductor memory device) are never accessed at the same time, by switching the function of each signal according to which memory device is accessed, a common signal line can be used. DRAM
It can be used for both EFROM and EFROM. This makes it possible to considerably reduce the cost of the gate array of the memory control circuit. Also, regarding the artwork on the board, the fewer the number of signal lines, the greater the benefit. Also,
If only the memory element is made as a module on a sub-board, the number of connector bins that connect the main board on which the memory control circuit is mounted and the sub-board on which the memory element is mounted is reduced, which also reduces the cost of connectors. There is an effect that makes it possible.

[Brief explanation of drawings]

1(A) to 1(E) are diagrams showing a first embodiment of the present invention, FIG. 2(A) and FIG. 2(B) are diagrams showing a second embodiment, and FIG. 3(A) to 3(D) are diagrams showing conventional configuration examples, FIG. 4 is a diagram showing a DRAM section, and FIG. 5 is an explanatory diagram of an EFROM. DESCRIPTION OF SYMBOLS 1... Memory control circuit according to the present invention, 11... Conventional memory control circuit, 2... Microprocessor, 3...
...DRAM section (256Kx8), 5...Data path buffer, 12...Latch, 13...Multiplexer, 1 4 -ALE (address l
atch enable) signal, 1 5 =- M P
X (Ilultiplex) signal, l 5 . ．．
．． N A AND gate, 17...AND gate, 3
1...IMDRAM with 256K words x 4 bits configuration
, 6... Control signal buffer, 7... Control signal buffer enable signal, 18, 18A... Control signal generation circuit, 19... NOR gate, 20... AND gate, 21... Derailleur In, 22...NOR gate, 23...Selector.

Claims (1)

[Claims] 1. A first semiconductor memory element whose address input is a signal obtained by multiplexing a row address and a column address, and a second semiconductor memory element whose address input is a normal address signal that is not multiplexed. A memory control circuit that controls a part or all of the address lines of the first semiconductor memory element and a part of the address lines of the second semiconductor memory element are used in common. . 2. The address line common to the first semiconductor memory element and the second semiconductor memory element has a row address for the first semiconductor memory element when the first semiconductor memory element is accessed. 2. The memory according to claim 1, wherein a column address is multiplexed and output, and when the second semiconductor memory element is accessed, a constant access signal for the second semiconductor memory element is always output. control circuit. 3. A microprocessor, a first semiconductor memory element whose address input is a signal obtained by multiplexing a row address and a column address, and a second semiconductor memory whose address input is an address signal that is constant during a cycle and is not multiplexed. and a memory control circuit that controls the first semiconductor memory element and the second semiconductor memory element, the memory control circuit controlling part or all of the address signal for the first semiconductor memory element. A part of the address signal for the second semiconductor memory element is output from a common signal line, and when the microprocessor accesses the first semiconductor memory element, the address signal for the first semiconductor memory element is outputted from the common signal line. An address signal in which a row address and a column address for the semiconductor memory device are multiplexed is output, and when the microprocessor accesses the second semiconductor memory device, the address signal is not multiplexed for the second semiconductor memory device. An information processing device characterized in that an address signal is output. 4. The memory control circuit outputs a part of the control signal for the first semiconductor memory device and the address signal for the second semiconductor memory device from a common signal line, and this common signal line is an enable terminal. is connected to the control signal terminal of the first semiconductor memory element via a buffer having a buffer, the buffer is controlled to be enabled by the enable terminal when the microprocessor accesses the first semiconductor memory element, and the buffer is controlled to be enabled by the enable terminal when the microprocessor accesses the first semiconductor memory element. 4. The information processing apparatus according to claim 3, wherein the second semiconductor memory element is controlled to be disabled when the processor accesses the second semiconductor memory element.