JPH03217172A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To improve resolution in a vertical direction for a picture with small noise and to reduce the amount of the noise for a picture with much noise by adaptively adding scanning line interpolation and the average of a current signal by using a delay circuit which can delay the signal for more than 1H. CONSTITUTION:When an electric field intensity detection circuit 110 outputs strong electric field intensity, a control circuit 113 sets a count K of a multiplier 1105 to 1. Since the count (1-K) of a multiplier 2106 becomes 0 as a result, as the output of an adder 107, the current signal is outputted as it is. When the electric field is gradually weakened, the count (1-K) of the multiplier 2106 is gradually enlarged. An interlace signal 101 and an average value signal are added and for the ratio of the signals, the average value signal is increased while weakening the electric field. For a double speed interpolation signal 109, the added result between the interlace signal 101 and the average value signal, and the average value signal are alternately outputted. When the electric field is changed from weak to strong, the inverse operation is executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit that performs scanning line interpolation.
It particularly relates to scan line interpolation with digitized video data.

[Prior Art] So-called digital television (DT'V) consists of three-dimensional Y/O separation, scanning line interpolation, and interlacing technology. In particular, scanning line interpolation increases vertical resolution. This is important for improving image quality, such as making line flickers less noticeable. The method of scanning line interpolation is to use a 1H line memory that stores image data for one horizontal scanning period (hereinafter abbreviated as IR) or a delay circuit that delays it by 1H to create the average value of the current signal and the signal 1H before. There is a method of performing scanning line interpolation based on values.

[Problems to be Solved by the Invention] However, when such scanning line interpolation is performed, the following problems arise. When reproducing a video source with little noise, such as an optically readable disc or a high-quality VTR, or when stable and good television reception can be achieved, scanning line interpolation can be effective. However, in cases such as television reception in areas where the electric field strength is weak, it is not possible to obtain a sufficient S/N ratio, so it is more desirable to improve the S/N ratio than to improve the image quality by scanning line interpolation.

In the present invention, by using a delay circuit that can delay more than IH and adaptively adding scanning line interpolation and the average of the current signal, scanning line interpolation is selected on a screen with little noise, and the vertical resolution is By increasing the vertical resolution on noisy screens and selecting the average value of the current signal and memory on noisy screens, the vertical resolution is increased on noisy screens, and the vertical resolution is increased on noisy screens. The purpose is to reduce the amount of noise.

[Means for Solving the Problems] In order to achieve the above object, the video signal processing circuit of the present invention has the following features: (1) α) In a video signal processing circuit that performs scanning line interpolation, b) is capable of delaying at least one horizontal scanning period. a delay device; C) an arithmetic unit that outputs the average of the output of the delay device and the current signal; d) a multiplier 1 that multiplies the current signal by a factor of K; and e) a multiplier that multiplies the output of the arithmetic device by a factor of -K) multiplier 2
and f) an adder that adds the output of the multiplier 1 and the output of the multiplier 2! 1) An interpolation circuit that performs scanning line interpolation using the output of the adder and the output of the arithmetic unit; and 1) A control circuit that controls the coefficient K of the multiplier 1 and the multiplier 2. do.

(2) (Z) A tuner for receiving television broadcasts, and b) a detection circuit for detecting electric field strength from the tuner and outputting it to the control circuit.

[Example 1] Hereinafter, a configuration example of the present invention will be explained based on the drawings. Figure 1 is a configuration diagram of a video signal processing circuit according to the present invention.

The 101 interlaced signal is, for example, a composite video signal, a luminance signal, a chrominance signal, etc. The 1021H delay circuit only needs to be a shift register that can delay IH.
Alternatively, it may be configured with a 1H line memory. The 106 adder adds the current signal and the output signal of the 1021H delay circuit, and in addition to multiplying the current signal by 1/2 with the 104 shift register, the average value of the current signal and the output signal of the 1021H delay circuit (hereinafter this value) is added. The signal is abbreviated as the average value signal). This configuration may be of any type as long as the average value of the current signal and the output signal of the 1021H delay circuit can be obtained. For example, each signal may be multiplied by 1/2 in a shift register and then added. The 105 multiplier 1 multiplies the current signal by a multiplier K determined by the 113 control circuit. The 106 multiplier 2 multiplies the output signal of the 10477 register by a multiplier (1-K) determined by the 113 control circuit. The 107 adder adds the outputs of the 105 multipliers 1 and 106 multipliers 2. . The 108 interpolation circuit combines the output of the 107 addition circuit with 1
Double-speed interpolation is performed based on the output of the 04 shift register, that is, the average value signal, to obtain a 109-times speed interpolation signal. An antenna 110 and a tuner 111 receive television broadcasting, and from this received signal, a field strength detection circuit 110 detects the field strength of the channel currently being received. This can be easily realized using the RFAGO of the 109 tuner, the color killer signal used in the color demodulation circuit, etc. The output of the 112 field strength detection circuit is sent to the 116 control circuit, and together with the 114 video/RF discrimination signal, determines the multiplier K of the 105 multiplier 1 and the 106 multiplier 2 mentioned earlier.

In addition to the 113 control circuit, the 1021H delay circuit 104
The shift register and the 108 interpolation circuit are controlled, but this control may be performed by providing another control section.

The operation of the video signal processing circuit shown in FIG. 1 will be explained with reference to FIG. It is assumed that the 114 video/RF discrimination signal is currently discriminating an RF signal. The 1021H delay circuit delays the 101 interlace signal by 1H, and its output is an image signal 1H before the current signal. 10
The output of the 4 shift register is the average value signal of the current signal and the output signal of the 1021H delay circuit. Although taking the average reduces information, it is an effective means for reducing noise. For example, if the correlation between the image signal 1H ago and the current image signal is strong, by taking the average value, the amount of noise becomes 1/2 in power and 1/2 in amplitude. Therefore, it can be seen that using the average value is more resistant to noise than the original signal.

Assume that when a television broadcast is being received by antenna 110 and tuner 111, the electric field strength detection circuit 110 outputs a strong electric field. The 113 control circuit sets the coefficient K of the 105 multiplier 1 to 1. As a result, the coefficient (1-K) of the 106 multiplier 2 becomes 0, so the current signal is output as is from the 107 adder. Therefore 109
The double-speed interpolation signal is of a type in which an average value signal and a 101 interlaced signal are alternately output.

Next, suppose that the electric field gradually weakens. The electric field strength detection circuit 112 outputs to the control circuit 113 that the electric field has become weak. The 113 control circuit thereby reduces the coefficient K. Therefore, the coefficient of 1.06 multiplier 2 ( 1 −K
) gradually becomes thicker. As can be seen from Figure 2, the output result of the adder 107 is the addition of the 101 interlace signal and the average value signal, and the absolute value remains 1, but as the ratio or the electric field becomes weaker, the average value signal increases. The 109 times higher speed interpolation signal is of a type in which the addition result of the 101 interlace signal and the average value signal and the average value signal are output alternately. When the electric field increases from weak to strong, the opposite operation is performed.

If the electric field becomes weak and the electric field strength detection circuit 112 determines that the electric field is completely weak, the control circuit 113 sets the coefficient K to 0.
Since the coefficient (1-X) of the 6 multiplier 2 is 1, the output result of the multiplier is only the average value signal. As a result, the 109 times speed interpolation signal is of a type in which the average value signal is repeated twice.

By performing the above operations, the vertical resolution increases when the electric field is strong, and a scissor image with less noise is obtained when the electric field is weak. This switching becomes more noticeable as the control precision of the coefficient K increases in the 1 1 3 itll control circuit.
If the accuracy decreases and it becomes noticeable, it can be made unsightly by performing this switching during the retrace period or by giving the switching a certain period of hysteresis.

Furthermore, it goes without saying that the 103 adder and 104 shift register can be omitted by changing the coefficient K of the multiplier between 1 and 0.5.

[Effects of the invention] As described above, according to the present invention, a scanning interpolation circuit that increases vertical resolution on a screen with little noise and reduces noise on a screen with a lot of noise can be realized with a simple configuration. Therefore, it is possible to reduce costs and facilitate miniaturization.

Furthermore, since the interpolation mode changes automatically and step-by-step depending on the field strength, good image quality is always obtained without any user intervention when receiving television, making it ideal for small portable television receivers. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing circuit according to the present invention. FIG. 2 is an operation diagram showing the control shown in FIG. 1. 101... Interlaced signal 102...
...1H delay circuit 103... Adder 104... Shift register 105... Multiplier 1 106... Multiplier 2 107... Adder 108...Interpolation circuit 109...Double speed interpolation circuit 110...Antenna 111...Tuner 112...Field strength detection circuit 116... ...control circuit

Claims (2)

[Claims] (1) a) A video signal processing circuit that performs scanning line interpolation, b) a delay device capable of delaying at least one horizontal scanning period, c) an arithmetic unit that outputs the average of the output of the delay device and the current signal, and d) a multiplier 1 that multiplies the current signal by a factor k; and e) a multiplier 2 that multiplies the output of the arithmetic unit by a factor (1-k).
and f) an adder that adds the output of the multiplier 1 and the output of the multiplier 2; g) an interpolation circuit that performs scanning line interpolation using the output of the adder and the output of the arithmetic unit; h) the multiplication 1. A video signal processing circuit comprising a control circuit for controlling a coefficient k of a multiplier 1 and a multiplier 2. (2) The video signal according to claim 1, further comprising: (a) a tuner that receives television broadcasting; and (b) a detection circuit that detects electric field strength from the tuner and outputs it to the control circuit. processing circuit.