JPH03217147A - Fsk demodulating circuit - Google Patents

Fsk demodulating circuit

Info

Publication number
JPH03217147A
JPH03217147A JP1309390A JP1309390A JPH03217147A JP H03217147 A JPH03217147 A JP H03217147A JP 1309390 A JP1309390 A JP 1309390A JP 1309390 A JP1309390 A JP 1309390A JP H03217147 A JPH03217147 A JP H03217147A
Authority
JP
Japan
Prior art keywords
frequency
circuit
signal
fsk
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1309390A
Other languages
Japanese (ja)
Inventor
Takeo Anzai
安齊 武雄
Hirokazu Norimatsu
乗松 宏和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Platforms Ltd
NEC Corp
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP1309390A priority Critical patent/JPH03217147A/en
Publication of JPH03217147A publication Critical patent/JPH03217147A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To prevent the degradation in quality of a reception signal due to band limiting by limiting the amplitude of an FSK signal and dividing the frequency and discriminating the frequency of the frequency divided signal to output a signal indicating the level of data. CONSTITUTION:The received FSK signal has the amplitude limited by a limiter circuit 1 and has the frequency accurately divided by the frequency dividing circuit of a binary counter 2 and is inputted to a frequency discriminating circuit 3. Thus, a conventional frequency converting circuit consisting of a local oscillating circuit 4, a multiplier 5, and a band selecting filter 6 is unnecessary, and the degradation in quality of reception data due to the output frequency deviation of the local oscillating circuit 4 is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はFSK復調回路に関し、特にデータ変復調装置
等に使用されるFSK復調回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FSK demodulation circuit, and particularly to an FSK demodulation circuit used in a data modulation/demodulation device or the like.

〔従来の技術〕[Conventional technology]

従来のこの種のFSK復調回路は、第2図に示すような
ヘテロダイン方式の回路が使われている。FSK信号は
、リミット回路1を通り振幅制限されたあと、乗算器5
で局部発振器4から与えられる復調用キャリアと乗算さ
れて、周波数変換を受ける。このあと、帯域選択フィル
タ6で所要帯域成分を抽出して、周波数弁別回路3を通
すことにより、データ信号を再生する。
A conventional FSK demodulation circuit of this type uses a heterodyne type circuit as shown in FIG. After the FSK signal passes through a limit circuit 1 and has its amplitude limited, it is sent to a multiplier 5.
The signal is multiplied by the demodulation carrier given from the local oscillator 4 and subjected to frequency conversion. Thereafter, a required band component is extracted by a band selection filter 6 and passed through a frequency discrimination circuit 3 to reproduce a data signal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述の従来のFSK復調回路では、周波数変換のために
局部発振器4、乗算器5、帯域選択フィルタ6を必要と
するので、局部発振器4の出力周波数偏差により生じる
周波数誤差の影響で、受信信号の品質劣化を生ずるとい
う問題がある。
The conventional FSK demodulation circuit described above requires a local oscillator 4, a multiplier 5, and a band selection filter 6 for frequency conversion. There is a problem that quality deterioration occurs.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の回路は、FSK信号を振幅制限して送出するリ
ミッタ回路と、該リミッタ回路の送出信号を分周する分
周回路と、該分周回路の分周信号の周波数を弁別してデ
ータのレベルを示す信号を出力する周波数弁別回路とを
備えている。
The circuit of the present invention includes a limiter circuit that limits the amplitude of an FSK signal and sends it out, a frequency divider circuit that divides the frequency of the signal sent out by the limiter circuit, and a frequency divider circuit that discriminates the frequency of the divided signal of the frequency divider circuit to determine the data level. and a frequency discrimination circuit that outputs a signal indicating the frequency.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。受信し
たFSK信号はリミッタ回路1を通り振幅制限された後
、バイナリカウンタ2の分周回路により正確に分周され
て、周波数弁別回路3に入力される.本実施例の場合、
第3図に示すように、伝送路上の周波数(Fz,Fa)
と周波数弁別回路3に入力される周波数(fz,fa)
との関係は、Fz=f zX2N Fa=f aX2N
(但し、Nはバイナリカウンタの段数)となり、従来回
路のような局部発振回路4、乗算器5、および帯域選択
フィルタ6から成る周波数変換用回路が不要であり、局
部発振回路4の出力周波数偏差に起因する受信データの
品質劣化を無くすることができる. 〔発明の効果〕 以上説明したように本発明によれば、FSK復調回路で
の周波数変換を、受信周波数に誤差を与えず、従って帯
域制限による受信信号の品質劣化を生じること無く行う
事ができる。
FIG. 1 is a block diagram of one embodiment of the present invention. The received FSK signal passes through a limiter circuit 1 to have its amplitude limited, and then is accurately frequency-divided by a frequency divider circuit of a binary counter 2 and input to a frequency discrimination circuit 3. In the case of this example,
As shown in Figure 3, the frequency (Fz, Fa) on the transmission path
and the frequency (fz, fa) input to the frequency discrimination circuit 3
The relationship is Fz=f zX2N Fa=f aX2N
(However, N is the number of stages of the binary counter), and the frequency conversion circuit consisting of the local oscillation circuit 4, multiplier 5, and band selection filter 6 as in the conventional circuit is unnecessary, and the output frequency deviation of the local oscillation circuit 4 It is possible to eliminate the quality deterioration of received data caused by [Effects of the Invention] As explained above, according to the present invention, frequency conversion in the FSK demodulation circuit can be performed without giving an error to the received frequency, and therefore without causing quality deterioration of the received signal due to band limitation. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例のブロック図、第2図は従来の
FSK復調回路のブロック図、第3図は本発明の実施例
の周波数配置図である。 1・・・リミッタ回路、2・・・バイナリカウンタ、3
・・・周波数弁別回路、4・・・局部発振器、5・・・
乗算器、6・・・帯域選択フィルタ。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional FSK demodulation circuit, and FIG. 3 is a frequency allocation diagram of an embodiment of the present invention. 1... Limiter circuit, 2... Binary counter, 3
...Frequency discrimination circuit, 4...Local oscillator, 5...
Multiplier, 6...Band selection filter.

Claims (1)

【特許請求の範囲】 1、FSK信号を振幅制限して送出するリミッタ回路と
、該リミッタ回路の送出信号を分周する分周回路と、該
分周回路の分周信号の周波数を弁別してデータのレベル
を示す信号を出力する周波数弁別回路とを備えているこ
とを特徴とするFSK復調回路。 2、前記分周回路は分周用のバイナリカウンタである請
求項1記載のFSK復調回路。
[Claims] 1. A limiter circuit that limits the amplitude of the FSK signal and sends it out, a frequency divider circuit that divides the frequency of the signal sent out by the limiter circuit, and a frequency divider circuit that discriminates the frequency of the divided signal of the frequency divider circuit to generate data An FSK demodulation circuit comprising: a frequency discrimination circuit that outputs a signal indicating the level of the FSK demodulation circuit. 2. The FSK demodulation circuit according to claim 1, wherein the frequency dividing circuit is a binary counter for frequency division.
JP1309390A 1990-01-22 1990-01-22 Fsk demodulating circuit Pending JPH03217147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1309390A JPH03217147A (en) 1990-01-22 1990-01-22 Fsk demodulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1309390A JPH03217147A (en) 1990-01-22 1990-01-22 Fsk demodulating circuit

Publications (1)

Publication Number Publication Date
JPH03217147A true JPH03217147A (en) 1991-09-24

Family

ID=11823548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1309390A Pending JPH03217147A (en) 1990-01-22 1990-01-22 Fsk demodulating circuit

Country Status (1)

Country Link
JP (1) JPH03217147A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494471A (en) * 1972-04-24 1974-01-16
JPS58222645A (en) * 1982-06-18 1983-12-24 Sanyo Electric Co Ltd Fsk demodulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494471A (en) * 1972-04-24 1974-01-16
JPS58222645A (en) * 1982-06-18 1983-12-24 Sanyo Electric Co Ltd Fsk demodulator

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