JPH03215974A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make a store node large enough in capacitance so as to improve a semiconductor memory device in resistance to soft errors by a method wherein a second polysilicon gate is formed on the tops of the gates of a first and a second drive transistor connected to a power supply of a memory cell through the intermediary of a very thin insulating film. CONSTITUTION:A semiconductor memory device of this design is composed of a 1 poly A which forms the gate of a drive transistor, a 2 poly B formed on the gate of the drive transistor, a 3 gate C, and a series capacitor D of a 2 poly and a 3 poly. The 2 poly B is formed on the 1 poly A which forms the gate of the drive transistor through the intermediary of a very thin SiO2 film so as to overlapping the 1 poly A. By this setup, a store node can be made large enough in capacitance and a memory device of this design can be improved in resistance to soft error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, particularly a static RAM.

[Conventional technology]

Figure 3 is a circuit diagram of a conventional memory cell.
is a memory cell, 2a2b is a bit line, (3) is a word line, 4a4b is a drive transistor, 5a5b is a MOS
Load elements constituted by transistors, resistors, etc., 6 is a power supply terminal, 7a7b is an access transistor, 8a8b is a store node of the memory cell 1, and 9 is a bit line load.

Next, regarding the operation of the semiconductor memory device with the above configuration,
As an example, a case will be described in which store nodes 8a and 8b are written to H level and L level, respectively. First, in the case of reading, when the word line 3 is activated, the access transistor 7 storing the L level
b becomes conductive. Therefore, a current flows through the path from the power supply terminal 6 to the bit line load 9, bit line 26, access transistor 7b, and tribe transistor 4b, allowing reading. Furthermore, when data is being held, the parasitic capacitance of store node 8a8b, for example, the gate capacitance or junction capacitance of inverter transistor 4a4b, greatly contributes to data retention.

[Problem to be solved by the invention]

Conventional static RAMs have had the problem that when the memory cell size becomes smaller due to higher integration, the capacity of the store node becomes insufficient, making them susceptible to soft errors.

This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor memory device that is resistant to soft errors by providing a sufficient capacity for storage nodes of memory cells that are becoming smaller. .

[Failure to solve the problem]

The semiconductor memory device according to the present invention has a double structure in the gate portion forming the drive transistor, and the oxide film between the layers is made sufficiently thin to provide storage node capacity and make it resistant to soft errors. It is.

[Effect]

The two gates formed on the gate of the drive transistor in this invention are formed into one gate through a sufficiently thin Sio2 film, so that the capacitance of the toner node (3) connected to the drive transistor can be sufficiently increased. Hold Soft 1 ~ Make it resistant to errors.

(Example) Hereinafter, one example of the present invention will be explained with reference to the drawings.
The figure is a plan view showing a pattern of memory cells of a semiconductor memory device according to an embodiment of the present invention.

In the figure, (A) is 1 polygon forming the gate of the drive transistor, (B) is 2 polygons provided at the gate of the drive transistor in this invention (C) is 3 polygon, (
D) is a direct connection of 2 poly and 3 poly.

In this embodiment, a sufficiently thin Sio2 film is placed over the 1st voltage (A) forming the gate of the transistor.
By providing polygon (B) so as to overlap one polygon (A), the capacity of the store node can be increased and it can be made resistant to soft errors. FIG. 2 is a cross-sectional view of the memory cell of FIG. 1.

〔Effect of the invention〕

(4) As described above, according to the present invention, by forming two gates on the negative and negative sides of the gate of the drive transistor through a sufficiently thin Sio2 film, the store node has sufficient capacity and soft errors can be prevented. A strong semiconductor memory device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor memory device pattern according to an embodiment of the present invention, FIG. 2 is a sectional view of FIG. 1, and FIG. 3 is a circuit diagram of a conventional memory cell. In Figure 1, (A) is 1 poly, (B) is 2 poly, and (C) is 3 poly.
Poly, (D) shows a direct connection connecting 2-poly (B) and 3-poly (C). In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A memory cell of a static RAM accelerator memory includes a first drive transistor for driving a first store node, a second drive transistor for driving a second store node, and a power supply section of the memory cell. A semiconductor memory device comprising a second polysilicon gate connected to the gates of the first and second drive transistors, the second polysilicon gate being formed on the upper surface of the gates of the first and second drive transistors via a sufficiently thin insulating film.