JPH03214812A - Cmos driver circuit for driving external load - Google Patents

Abstract

PURPOSE:To reduce voltage noise by connecting one terminal of a connecting body to which a transistor(TR) or over whose drain and gate are connected in common are connected in series to a line connecting an auxiliary inverter and a main inverter, and the other terminal to a power line. CONSTITUTION:A series connection is provided, in which two TRs 8, 9 whose drain and gate are connected in common are connected in series and the source of the TR 9 located at one terminal is connected to ground. The drain of the TR 8 located at the other terminal of the series connection is connected electrically to a connection line 15 interconnecting a main inverter 13 and an auxiliary inverter 12 through MOSTRs 6, 7 to which a control signal line 17 is connected. MOSTRs 10, 11 form an inverter circuit and the MOSTRs 6, 7 form a transfer gate together with an inverter circuit. When the signal level of the control signal 17 goes to a high level, the transfer gate is set to decrease the voltage noise of a power line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to preventing malfunctions of digital devices due to voltage noise caused by changes in the output of a CMOS driver circuit for driving an external load.

[Conventional technology]

An example of a conventional CMOS driver circuit for driving an external load is shown in FIG. 4, and a timing chart of the same circuit is shown in FIG.

In FIG. 4, (34) is an input signal line, (36) is an output signal line, (22) and (24) are N-channel enhancement type MOS transistors (hereinafter simply MOSTr).
It is written as ), (21) and (23) are P-channel enhancement type MOSTr, and (25) is a load capacitance.

In Fig. 2, (b) shows the signal waveform of the input signal line (34), the signal waveform of the connection line (35) is shown by the chain line (b), and the signal waveform of the output signal line (36) is shown by the chain line (c). Indicated.

The operation of the conventional CMOS driver circuit for driving an external load shown in FIG. 4 will be described below.

As shown in FIG. 4, this CMOS driver circuit for driving an external load is generally composed of two stages: a main inverter (33) and an auxiliary inverter (32).

Transistor channel width (ri) and channel length (l)
) is several times larger in the main inverter (33) than in the auxiliary inverter (32).

From time (70) to time (t1), the input signal line (
The signal at MOSTr(34) is low level, and the signal at MOSTr(
2l) is on, MOSTr (22) is off, the signal on the connection line (35) is high level, MOSTr (23) is off, and MOSTr (22) is off.
(24) is turned on. Therefore, the output signal line (3
The signal 6) becomes low level.

When the signal level of the input signal line (34) changes from low level to high level at time (1+), MOSTr (21
) is off, M O S T r (22) is on, and the signal on the connection line (35) becomes low level, so
MOS T r (23) is on, M O S T r
(24) is in the off state. Therefore, the output signal line (3
The signal 6) becomes high level.

At time (1z), the signal on the input signal line (34) changes from high level to low level, and MOSTr (21) turns on.
Since M O S T r (22) is turned off and the signal on the connection line (35) becomes high level, M O S
T r (23) is off, M O S T r (2
4) is in the on state. Therefore, the signal on the output signal line (36) becomes low level. In this way, the conventional CMOS driver circuit for driving an external load operates.

[Problem to be solved by the invention]

However, in semiconductor integrated circuits, if multiple output terminals that are set to have a high drive capability for external loads, so-called high drive capability output terminals, change simultaneously, voltage noise will occur in the power supply line, causing malfunctions in other digital circuits. There is a problem that it causes

In addition, in order to suppress this noise, there is a method to add a power supply terminal near the output terminals that change simultaneously, but with this method, the number of usable terminals out of the limited number of external terminals is There was also the inconvenience that the number decreased.

(Means for Solving the Problems) In view of the above problems, the present invention includes an auxiliary inverter, a main inverter, a connection line connecting an output terminal of the auxiliary inverter and an input terminal of the main inverter, and a drain and a gate. One end of a series connection body formed by connecting in series one or more transistors connected in common is connected to a switch circuit that controls connection or disconnection between this series connection body and the connection line, and A measure was taken to connect the other end of the connector to the power line.

[For production]

According to the present invention, in a CMOS driver circuit for driving an external load that includes an auxiliary inverter, a main inverter, and a connection line that connects the output terminal of the auxiliary inverter and the input terminal of the main inverter, the drain and the gate are commonly connected. One end of a series connection body formed by connecting one or more transistors in series is connected to a switch circuit that controls connection or disconnection between this series connection body and the connection line, and the other end of this series connection body is Since it is connected to the power supply line, the voltage between the gate and source of the MOSTr of the main inverter can be lowered.

Therefore, the amount of change in the current between the drain and the source over time becomes small, so even if a plurality of output terminals with high drive ability in an integrated circuit or the like change simultaneously, the voltage noise generated in the power supply line becomes small.

(Example) A CMOS driver circuit for driving an external load according to the present invention will be described in detail below with reference to the drawings.

Fig. 1 is a circuit diagram showing an embodiment of the CMOS driver circuit for driving an external load of the present invention, Fig. 2 is a timing chart of the circuit, and Fig. 3 shows the voltage between the gate and source of the MOSTr used in the circuit. FIG. 3 is a relationship diagram of current between drain and source.

This will be explained based on FIGS. 1, 2, and 3 above.

As shown in FIG. 1, the configuration of the CMOS driver circuit for driving an external load of the present invention is that two transistors (8) and (9) whose drains and gates are connected in common are connected in series, and one A series connection body is provided in which the source of the transistor (9) located at one end is grounded, and the drain of the transistor (8) located at the other end of the series connection body is connected to the main inverter (13) by a control signal line (17). ) and the auxiliary imperter (12) to the connecting wire (15).
It is characterized by being electrically connected through r (6) and (7). By the way, as shown in FIG. 3, the voltage-current characteristics of the MOSTr are constant if the geometric dimensions are constant, and in the saturation region, the voltage-current characteristics are constant. ,” (Vcs V
t)'', and in the non-saturated region IoscC(
Vcs Vt ) Vos Vos" / 2. Then, when charging or discharging the load capacitance through the MOSTr, the change in current with respect to time (dl
/dt. ) is this drain-source current (■.,
) is determined. Further, the threshold voltage v7 at which the MOSTr circuit becomes conductive is constant if there is no change in the process. For example, an N-channel MOST operating at 5 volts
If r, it is 1. It is an OV bolt.

The voltage noise (Δ■) due to the inductance component (L) is ΔV=L − d I/d t. Δ■ becomes maximum when the MOSTr changes from off state to on state, and the current (■.,) changes from 0 to IDS in the saturation region.
oc(VcsVT)''.

From the above, if the gate-source voltage (■.,) can be lowered and the current (Ios) can be lowered by some means, the noise (ΔV) due to the inductance component (L) can be reduced.

The present invention utilizes this principle, and the control signal line (
The main inverter (l3) of the drive circuit is activated by the signal of
) by lowering the voltage (■.,) between the sources of the MOSTr (3) (4) (7) MOSTr (I) and lowering the current Has), the change in current (di/dt) is reduced,
This reduces noise due to the inductance component (L) of the power supply line.

Next, the operation of the CMOS driver circuit for driving an external load according to the present invention will be explained based on the circuit diagram shown in FIG.

In the circuit shown in Fig. 1, the drain voltage of M O S T r (9) is (V,), M O S T r (8
) drain voltage (V!), auxiliary inverter (l2)
Let the voltage of the connection line (15) connecting the main inverter (13) and the main inverter (13) be (v3).

Since the drain and gate of M O S T r (8) and (9) are connected, M O S T r
operates in the saturation region.

First, the control signal line (l7) and MO S T r (6)
(7) Oyobi M O S T r (10) (11)
We will explain the circuit consisting of. M O S T r (10) (11) constitutes an inverter circuit, and S T r (6) (7) constitutes a transfer gate together with the above inverter circuit.

When the signal level of the control signal line (l7) is low level,
The transfer gate is turned off. That is, when the signal level of the control signal line (17) is low level, this circuit operates as the conventional external load driving CMO shown in FIG.
It operates exactly the same as the S dryer circuit.

Next, when the signal level of the control signal line (17) is high level, the transfer gate is turned on.

In this state, when the signal waveform (a) shown in Figure 2 is input to the input signal line (l4) of the auxiliary inverter (l2), when the signal level of the input signal line (14) is high level, M O S T r (8) (9) is turned off and the signal (V or O volt) on the connection line (15) becomes.

Also, when the signal level of the input signal line (14) is low level, the threshold voltage of the MOSTr is set to (VT), the MOST
If the variation in threshold voltage due to the pack gate bias effect of r is (ΔVt), then the operating condition of the MOSTr is
. , ≧V, so ■, = V7 , Vz = V3
=Vy +Vr+ΔV, =2Va+ΔvT. As a specific example, the power supply voltage (VDD) is 5.0 volts, the threshold voltage (■7) is 1.5 volts, and the variation (Δ■T) is 1.
．． If it is 0 volts, ■, = 1.5 volts, Vz "'
V:+=4.0 volts.

Next, the N-channel MOST of the main inverter (13)
The gate-source voltage (VCS) of r (4) is the voltage (
Vs) and P channel Mo S T r (
The gate-source voltage (Vcs) of 3) is (V3VD
D). Focusing on the operation of the N-channel MOS Tr, from time (t1) to time (t2), the voltage at the output terminal (16) is equal to the power supply voltage (Vl)D), and MOS Tr (3) is on. Condition, M O S T
r (4) is in the off state. M O at time (t2)
S T r (3) is off state, M O S T r
(4) is turned on. At this time, M.O.S.T.
The gate-source voltage (Vcs) of r (4) changes from (0) to (2VT+ΔVt). Voltage (V,,)
When is (0), the current (hDs) is (0), and when the voltage (■.,) is (2■7+ΔV,), it is in the saturation region, so the current (105) is Inscc (■ .s
Vt )2=(Vt +Δ■a)2.

In the conventional circuit, the gate-source voltage (Vcs) is (0
), the current (I0) is (0) and the voltage ('VG
When s) is (VDD), it is in the saturation region, so the current (Ios) is IDsCC (VGS Vt) 2=
(■.oVt)2. Since the noise voltage (Δ■) due to the inductance (L) is (L-di/dt), if the noise voltage of the conventional circuit is (1), the noise voltage of this embodiment is (Va+ΔV.)'2 /(VDD Vr
)”, which is smaller than before.

To give an example of specific numerical values, Voo=5 volts, Vt
= 1.5 volts, ΔVt = 1.0 volts, the ratio of noise voltage between the conventional circuit and the circuit of this embodiment is 3.5=
It becomes 2.5. That is, the noise voltage due to the inductance generated when discharging the load capacitance (5), assuming that the value in the conventional circuit is (1), is less than 2 in this embodiment.
5/3.5=0.71).

Although this embodiment shows an example in which voltage noise is suppressed by the N-channel MOSTr, the same applies to the P-channel MOSTr.

In this example, an example was shown in which two MOSTr (8) and (9) with their gates and drains connected were connected in order to lower the high level voltage of the connection line (15). Threshold voltage (■a) and MOST
The MOS connected in series depends on the value of threshold voltage variation (ΔVt) due to the pack gate bias effect of r.
Needless to say, the number of Tr's changes.

〔Effect of the invention〕

According to the CMOS driver circuit for driving an external load according to the present invention, voltage noise due to the inductance component of the power supply line at the rise and fall of the signal at the output terminal can be reduced, so that simultaneous changes in a plurality of output terminals in an integrated circuit, etc. Therefore, it is possible to reduce the voltage noise of the power supply line caused by the noise, and it is possible to obtain the effect that malfunction of the digital device can be prevented.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the CMOS driver circuit for driving an external load of the present invention, Fig. 2 is a timing chart of the circuit, and Fig. 3 shows the voltage between the gate and source of the MOSTr used in the circuit. FIG. 4, which is a diagram showing the relationship between the drain and source current, is a conventional CMOS driver circuit for driving an external load. (l2)...Auxiliary inverter, (l3)...Main inverter, (8) (9)...Series connection body, (6) (
7) (10) (11)...Switch circuit, (15
)...connection line, VDD...power line. Figure 1

Claims (1)

[Claims] A series connection consisting of an auxiliary inverter, a main inverter, a connection line connecting the output terminal of the auxiliary inverter and the input terminal of the main inverter, and one or more transistors whose drains and gates are connected in common. For driving an external load, one end of the body is connected to a switch circuit that controls connection or disconnection between the series connection body and the connection line, and the other end of the series connection body is connected to a power supply line. CMOS driver circuit.