JPH03214781A - Semiconductor photodetector - Google Patents

Abstract

PURPOSE:To manufacture a device having the excellent characteristics such as low noise, rapid response, etc., by tilting the substrate surface of an avalanche duplicated photodetector to a specific face orientation. CONSTITUTION:The title semiconductor photodetector is provided with an avalanche duplicated layer comprising a superlattice structure on a semiconductor substrate while the face orientation of the semiconductor substrate is tilted from a face (100) to face (111)-A direction or to an equivalent face orientation with respect to the atomic arrangement or from face (x11)-A (where x represents an integer of 1 or above) to the face orientation (100) or in an equivalent direction, or tilted to any face orientation from the face (y11')-B (where y represents an integer of 1 or above) to an arbitrary face orientation. That is, the steps each being of one atom level are formed stairwise by tilting from the flat face (100). When the vapor phase epitaxy is performed on the substrate, an excellent epitaxial layer is formed through a bonding process of vapor phase atoms adsorbing and migrating on the surface to the step part. Through these procedures low noise and rapid response are achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor light-receiving device, and particularly to an avalanche multiplication type semiconductor light-receiving device that is excellent in low noise and high-speed response.

(Prior art) Conventionally, In0.53GaO lattice-matched on an InP substrate has been used as a semiconductor light-receiving element for optical communication in the wavelength band of 1 to 1.6 μm.
．． A PIN-based semiconductor light-receiving element with a 47AB layer (hereinafter abbreviated as InGaAs layer) as a light absorption layer was published in Electronics Letters.
s) In 1984, Vol. 20, pp. 653-654, avalanche multiplier semiconductor photodetectors were published in IEEE Electron Device Letters (IEEE.
Electron. Device Letters) 1
986, Vol. 7, pp. 257-pp. 258). In particular, avalanche multiplication type semiconductor light receiving elements have been put into practical use for long-distance optical communications because they have an internal gain effect due to avalanche multiplication and high-speed response.

By the way, avalanche multiplication type semiconductor photodetector (hereinafter referred to as
The operating principle of the APD (abbreviated as APD) is to inject photocarriers generated by light absorption into a high electric field region to cause ionization collisions and obtain multiplication characteristics. In this APD, it is known that the noise and high speed response characteristics, which are important in terms of device characteristics, are dominated by the random ionization process of carriers during the multiplication process. Specifically, the greater the difference between the ionization rates of electrons and holes in the InP layer, which is the multiplication layer, the more ionization collisions occur with pure carriers (the ionization rates of electrons and holes are α and p, respectively). Then, a/p>
When p/α>1, holes should be the main carriers that cause ionization collisions. ) Desirable in terms of device characteristics.

However, the ionization rate ratio (p/α) is determined by the physical properties of the material, and for InP, p/α=2 at most. This is significantly different from the Si a/p-20, which has low noise characteristics, and innovative material technology is required to realize even lower noise and high-speed response characteristics.

On the other hand, F. Capasso et al. applied a superlattice structure with large band discontinuities to an avalanche multiplication layer (Appl. Phys. Lett., 40, p.
p. 38-40 (1982)) proposes that the ionization rate ratio can be artificially controlled. Optical communication wavelength band (1
~L611m) against Kay Brennan (K.B.
Rennan) theoretically estimated that by applying an InALAs/InGaAs superlattice system as a multiplication layer, an ionization rate ratio of about a/13-20 could be obtained by the Monte Carlo method. Described in IEE Transactions on Electron Devices. (IEEE. Trans. Electron
Devices, ED-33, pp-1502-1
510 (1986)). In addition, Makita et al. fabricated a prototype InAIAs/InGaAs superlattice APD using MOCVD technology and verified that a/p > 15 (3rd volume of the proceedings of the 50th Japan Society of Applied Physics Academic Conference, 29ZM −
4, Fall 1989).

Avalanche multiplier photodetectors (hereinafter abbreviated as superlattice APD) using these superlattice structures are
There are great expectations as a device that far exceeds As-APD in terms of characteristics.

(Problems to be Solved by the Invention) As the above-mentioned superlattice, when limited to optical communication in the wavelength band of 1 to 1.611 m, the superlattice described by K.
The InAIAs/InGaAs superlattice system proposed by Nnan) can be considered. This superlattice system is located on the valence band side (ΔE
vwO. 2eV), there is a large discontinuity on the conductor side (
ΔEcmO. 5 eV). For this reason, in carriers generated by light, electrons in particular often travel through band discontinuities (superlattice structure regions), making it possible to take in conductor discontinuities as energy, and as a result, the electron ionization collision threshold It becomes possible to effectively reduce energy. Therefore, InAIAs/InGaA
The s superlattice APD has the property of selectively ionizing electrons, that is, increasing the electron ratio. In fact, in experiments by Makita et al., it was verified that the electron ionization rate ratio increases selectively in InAIAs/InGaAs superlattice APDs, and the a/13 ratio is 15 or more, and the above device principle is confirmed. It has become something.

However, the characteristics of current superlattice APDs are similar to that of InAIA.
It is known that it greatly depends on the crystal quality of the s/InGaAs superlattice structure. For example, it has already been reported that InAIAs crystal has a large number of deep trap levels. Furthermore, the quality of the interface between InAIAs and InGaAs is largely related to the controllability of the growth technique, and trap levels via defects at the interface are also expected.

If these trap levels exist in an actual device structure, the following problems will occur.

■An ionization process occurs via the trap level, which contaminates the multiplication process that utilizes the original band discontinuity.

■The dark current increases due to the current generated through the trap level.

In this way, in conventional superlattice APDs, especially InA
There was a problem to be solved regarding the crystal quality of the IAs/InGaAs superlattice structure. SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a superlattice avalanche multiplication type semiconductor light-receiving element having low noise and high-speed response.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems are as follows:
In a semiconductor light-receiving element having an avalanche multiplication layer having a superlattice structure on a semiconductor substrate, the plane orientation of the semiconductor substrate is from the (100) plane to the (111)-A plane direction or a plane direction equivalent thereto in terms of atomic arrangement. Are you leaning towards (
x11)-A side (where X is an integer of X≧1), (100
) Is it tilted in the plane direction or an equivalent plane direction?
It is characterized by being tilted in an arbitrary plane direction from the (yl-d)-B plane (where y is an integer of 1 or more).

Alternatively, in a semiconductor light-receiving element having an avalanche multiplication layer having a superlattice structure on a semiconductor substrate, the semiconductor substrate having an arbitrary plane orientation is tilted by 3° to 10° in an arbitrary plane direction.

(Function) The present invention has solved the problems remaining in the prior art by taking the above-mentioned measures.

In the present invention, the inventors have developed a method using metal organic vapor phase epitaxy (MO
An experiment was conducted to qualitatively understand the crystal quality of the InAIAs/InGaAs superlattice structure using the CVD method. The MOCVD equipment used in this experiment uses a high-frequency heating method to
Heat the P substrate and introduce TMAI ( }limethylaluminum), TEGa ( }ethylgallium), TMIn ( }limethylindium) as group III raw materials, and AsH3 (arsine) gas and PH3 (phosphine) gas as group V raw materials. InAIAs/InGaAs
A superlattice structure has been obtained.

In addition, as a means to qualitatively understand the crystal quality of the InAIAs/InGaAs superlattice structure, I
A nAIAs/InGaAs single well quantum structure (SQW structure) was stacked and evaluated by a 2K photoluminescence method. In this case, it is a well-known evaluation technique that the interface/bulk quality can be estimated by evaluating the photoluminescence half-width with respect to the well layer thickness Lz of the SQW structure.

In general, the factors that increase the half-width in a region where Lz is narrow (Lz < 50 people) include large fluctuations at the interface and I
It is said that this is due to mixed crystal fluctuations in the bulk of nAIAs and InGaAs. In addition, a region where Lz is wide (LZ>5O
The reason for the widening of the half-width in A) is the band filling effect due to the high electron concentration in the well layer. Here, interfacial fluctuations, mixed crystal fluctuations, etc. indirectly suggest the interfacial and bulk quality. Furthermore, the band filling effect is also controlled by the impurity/defect concentration in the bulk and at the interface. Therefore, qualitatively, the narrower the half width, the better the quality of the superlattice structure. Against this background, the present inventors developed InAIAs/InGaA based on the plane orientation of the InP substrate.
The crystal quality of the s superlattice structure was grasped.

FIG. 3 relates to the effect of the invention of claim 1 to solve the problem, and plots the photoluminescence half-width at a temperature of 2 K versus Lz in an InAIAs/InGaAs SQW structure. In this case, the samples include a (100) flat InP substrate surface, an InP substrate surface tilted 2° from the (100) plane toward the (111)-A plane, and (
In inclined at 2° from the 100) plane toward the (111)-B plane
The P substrate surface is used as a parameter. Comparing the crystal quality from this, 2° (111) − from the (ioo) plane
When the crystal is tilted toward the A-plane direction, the half-width is narrow and the crystal quality is good. The tilting angle is not limited to 2 degrees, but any angle of 1.5 degrees or more will be effective.

This result can be explained by the following reason using FIG. Generally, steps having a height of one atomic layer are formed in a stepped manner by tilting from a (100) flat plane. When vapor phase epitaxial growth is performed on such a substrate, the process of adsorption and migration of gas phase atoms (especially group III atoms consisting of Ga, In, and AI here) to the surface and bonding to the step portion is avoided. As a result, a high quality epitaxial layer is formed. In this case, the atomic arrangement in the step is particularly important, and it is sufficient to consider two types of arrangement, one tilted toward the (111)-A plane and the other tilted toward the (xti)-B plane, as shown in Figure 4. It is. Especially here (1
11) When tilted in the -A plane direction, the migrated group III atoms direct their three bonds toward the step site, so the bond is stable in terms of atomic arrangement.

In comparison, when it is tilted to the (uT)-B plane, only two bonds face the step site and it is not stable. Therefore, the quality of the epitaxial layer on the substrate tilted in the (111)-A plane direction is good.

A similar atomic arrangement is the (x11)-A-plane substrate (where X≧1
), when tilted in the direction of the (100) plane, (yl-d)
It is expected that a single B-plane substrate (y≧1) may be tilted in any direction, or may have an equivalent surface orientation relationship. Therefore, similar improvement in crystal quality is possible on a semiconductor substrate using the above-mentioned plane orientation.

In the above action, from (100) plane to (111)-A plane direction, from (x11)-A plane (however, X≧1) to (100)
By using an A substrate tilted in any plane direction from (y11)-B plane (y≧1), InGaAs
The crystal quality of the /InAIAs superlattice structure is improved, and excellent device characteristics of the superlattice APD can be obtained.

FIG. 5 describes the operation of the invention according to claim 2, and shows the Lz dependence of the photoluminescence half-width when the angle of the substrate surface orientation is changed in the InAIAs/InGaAs 8QW structure. In this case, (ioo)
00, 2°, 3°, 6°, 1 from the (110) plane
A comparison is made by using an InP substrate tilted by 0°. It can be seen from this that the photoluminescence half-width is reduced by tilting it by 3 degrees or more.

This result can be explained by the following reason using FIG. 6, which shows the diffusion (migration) of atoms on the terrace of the step. The aforementioned? The length 1 of the step caused by tilting the plate orientation is generally expressed by the following equation.

1=4 a■ cot(θ). ．． ．． ．．
．． ．． ．． ．． ．． (1) where aQ is a lattice constant and θ is an off angle. In order to form a high-quality epitaxial layer, it is an important process that Group III atoms migrate to the step portion and stably bond, as described above.

By the way, the possible migration distance λ is determined by the physical properties inherent to atoms.

Here, if λ×l as shown in Fig. 6 (Fig. 6 (
Corresponding to b)), the probability that a group III atom will arrive at a step becomes smaller, and clusters and clusters randomly occur outside of the step.
It may cause island-like growth, and a decrease in crystal quality is expected. As shown in equation (1), the step length 1 becomes smaller as the off angle becomes larger. By increasing θ, the region of λ〉■ (corresponds to Fig. 6 (a))
In contrast, group III atoms can be stably supplied to the step through migration, so that crystal quality can be improved. In particular, in the present invention, the (11
0) When tilted in the plane direction, 3 degrees or more (11) The experiment shown in Figure 5 qualitatively shows that tilting is effective. In this experiment, the upper limit of the off-angle was set to 10°, and the crystal quality was not inferior in any way.

This effect is the same for other substrate surface orientations, and by tilting the substrate surface by 3° to 10°, it is possible to improve the quality of the superlattice structure, resulting in better device characteristics. Superlattice APD becomes possible.

As described above, by tilting the substrate surface in a certain plane direction, or by tilting it in an arbitrary plane direction by 3° to 10°, it is expected that crystal quality will be improved due to different effects. In the present invention, such an effect is confirmed by the MOCVD method, but a similar effect can be obtained using other vapor phase growth methods such as MBE (Molecular Beam Epitaxy).
) method, gas source MBE method, and MO-MBE method.

(Example) Examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a structural sectional view of an avalanche multiplication deaf light receiving element having a superlattice structure formed (12) according to an embodiment of the present invention. The structure of this example is n-type I
An n-inch InP buffer layer 2 is formed on an nP substrate 1 with a superlattice structure (
an n-type multiplication layer 3 made of InAIAs/InGaAs);
n-type InGaAs light absorption layer 4, nlInP cap layer 5
are sequentially laminated by the MOCVD method. Then P
A + light-receiving region 6 and a P- guard ring region 7 are formed by a diffusion method, and a passivation film 8 and electrodes 9 and 10 are formed.
The device structure is obtained by forming . Here In
The P substrate 1 is made from the (100) plane of the present invention and has a (111) plane.
- The substrate is tilted toward the A plane, and the (11
0) The former and the latter correspond to the invention of claim 1 and claim 2, respectively, in which both were manufactured using substrates tilted by 3 degrees in the plane direction.

In the structure shown in FIG. 1, light incident from the P+ light-receiving region 6 is absorbed in the InGaAs light-absorbing layer 4 to generate electron-hole pairs. In this, electrons are injected into the avalanche multiplication layer 3 having a superlattice structure by a reverse electric field. Electrons easily reach ionizing collisions by taking in large conduction band discontinuities (ΔEcwO.5 eV) as energy in the InAIAs/InGaAs superlattice structure. Therefore, the ionization rate of electrons increases, and the ionization rate ratio a
/13 will be exaggerated.

Here, by selecting the substrate surface as in this embodiment, the quality of the superlattice structure can be improved as shown in the operation. Therefore, the device characteristics of the superlattice APD are improved.

FIG. 2 shows the voltage differences between the superlattice APD obtained by the present invention ((a), (b) in FIG. 2) and the superlattice APD obtained by the conventional technique ((C) in FIG. 2). Indicates dark current characteristics. Here, (a) is (111)-A from the (100) plane
Using one substrate tilted to the surface, (b) is (100)
(c) uses a (100) flat InP substrate.

In general, dark current is greatly affected by the crystal quality.
In particular, when there is a defect in the bulk or interface, it contributes as a generated current in the low voltage region to form a trap level. In FIG. 2, the dark current of all superlattice APDs according to the present invention is reduced by about 17100 in the low voltage region compared to the conventional technology. This indicates that the quality of the superlattice structure according to the present invention is good.

As described above, by using the method of the present invention, the superlattice structure InAIAs/
An avalanche multiplication type light receiving element using InGaAs as a multiplication layer becomes possible.

Note that from the (100) plane to the (1
11) In the case of a substrate tilted to the -A plane, the tilt angle should be 1.5° or more.

In addition, in this embodiment, a substrate is tilted in the (100) plane direction or an equivalent direction from the (x11)-A plane in claim 1, and a substrate is tilted in an arbitrary plane direction from the (yli)-B plane. Although not shown, it is thought that there is a similar effect of improving the quality of the crystal as described in the section of the effect, and when applied to a device, the same effect as this example can be obtained.

(Effects of the Invention) As explained above, the avalanche multiplication type light-receiving element obtained by the present invention can be made by tilting the substrate surface in a specific plane direction or by optimizing the tilt angle (16). Improving quality makes it possible to improve device characteristics.

In particular, by applying the present invention to a light receiving element having a superlattice structure, a device excellent in low noise and high speed response can be obtained.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of an avalanche multiplication type light receiving element according to an embodiment of the present invention. Figure 2 shows the superlattice A of the present invention and the conventional one.
A voltage-dark current characteristic diagram of a PD. Figure 3 shows InAIAs/I
FIG. 3 is a diagram showing the dependence of photoluminescence half-width on well layer thickness in an nGaAs SQW structure. FIG. 4 is a diagram showing an atomic arrangement in a step region to explain the effect of the present invention. Figure 5 shows InAIAs/InGaAs
FIG. 3 is a diagram showing the dependence of the photoluminescence half-width on the well layer pressure in the SQW structure. FIG. 6 is a diagram showing the migration of atoms on the terrace of steps. In each figure, 1.nWInP substrate ((111)-A from (100) plane
A substrate tilted in the plane direction or a (110
) Substrate tilted by 3 degrees in the plane direction), 2...n-InP buffer layer, 3...n-type (16) InAIAs/InGaAs superlattice structure (avalanche multiplication layer), 4... n-type InGaAs light absorption layer, 5...
・N-type InP cap layer, 6...P+1 light-receiving region, 7
...P--guard ring region, 8...passivation film, 9...P-side ohmic electrode, 10...n
Side ohmic electrode.

Claims (2)

[Claims] (1) In a semiconductor light-receiving element having an avalanche multiplication layer having a superlattice structure on a semiconductor substrate, the plane orientation of the semiconductor substrate is from the (100) plane to the (111)-A plane or equivalently in terms of atomic arrangement. Is it tilted in the direction of the plane, or is it tilted to (1
00) A semiconductor light-receiving element characterized by being tilted in a plane direction or a direction equivalent thereto, or in an arbitrary plane direction from the (y1@1@)-B plane (where y is an integer of 1 or more). (2) A semiconductor light-receiving element having an avalanche multiplication layer having a superlattice structure on a semiconductor substrate, characterized in that the semiconductor substrate having an arbitrary plane orientation is tilted by 3° to 10° in an arbitrary plane direction. Semiconductor photodetector.