JPH03214263A - Fast backward searching method for wiring processing - Google Patents

Abstract

PURPOSE:To increase the processing speed in the backward search of a maze method by making use effectively of the pipeline processing. CONSTITUTION:The value of '1' of a search flag is sequentially sent to the PEs taking charge of the contiguous grids on a retrieving path for each action of a means 8 in a backward search covering a target T of 8-h through source S of 3-h. When the value of '1' of the source flag reaches a source grid, an AND obtained between the search flag set to the source grid and a source flag is set at '1'. This fact is judged by a controller, etc. The action of the means 8 is repeated in a pipeline system until the judging result of the controller is equal to '1' and before the controller judges the OR of a means 9 is equal to '1' with all PEs. Thus the backward search processing speed is increased.

Description

[Detailed Description of the Invention] [Summary] A backward search that traces the wire attached from the starting point of the wiring toward the target point in the reverse direction from the target point in the forward search.
Regarding a high-speed backward search method in wiring processing that effectively uses pipeline processing to speed up wiring processing, a PE in charge of each grid in backward search can send a label to a PE in charge of an adjacent grid without waiting for the controller's decision. The aim is to speed up the backward search process by repeating the process of transmitting the data simultaneously as a pipeline process. In a wiring process executed by a computer by associating each PE with one-to-one correspondence to grids and grids on a lattice graph, the plurality of PEs
A 4-bit arrow flag indicating whether the label attached from the starting point of the wiring has been transmitted in the forward search is up, down, left or right, and an l-bit search flag indicating whether the backward search has already been performed. , is provided with a 1-bit source flag indicating whether or not it is the starting point, and as the arrow flag, all O's are set for the PE in charge of the starting point, and the above in the forward search is set for all PEs other than the PE. The value is 1 for the direction in which the label is transmitted and 0 for the other directions.
Also, as the search flag, the PE in charge of the wiring target point
1 for , O for all PEs other than this PE,
Also, as the source flag, the PE in charge of the starting point
42, O is set for all PHs other than the PE, and all PEs perform a logical product between each bit of the arrow flag of their own PE and the search flag, and use the result as the arrow flag. It is sent as a new search flag candidate value to the adjacent PE in the direction corresponding to each bit of The operation to set the value to is repeated by pipeline processing, and every PE in each operation outputs the logical product of its own PE's new search flag and the source flag, and the logical sum of this output for all PEs is 1.
The configuration is such that the repetition of the above-mentioned operation ends when .

(Industrial Application Field) The present invention relates to a search method for wiring patterns of printed circuit boards and LSIs, and more specifically, in forward search, the label attached from the starting point of the wiring toward the target point is traced backward from the target point. This invention relates to a high-speed backward search method in wiring processing that speeds up backward search by effectively utilizing pipeline processing.

As the density of wiring targets increases, the amount of data handled increases, and faster wiring processing is required.

In response to this, attempts are being made to speed up processing through parallel processing. In other words, one of the basic algorithms for wiring processing
In an attempt to parallelize the maze method, the grid, which is the unit of the wiring area, is allocated one-to-one to the processors (PEs) in the processor array with communication ports tangent to them, and the wavefront in the forward search is A method for operating PEs in parallel has been devised. However, the backward search of the maze method still uses a sequential processing method, and it is desired to speed up the backward search processing in order to increase the speed of the wiring system as a whole.

[Conventional technology]

The maze method, which is widely used as a method for processing wiring for printed circuit boards and LSIs, is an algorithm that attempts to find the shortest route for wiring on a grid graph. In the maze method, starting point (source) S on the grid graph is the starting point (0 label),
Search the grid points in the order in which the wavefront spreads, give the distance from the starting point as a label value, and when you arrive at the target point T, depart while tracing the grid points in the direction in which the label value decreases one by one. By returning to the point
One wiring route is determined.

In the maze algorithm, in order to save the memory of the bitmap representing the state of the label of each grid point, the label may be represented by an arrow instead of being given as a distance from the source. FIG. 9 shows an example of the labels in each grid after the labeling from the source to the target has been completed, that is, after the forward search is completed. In the figure, 3,000 is the source and 8-chi is the target.

First, four grids adjacent to the 3-chi source, ie, 3-chi, 3-chi, 4-chi, and 2-chi, are marked with arrows pointing toward the source. Next, to grid 3- adjacent to these four grids, 2-
Each of the 1st, 4th, 1st, 5th, 2nd, and 4th is marked with an arrow pointing toward the grid that is already marked with an arrow. Here, if there are two adjacent grids with arrows already attached, for example, the left and right direction will be given priority for the 2-t grid,
The second mark is marked with a rightward arrow. Labeling is subsequently performed on grids other than the wiring prohibited area one after another, and the forward search process ends when a label is added to the target.

FIG. 10 is an example of a bus searched by a backward search for determining a wiring route by retracing the labels attached in the forward search of FIG. In the same figure, the backward search is 8-
Since the direction of the label attached to this grid is to the left, the next grid to be traced is 9-chi, which is one place to the right. Also 9-
Since the arrow attached to the grid also points to the right, the grid 10-chi further to the right is traced. In this way, the grid is sequentially traced until the source 3-chi is reached, resulting in a bus as shown in FIG.

In such backward search processing, parallel computers, such as S
When using an IMD type computer, a grid-like PE array in which processor elements (PEs) are allocated one-to-one corresponding to each grid is controlled by one controller, but in the past, A method has been used in which the controller determines the most recently traced grid (the label for the current PE, that is, the direction of the arrow) and determines the next grid to trace.

[Problem to be solved by the invention]

As described above, in the conventional backward search method, the next trace processing cannot be performed until the controller determines the label value for the PE in charge of the most recently traced grid, and the parallelism of the PE array cannot be utilized. The problem was that there was no.

If the number of PEOs on the PE array is very large, it may take a considerable amount of time for the controller to determine the value of the label for the PE responsible for the most recently traversed grid. For example, it takes 20 bits (
If it takes a long time (operation), it will take 20 bits for each process to perform backward searches one after another. Therefore, in order to trace n grids, n×
There was a problem in that it required 20 bits of time.

In the present invention, the PE in charge of each grid in backward search
The present invention aims to speed up the backward search process by repeating the process of simultaneously transmitting labels to the PEs in charge of adjacent grids as a pipeline process without waiting for the controller's decision.

[Means and operations for solving the problems] FIG. 1 is a functional block diagram of the present invention. The figure shows a parallel computer with a PE array in which communication ports of multiple processor elements (PE) are connected in a grid, such as SIMD (Single Instruction Multiple Data Stream).
FIG. 2 is a functional block diagram of a high-speed backward search method in maze method processing as a basic algorithm for wiring processing, which is executed by associating each PE with a grid on a lattice graph in one-to-one correspondence using a lattice type computer.

In Figure 1, a 4-bit arrow flag indicating whether the direction in which the label attached from the starting point of the wiring toward the target point is transmitted in the forward search to all multiple PEs at 6 is up, down, left, or right. , a 1-bit search flag indicating whether the grid that the PE is in charge of has already been searched backwards, and a 1-bit source flag indicating whether or not it is the starting point for wiring. Here, the arrow flag is set to 1 only in the direction in which the label is transmitted out of the 4 directions (up, down, left, right),
The remaining three directions are O. For example, each of the four bits indicates four directions from the top, top, bottom, left, and right, and if the label is transmitted from the left grid, the arrow flag is 0.
It is assumed to be 001.

Then, in step 7, each flag is set. In other words, the arrow flags are all 0 for the PE responsible for the starting point of the wiring, and 1 for all other PEs, indicating the direction in which the label was transmitted during forward search, as described above.
The other direction is O.

Next, the search flag is set to 1 for the PE in charge of the target point of the wiring, O is set to all other PEs, and the source flag is set to 1 for the PE in charge of the starting point of the wiring. , O is set for all other PEs.

Next, in step 8, all PEs constituting the PE array perform a logical AND operation between each of the four arrow flag bits of their own PE and the [search flag] bit, and use the result in the direction corresponding to each bit of the arrow flag. A new search flag candidate value is sent to neighboring PEs, and the PE that receives the candidate value
The operation is repeated in which the logical sum of the candidate value and the value of the search flag held by the PE itself is set as the new value of the search flag.

For example, in FIG. 10, the search flag of the 8-chi target grid is 1, and the arrow flag is 0010, so the AND of each bit of the arrow flag and the search flag is 00.
10, and the candidate value of the search flag sent to the right adjacent PE is 1. Therefore, the adjacent PEs on the right are 9
- For the PE in charge of the grid of
Regardless of the search flag candidate values (actually all 0) sent from the 9-th, 10-th, and 9-th grid grids, the new search flag value of the PE for the 9-thousand grid is 1. The operation in which all PEs send the result of the logical product of the arrow flag and the search flag to an adjacent PE as a new search flag value is repeated one after another in a vibrating manner.

For each operation in step 8, all PEs output the logical product of the new search flag value for their own PE and the source flag set in step 7, and the logical sum of the output for all PEs is determined by 9. When the controller of the SIMD computer, for example, determines that the logical sum becomes 1, the repetition of the operation in step 8 is terminated.

That is, in Fig. 10, from the 8-chi target to the 3
- In the backward search up to the source of the grid, the value of 1 of the search flag is transmitted one after another on the search bus to the PEs in charge of adjacent grids for every operation of 8 in FIG. At this point, the logical product of the search flag for the source grid and the source flag becomes 1, which is determined by, for example, the controller.

The operation at 8 in FIG. 1 is repeated one after another in pipeline 2 in all PEs until the determination result becomes 1, before the controller determines that the logical sum at 9 is 1. This makes it possible to speed up the backward search process.

〔Example〕

FIG. 2 is a block diagram of the overall configuration of a parallel computer system using the backward search method of the present invention. In the figure, the system includes a PE array 10 in which communication ports of a plurality of processor elements (PEs) are connected in a lattice, each of which is equipped with a memory that holds necessary data and an arithmetic unit that executes operations on the data. A collection arithmetic circuit 11 performs operations such as logical sum, logical product, and addition on the outputs of each PE constituting the PE array 10 and collects the results, and the arithmetic results of the collection arithmetic circuit 11 and the PE array 10 are configured. All PE
Global memory 12, PE array 10 and global memory 1 that hold data to be broadcast to
It consists of a controller 13 for controlling 2.

In order to explain in detail the operation of the acquisition arithmetic circuit 11 in FIG. 2, FIG. 3 shows the entire system in FIG. 2 again, focusing on its configuration. In the figure, the collection arithmetic circuit 11 is composed of arithmetic control registers 15A to 15D and collection arithmetic circuits GLU16A to 16D. Inside the controller 13, there is a control memory 19 in which microinstructions including output control signal data, etc. are stored. Via the signal line 18, the control register 15A in the acquisition arithmetic circuit 11
A control signal is outputted to 15D through the arithmetic control signal line 17. The collection calculation circuits 16A to 16D are circuits that perform a process of collecting output data from each processor 14 to the stove 13. As shown in Figure 3,
They are connected in a tree structure, and each collection calculation circuit 16A in the first stage inputs the output data of several processors (PE) 14, and sends the calculation results based on the input to the collection calculation circuit 16B in the second stage. Output. Similarly, data is collected from the second stage to the third stage, from the third stage to the fourth stage, and in this example, the collection calculation circuit 16D is the final stage. The final stage collection arithmetic circuit 16D collects the results of the outputs of all the processors 14 into the global memory 1 of the controller 13.
Not sent to 2.

These circuits are grouped according to the number of stages in the tree structure, and each group is provided with arithmetic control registers 15A to 150 that supply arithmetic control signals.

The calculation control register 15A sends the same calculation control signal to each collection calculation circuit 16A belonging to the first group. The next stage arithmetic control register 15B sends an arithmetic control signal to each acquisition arithmetic circuit 16B. The same applies hereafter.

The arithmetic control registers 15A to 15D are connected in series by a pipeline corresponding to the number of stages in the tree structure, and the arithmetic control signals set in the registers are transmitted from the controller 13 via the arithmetic control signal line 17 in response to a predetermined clock. will be sent. Therefore, for example, when an addition instruction control signal is set in the arithmetic control register 15A, the collection arithmetic circuit 16A
performs addition of the output data of each processor 14, and outputs the result to the collection calculation circuit 16B at the next stage. At the next clock, the addition instruction in the arithmetic control register 15A is transferred to the arithmetic control register 15B, and the collection arithmetic circuit 16B similarly executes the addition operation. The calculations under pipeline control proceed in this way, and finally, when the collection calculation circuit 16D performs addition according to the addition instruction set in the calculation control register 15D, the result is written to the global memory 12 of the controller 13. It will be done.

In addition, when the controller 13 synchronizes the processing instructed to all the processors 144, it outputs "1" through the processor control signal line 18 when the processing in each processor 14 is completed. Instruct Proce Nosa 14 to do so.

Then, a control signal instructing an AND logic operation is sent to the operation control signal line 17.

When an AND logic operation signal is sent to the operation control register 15A, the first stage collection operation circuit 16A executes an AND logic operation on the outputs of each processor 14. At the next clock, the second-stage acquisition calculation circuit 16B similarly performs an AND logic operation. In this way, the pipeline control is advanced, and when the final stage collection calculation circuit 16D executes the AND logical operation, if the result is "1", the controller 13 determines that all the processors 14 output "1". You can recognize that.

In addition, in the present invention, the collection arithmetic circuit 11 is used only for the purpose of calculating the logical sum of the outputs of the processor 14, as will be described later, and the circuits 16A to 16D can be simply configured by combining, for example, a NOR circuit and a NAND circuit. be able to.

FIG. 4 is an example of the search flag, arrow flag, and source flag in the present invention. In the figure, each flag is set for each PE that constitutes the PE array 10 in Figure 2, and the value of the search flag ■ is 1 for the PE in charge of the target, and 1 for the other PEs. is O, and then the value of the arrow flag that indicates the direction in which the label was transmitted in the forward search among the four directions (up, down, left, and right) is 1. Only the direction in which the label was transmitted is 1, and the remaining 3 directions are O.
is set to The four bits of the arrow flag indicate the upper, lower, left, and right directions, and if the label is transmitted from the left direction, the arrow flag becomes 0001. However, the values of the arrow flags for the PE in charge of the source are all set to O. Furthermore, the source flag (2) is set to 1 for the PE that is once assigned the source, and 0 for the other PEs.

FIG. 5 is a flowchart of an embodiment of forward search in wiring processing. In the figure, when the forward search process is started, first, in S20, the values of the arrow flag, search flag, and source flag for each PE are cleared, that is, all are set to O as an initialization process. Then, in S21, the value of the source flag is set to 1 only for the PE in charge of the source,
Further, in S22, the value of the search flag is set to 1 only for the PE in charge of the target.

In S23, label propagation is performed. That is, all PEs that are not on the wiring prohibited area and whose arrow flags are in a clear state perform a process of setting a flag for an adjacent PE whose arrow flag is not in a clear state as the value of the arrow flag for its own PE. However, if there are two or more adjacent PEs whose arrow flags are not cleared, the value of the arrow flag is determined based on the priority (for example, left/right direction). Next, in step 324, forward search is performed to determine whether the label has reached the target. In order to determine whether or not the forward search can be terminated, the arrow flag for the target is read. That is, the PE whose search flag is 1 outputs the value of the 4 bits of the arrow flag one bit at a time to the collection calculation circuit 11 in FIG. 2, and the other PEs output oooo to 1.
Output bit by bit. The logical sum of the output values of all PEs is 1
The value of the arrow flag at the target is stored in the global memory 12 by being taken bit by bit synchronously by the acquisition calculation circuit 11, and is read out by the controller 13.

Then, in S25, it is determined whether the arrow flag is in a clear state, and if it is in a clear state, it means that the label has not yet reached the target in the forward search process, so the processes from S23 onwards are repeated. , S25
The forward search process ends when it is determined that the arrow flag of the target is not in the clear state. Note that in this flowchart, to simplify the explanation, the process of detecting when wiring is impossible is omitted.

FIG. 6 is an example of the results of forward search processing.

The same figure (al shows the state in which the label attached from the source S at the position of low C has reached the target T at knee a.Here, the arrow at T has priority in the left and right direction as described above. Therefore, it is facing left.

FIG. 6fb) shows the values of the search flag, arrow flag, and source flag in each PE corresponding to fa) in FIG. In the figure, the search flag is set to 1 only for the PE in charge of the target, and the source flag is set to 1 only for the PE in charge of the source. Further, the arrow flag is oooo for the PE in charge of the source, but for other PEs it has values corresponding to the arrows in fa+.

FIG. 7 is a flowchart of an embodiment of backward search processing. In the figure, in S26, each of the 4 arrow flag bits in its own PE is ANDed with 1 bit of the search flag in all PEs, and the result is assigned to the search flag candidate in the adjacent PE in the direction corresponding to the arrow flag. It is conveyed as a value, i.e. a temporal flag. The PE on the receiving side will receive temporal flags from PEs in four directions: top, bottom, left, and right, but each time it receives each flag, for example, one bit at a time, it will logically OR it with the search flag held in its own PE. A new search flag value for each PE is determined by taking . And all PEs are S
At step 27, the value of the new search flag and the source flag are ANDed and the result is output to the collection calculation circuit 11 in FIG. , the result is written to the global memory 12. In S29, the controller 13 determines whether the value is 1 or not, and when the value becomes 1, all processing ends.

Note that the transmission of the new search flag value to the adjacent PE in S26 is performed by inter-processor communication.

In other words, each PE constituting the PE array 10 in FIG. 2 uses communication ports connected in a grid pattern to
It has the ability to communicate with E. This communication cannot be performed in all four directions at the same time; since it is a SIMD type, for example, all PEs communicate in the upward direction for 1 bit, then in the downward, left, and right directions. Communication takes time for each bit.

What is important in FIG. 7 is that the process in S26 is performed in S29.
Without waiting for the determination result of the value of the global memory 12 by the controller 13 in step 327, the new search flag value and the source flag are logically ANDed in each PE in step 327 and then repeated in pipeline 2 one after another. be. Since this process is pipelined by hardware, it is repeated one after another without waiting for the determination result in S29.

The path containing the grid to which I is passed as the new search flag becomes the bus to be searched. Finally, when I is transmitted as the new search flag value to the PE in charge of the source grid, the AND of the search flag for the source and the source flag at 327 becomes 1, and the result is 328
The data is written to the global memory in S29, and the process finally ends when it is determined in S29 that the value in the global memory has become 1. That is, as long as the value of the global memory is not 1 in S29, the process in S26 is continued.

Note that even after the search flag for the source becomes 1, the process of S26 will continue for a while.
The values of the arrow flags for the source are all O, and the search flags will not be rewritten after the backward search reaches the source, so no particular problem occurs.

FIG. 8 is a time chart of an embodiment of backward search processing according to the present invention. In the same figure, S26 to S in FIG.
The processing up to 29. is considered as one unit, and depending on the number of stages of the acquisition calculation circuits 16A to 16D in FIG. 3, for example, 1
Even if the time required to process one is 20 bits, 526
The time required is 4 times, excluding the 1 bit required for the controller 13 to command all PEs at the start of the backward search.
1 bit each to transmit the value of the temporal flag to the neighboring PEs on the upper, lower, left, and right sides, and 1 bit each to OR the transmitted temporal flag value and the search flag held to create a new search flag value. bit, totaling 8 bits, S
Adding 1 bit for ANDing the new search flag and the source flag in step 27, the tracing of the grid in the backward search is performed one after another in a time of 9 bits and 7 bits.

Therefore, the processing time can be significantly reduced compared to the conventional case in which the controller 13 determines the grid to be traced next after 20 bits of time and then performs tracing again. In other words, in the conventional method in which the second trace process is started after all the first trace processes are completed, it takes 20Xn bits of time to execute 0 processes, whereas in FIG. (1+9Xn
+11) bit time is required.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by effectively utilizing pipeline processing in the backward search of the maze method, it is possible to dramatically speed up the processing.
This greatly contributes to speeding up the wiring system as a whole.

[Brief explanation of drawings]

Figure 1 is a functional block diagram of the present invention. Figure 2 is a block diagram of the overall configuration of a parallel computer system using the backward search method of the present invention. Figure 3 is the overall configuration of a parallel computer system centered on the configuration of the collection operation circuit. 4 is a diagram showing an example of the search flag, arrow flag, and source flag for each processor element (PE); FIG. 5 is a flowchart of an example of forward search processing; FIG. 7 is a diagram showing an example of the label and each flag at the end of forward search, FIG. 7 is a flowchart of an example of backward search processing, FIG. 8 is a diagram showing a time chart of an example of backward search processing, FIG. 9 is a diagram showing an example of labels added in the forward search, and FIG. 10 is a diagram showing an example of buses searched by the backward search. DESCRIPTION OF SYMBOLS 10... Processor element (PE) array, 11... Collection arithmetic circuit, 12... Global memory, 13... Controller,

Claims (1)

[Claims] Executed by a parallel computer having a PE array in which communication ports of a plurality of processor elements (PEs) are connected in a lattice shape, each PE is made to correspond one-to-one to a grid on a lattice graph. In the wiring process, all of the plurality of PEs are provided with a 4-bit arrow flag indicating whether the direction in which the label attached from the starting point of the wiring has been transmitted in the forward search is up, down, left, or right, and whether the backward search has already been performed. (6)
, As the arrow flag, set all 0 for the PE in charge of the starting point, set 1 for the direction in which the label was transmitted in the forward search for all PEs other than this PE, and set 0 for other directions. The search flag is 1 for the PE in charge of the target point of the wiring, 0 for all PEs other than this PE, and the source flag is 1 for the PE in charge of the starting point. , all PEs other than this PE
is set to 0 (7), and all PEs perform a logical AND operation between each bit of the arrow flag of their own PE and the search flag, and use the result in the direction corresponding to each bit of the arrow flag. A pipeline process is performed in which a new search flag candidate value is sent to an adjacent PE as a new search flag candidate value, and the PE that receives the candidate value sets the logical sum of the candidate value and the search flag held by its own PE as the new search flag value. Repeatedly (8), all the PEs for each time of the operation output the logical product of the new search flag of its own PE and the source flag, and when the logical sum of the output for all PEs becomes 1, the above A high-speed backward search method in wiring processing characterized by terminating repetition of operations (9).