JPH03214235A - Parallel processing method for plural paths - Google Patents

Abstract

PURPOSE:To extract the 100% parallelism out of a relevant program by preparing plural instruction taking-out parts. CONSTITUTION:When a breakup instruction is executed by a processing system, the instruction take-out means of other processing systems have accesses to an instruction cache memory 101 based on an instruction address set by a breakup instruction or an instruction address that is already set. Thus, the parallel processing can be carried on in each processing system despite an internal branching occurred in an instruction train during processing at each side. Meanwhile it is required again to select one of those processing systems that start their actions independently of each other. In such conditions, a merging instruction is executed by a single instruction executing means 105 (107). Thus, the actions of the instruction taking-out means of other processing systems are stopped. Then the operation of the means 105 (107) is also stopped. Consequently, the branching instructions themselves can also be executed in parallel with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-pass parallel processing method for simultaneously processing a plurality of instructions.

[Prior Art] An example of a processing device that executes multiple instructions simultaneously in order to speed up arithmetic processing is disclosed in Japanese Patent Laid-Open No. 63-4984.
No. 3, US Pat. No. 4,766, 566, and European Patent No. 871.10751.2, and these patents have the same contents filed in various countries. The claim in this patent application is a parallelization method recently called superscan, in which two instructions with consecutive addresses are executed at the same time. Fj (<, 2
7, two instructions to be executed simultaneously are stored in a single instruction buffer, and are executed simultaneously. In this method, since consecutive instructions cannot be executed when a branch occurs, when a branch instruction is executed in one execution unit, the instruction buffer is canceled to perform processing when a branch occurs.

[Problems to be Solved by the Invention] The above-mentioned conventional technology has a problem in that the degree of parallelism essentially decreases due to the one-branch instruction. That is, the instruction buffer is canceled by the branch instruction of one execution unit 1-, and at this time the two execution units cannot operate independently. Therefore, the range to be optimized when extracting the degree of parallelism of instructions is limited to only between the entry and the branch instruction. Here, the entry refers to the destination of a branch instruction or the instruction immediately after the branch instruction. It is said that a branch instruction appears once in every five instructions, and optimization has little meaning in this state. Even though twice as much hardware is used, the effect of performance improvement due to simultaneous execution of two instructions is small or almost non-existent.

The first object of the present invention is to solve the problem of the decrease in the degree of parallelism caused by branch instructions, and to provide multiple paths M that can also parallelize the branch instructions themselves.
To provide a single column processing method.

Means for Solving the Problem] In order to achieve the object described in 1, the present invention provides a processing system that can operate independently of each other, consisting of an instruction fetching means, a decoding means, and an instruction execution means arranged in a pipeline. A plurality of systems are provided, and when one processing system executes the instruction, there are split instructions and fusion instructions to start and stop the operation of other processing systems, and a flag indicating how far the instruction execution has progressed. , and a conditional pause instruction that controls the execution of instructions by each processing system by referring to the flag.

C action] When a splitting instruction is executed by one processing system, the instruction retrieval means of the other processing system accesses the instruction cache memory according to the instruction address set by the splitting instruction or the instruction address that has already been set. do. As a result, each instruction fetching means has a different program counter, so they basically operate independently, so even if there is a branch within the instruction string being processed on each side, parallel processing in each processing system is possible. can continue.

On the other hand, there also arises a need to narrow down the processing systems that have started operating independently in this way to one again. At this time, by executing the fused instruction by one instruction execution means, the operation of the instruction fetching means of the other processing system is stopped. Along with this, the instruction execution means is also stopped. In other words, the pipeline is narrowed down. A pipeline stopped by a fusion instruction can be restarted only by a split instruction from an active pipeline or by a timer check mechanism that is performed at regular intervals.

If there is a data dependency between the processes of two processing systems, an instruction for controlling the execution order, that is, a conditional pause instruction, is embedded in the execution code according to the execution order information possessed by the compiler. Each processing path of a plurality of processing systems has a synchronization flag, and the value of these flags can be increased by a splitting instruction. Then, the conditional pause instruction determines whether or not to wait for the next process based on the contents of the flags of each processing system and the processing result of its own processing system at that time, and after the necessary data is obtained, the relevant process is executed. Execution control of each processing system is performed to ensure that the processing is executed properly.

[Example] Hereinafter, one example of the present invention will be described in detail. FIG. 1 is a block diagram of a processor to which the present invention is applied. Each of the instruction fetch units 100 and 102 has a program counter that operates independently, and has a 4g signal line 1.
11 and 112 are used to issue an instruction fetch request to the instruction cache memory January 01.

The cache memo IJIOI accepts one of these alternately or both at the same time. If the corresponding data are accepted at the same time, they remain as they are; if they are accepted alternately, they are buffered inside the cache memory 101, and are transferred to the signal lines 114 and 115 for each cycle.
Output to. Control blocks +03 and 104, each consisting of a decoder and a sequencer that can operate independently, execute the following instruction execution units using signal lines +18 and 119 based on information obtained by decoding instructions from the cache memory 101. The signal lines 113 and 1.16 and the data lines 122 and 1 are controlled in parallel and based on information such as branch instructions.
2g is also used to control instruction fetch units 100 and 102. Control blocks 103 and 104 are connected to signal line 1
17, and this signal is used, for example, when synchronizing the two. The instruction execution unit has one register file 106 and two execution units 1.
Consists of 05 and 107. Register file 10
A portion of register file 106 and execution unit 105 are controlled by control signal 118 to
7 are each controlled by a control signal 119. There may or may not be commonalities between the portions of register file 106 controlled by control signals 118 and 119. Execution units 105 and 107 have independent source data buses 120 and 121, respectively, and target data buses 124 and 126, respectively, for storing operation results to file 106.

For memory access, the memory addresses calculated by the execution units 105 and 107 are sent to the memory access controller 1.
These controllers 108 and 11.0 issue access requests 129 and 130 to the data cache memory 109. The cache memory 109 accepts these signals alternately or simultaneously, and supplies data to the register file 106 via the load/store dedicated bus 25.

The left and right resources in FIG. 1 can operate independently except in special cases, and have a configuration suitable for extracting parallelism in programs and executing them simultaneously. In an extreme case, it is also possible to run completely different programs on the left and right sides. On the other hand, in FIG. 1, the instruction cache memory +J101 and register file 1 shared between the left and right
06 and the data cache memory 109 may differ somewhat depending on how the processor is implemented and the purpose of use. In other words, the inside of the cache memories 101 and 109 may consist of two cache memories)
However, it may be composed of one multi-vote cache memory. Another method is to configure the cache memory with one cache memory that can accept fetch requests alternately, and have a means for buffering the obtained instructions in the instruction fetching unit, making it appear as if the instructions were fetched every cycle. The inside of the register file 106 may be a register file completely shared between the left and right sides, or
It may also consist of two completely independent register files. Of course, it is also possible to partially share the information.

In the shared part, there is an independent bus 1 distributed to the left and right.
20.121.

Next, we will explain the operation of the system realized in this way in a second way.
This will be explained using figures. A 1 in the tarock signal is a high level signal in the first half of the machine cycle and a low level signal in the second half, and each part performs a predetermined process in this one cycle. The output signals 11, 4, and 115 of the instruction cache memory IJIOI each have a bit width for two instructions, and therefore, instructions need only be read once every two cycles. The output signal 114 is decoded by the control block 103 and becomes the primary stage signal 118. This signal controls data 120 in the next stage and data 124 in the next stage. By dividing one instruction into a series of processes in this way, a pipeline is configured to achieve parallel processing of instructions. The same applies to the signal lines 115.119.121.126 that operate the right half, but it is assumed here that they are not activated.

To operate on these signals, the right half of FIG. 1, the processor has special instructions or special fields embedded within the instruction code. Such an instruction will be referred to as a split instruction (F-ission B ran).
ch I n5 truction).

This splitting instruction is sent to execution unit 10 in time slot S1.
5, the control signal 20 in FIG.
1 is turned on, and the instruction fetch unit 102 becomes operational. The unit 102 accesses the instruction cache memory 101 according to an address set by the splitting instruction or an address that has already been set.

As a result, the pipeline in the right half of FIG. 1 also starts operating. The right and left halves of FIG. 1 operate independently.

On the other hand, it is also necessary to narrow down the pipelines that have started operating independently in this way to one again. Therefore, as in the case of splitting, this processor has special instructions or special fields embedded within the instruction code. Such an instruction is called a fusion instruction (Fusjon B ranc).
h I n5 truction). This fused instruction is sent to execution unit 105 in time slot S2.
If the control signal 202 in FIG.
is turned on, and the instruction fetch unit 1.00 stops operating. Along with this, the control block 103 and execution unit 105 are also stopped, and the left half pipeline is completely stopped. In other words, the pipeline is narrowed down to only the right half. A pipeline stopped by a fusion instruction is restarted only by a split instruction from an active pipeline or by a timer mechanism that is executed at regular intervals. Further, when parallel processing is stopped by this fusion instruction, it is also possible to use the processing system that was stopped using the conventional superscalar method.

Next, effective programming when using such a processor will be explained using FIGS. 3 and 4. Here, a superscalar machine that simultaneously processes two instructions at consecutive addresses will be used as a comparison target. Superpass machines are an effective method when the amount of hardware is limited, such as when using LSIs with low integration, but the constraint of two instructions with consecutive addresses makes it difficult to parallelize. The problem is that it doesn't improve. The rate of speedup achieved by this method is estimated to be about 1 to 20% at most.

Figure 3 shows 8 instructions with different numbers of execution cycles (○P301
~OP30g) is executed by both parties. For simplicity, it is assumed that there is no data conflict between instructions. OP2O3, OP2O3, OP2O3゜0P30
8 is an instruction that requires two cycles to execute, and the remaining instructions can be executed in one cycle. The left side of FIG. 3 shows an example of a superpower machine. Because a superpowered machine processes two instructions at consecutive addresses simultaneously, those instructions begin execution at the same time. Therefore, if the processing times of simultaneously executed instructions are different, there will be gaps here and there, and eight cycles of time slots T1 to T8 are required for the entire execution. On the other hand, in the multi-pass parallel processing method according to the present invention shown on the right side of FIG. 3, there is no such restriction, and the execution ends in six cycles of time slots T1 to T6.

The above is a comparison of a simple case with no branches, but the more important difference is that the parallelization rate is essentially different. That is, in a superscalar machine, two consecutive instructions cannot necessarily be executed simultaneously, so even if a code is generated using an optimizing compiler, the parts that cannot be parallelized will not essentially be eliminated. A good example is a branch instruction. Superpowered machines can only execute one branch at a time, and parallelism can only be extracted within a small amount of code between the branch entry and the next branch instruction. It is said that a branch instruction appears once in every five instructions, and the degree of parallelism is extracted between an average of four instructions. Figure 4 shows an example of code that includes a branch instruction (OP
401-0P408).

0I) 403 and 0P408 are conditional branch instructions, which branch to OP2O3 and OP2O3, respectively. 0P403
branches 7 times and does not branch once. Furthermore, 0P408 branches five times and does not branch once. Therefore 01) 401
Kara 0P403 is 8 times, 0P404 to 0P408 is 6 times.
Executed times. It is assumed that when a conditional branch instruction branches, four cycles are required for its execution, and when no branch is made or for other instructions, execution is completed in one cycle.

In the case of the conventional architecture with one pipeline (single mode) as shown in Figure 4(a), there are 54 instructions to execute and 12 branches, resulting in a total of 90 instructions.
It will take a cycle. In the case of the superscalar mode shown in FIG. 4(b), OP2O3 402, OP
404 and 0P 405 and 0P 406 and 407 can be executed in parallel, the number of instruction pairs to be executed is 34, and there are 12 branches as in the single mode, so the total number of cycles is 70. On the other hand, if the multiple pass parallel processing method according to the present invention shown in FIG. becomes. That is, 0P
401 to 403 are assigned to the pipeline on the left half of the processor, and the rest are assigned to the right half of the processor. The execution time of the pipeline in the left half of the processor is 45 cycles in total because the number of instructions is 24 and the number of branches is 7. Also,
The execution time of the pipeline in the right half of the processor is 45 cycles in total since the number of instructions is 30 and the number of branches is 5. Therefore, the total execution time is 45 cycles, which means that twice the degree of parallelism has been extracted compared to 90 cycles in single mode. Of course, there is an overhead associated with splitting and branching, but as the number of loops increases, this effect becomes negligible. This is why the present invention is inherently superior to superscalar mode.

Now, when using such a multi-pass parallel processing method, it is also necessary to consider the case where there is a data dependency between two passes, that is, two pipelines. This is because the possibility that such a situation will occur is extremely high, and without countermeasures against this situation, it will be impossible to derive the essential high performance of the multi-pass parallel processing method. FIG. 5 shows the flow of a program using the multiple-pass parallel processing method. The pipeline of this processor is divided into two by the splitting instruction 501, but each path operates in relation to each other. That is, in procedure 504, writing (Wl) is performed to the first register or memory, and it is referenced in procedure 509 of the other pass (R1). Procedure 5
09 further writes to the second register or memory (W2) and refers to it in procedure 512 (R2). At the same time, in procedure 508, a write is made to the third register or memory (W3), which is referenced in procedure 513 (R3).

Thereafter, the pipeline is unified by a fusion instruction. The execution order of the program flow shown in FIG. 5 is defined by data dependencies.

In other words, the procedure 504 is performed before the procedure 509.
8 must be executed before procedure 513, and procedure 509 must be executed before procedure 512.

Although this kind of execution order cannot be controlled by hardware, the compiler that generates the code for this program has information about the execution order, so it is possible to embed instructions for controlling the execution order in the code. . This instruction is accompanied by a conditional pause instruction (Iincrement and con
The operation will be explained below. As explained above, procedure 5
04 must be executed earlier than procedure 509. Therefore, synchronization is achieved using conditional pause instructions 506 and 507. Each of the two paths has a synchronization flag 502.
503, which are reset by the split instruction 501 and have their values increased by the conditional pause instruction. The conditional suspension instruction 507 has the function of making the execution of the procedure 509 wait until the execution of the procedure 504 is completed.

When the execution of the procedure 504 ends, the conditional pause instruction 506 has been executed, and the flag 502 is set to 1. The conditional suspension instruction 507 sets the flag 503 to 1 and sets the flag 502
Compare with. At this time, the conditional pause instruction 507 is flag 5.
The contents of 02 can be referenced using the signal line 515. If flag 502 is O, that is, flag 502 is flag 5.
03, the conditional pause instruction 507 stops the pipeline and waits for the conditional pause instruction 506 to finish executing. The same applies to conditional suspension instructions 510 and 511, but procedures 512 and 513 cannot start execution unless procedures 509 and 508 are completed, respectively, so the pipeline is stopped if the flag and value of the other party are not equal. Use a conditional pause instruction that has a judgment condition of

In this way, target programs can be executed in parallel without malfunction.

[Effects of the Invention] According to the present invention, by having a plurality of instruction fetch sections, the reduction in parallelism due to branch instructions can be solved, and the branch instructions themselves can also be parallelized. % can be extracted. Furthermore, by employing instructions and hardware for synchronizing a plurality of instruction execution units, the execution order of instructions can be controlled without malfunction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a processing device to which the method of the present invention is applied, FIG. 2 is an explanatory diagram of pipeline control in the processing device of FIG. 1, and FIGS. 3 and 4 are conventional methods. FIG. 5 is an explanatory diagram of an execution order control method when there is a data dependency relationship between instructions. 100, 102... instruction fetch unit, 103.
104...Control block, 105.107...Execution unit, 502°503...Flag.

Claims (1)

[Scope of Claims] 1. A processing system capable of independently operating, comprising an instruction retrieval means for retrieving an instruction from a memory, a decoding means for the instruction retrieved by the means, and an execution means for the instruction decoded by the means. In addition to providing a plurality of instructions, splitting instructions, and merging instructions, when there are instructions that can be processed simultaneously in the instruction sequence being processed by one processing system, by having that processing system execute the splitting instructions, the splitting instruction can be executed by another processing system. When starting simultaneous parallel processing and combining the simultaneous parallel processing of multiple processing systems into processing of one processing system, the above simultaneous parallel processing of the processing systems other than the one processing system is executed by having the one processing system execute the above fusion instruction. A multi-pass parallel processing method characterized by stopping the operation of a processing system that was performing processing. 2. When simultaneous parallel processing is performed by the plurality of processing systems, a flag is set for each of the plurality of processing systems, and a conditional pause instruction is inserted into the instruction string to be processed by the processing system. The flags of each processing system are cleared by the splitting instruction that instructs the start of parallel processing, and when each processing system executes the conditional suspension instruction, the flag of its own processing system is updated by +1, and the flag of the other processing system is checked. , If the values of the flags of the self-processing system and the other processing system are different, the processing of the next instruction of the self-processing system is suspended until the values match. . 3. When the fusion instruction is executed, a part of the consecutive instructions of the processing continued in the processing system that executed the fusion instruction, when the consecutive instructions do not include a branch instruction, is executed by the fusion instruction. 2. The multi-pass parallel processing method according to claim 1, wherein simultaneous parallel processing is performed by a processing system whose operation has been stopped.