JPH03212900A - Semiconductor memory and its testing method - Google Patents

Abstract

PURPOSE:To decide the address of a defective memory cell by storing normal/ defective data in a register at every decision of the normal/defective condition of a memory cell, and making access the register. CONSTITUTION:Plural bit lines 1,... are intersected orthogonally to plural word lines 2,..., and plural memory cells 3,... connecting the bit lines 1 and the word lines 2 are provided at each of those crossing points. The bit lines 1,... are connected selectively to one input side of comparators 6,... and inversion circuit selection switch S3 sides by the switching operations of comparator selection switches S1,... The comparators 6,... compare data read out of the memory cells 3,... with prescribed data, and write comparison results or the data in the memory cell on the registers 10,... In such a way, it is possible to specify the register on which write is performed by making access the registers sequentially, and to detect the address of a normal memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and a test method thereof.

[Conventional technology]

As the capacity of semiconductor memories continues to increase, an increase in testing time has become a problem, and various testing methods have been proposed as solutions to this problem. One such test method is the line test mode, which writes data to multiple memory cells for one column and compares the read data with the written data to check whether the data matches. It tests memory cells by detecting mismatches.

Figure 5 is a configuration diagram of a memory cell array for realizing the line test mode described in the 1989 Institute of Electronics, Information and Communication Engineers Autumn National Conference Proceedings C-155, and Figure 6 is the circuit for one row. It is a diagram.

First, the operation of the semiconductor memory device shown in FIG. 5 will be explained. This semiconductor memory device normally writes data into a memory cell 3 selected by a bit line 1 and a word line 2, and also reads data written into the memory cell 3.

When testing a semiconductor memory device, first close a plurality of launch circuit selection switches St, S2..., connect the I10 line 8 and a plurality of launch circuits 4, 4..., and connect the I10 line from the outside. For example, test data of "1" is applied to the latch circuits 4, 4, . . . Each launch circuit 4.4
... latches the given test data as an expected value.

Subsequently, a plurality of comparison circuit selection switches S1. sI...
to the upper side of the diagram, and multiple inverting circuit selection switches S: +
, Sz .
, 4... are launched. When writing test data "ON" to the memory cells 3, 3..., the inversion circuit selection switches S, , S,...
・Switch to the lower side of the diagram and write the inverted result using the inverting circuit 5.5...

In this way, when the writing of test data to the memory cells 3, 3, . . . connected to the respective word lines 2, 2, .
・Switch to the lower side of the figure, raise the word line 2,
The data of the memory cells 3.3... connected thereto is read out and applied to the comparison circuits 6, 6.... In addition, in order to give the same test data as the data written to the memory cells 3, 3, etc. from the latch circuit 4.4, the data of the memory cells 3, 3, etc. is set to "1"("O"), for example. In this case, the inversion circuit selection switch S3. S, ... at the top of the figure (
The same data written in the memory cells 3, 3, . . . is applied from the latch circuits 4, 4, . . . to the comparison circuits 6, 6, . Comparison circuit 6, 6...
Each compares both data simultaneously and detects a match or mismatch.

If the comparison results of all the comparison circuits 6, 6... match, the match wire 7 to which the output side of the comparison circuit is connected becomes "B". Also, any of the comparison circuits 6, 6... If the comparison results do not match, match vA7 becomes "0", and this is used as an error signal to determine that one of the memory cells 3 connected to the word line 2 is defective. A plurality of memory cells 3.3 and 3 connected to each word line 2 are connected to each word line 2 as a unit.
The quality of... is determined all at once.

Next, the operation will be explained with reference to FIG. 6, which shows in detail one row of the semiconductor memory device shown in FIG. 5. Here, the memory section will be explained as dynamic access memory for convenience, but
The same applies to static memory or EFROM.

Now, the test data is sent to the latch circuit 4 connected to the power supply line VCC and the ground line GND, for example, by connecting the node N5 to "
0”, node N6 is latched as “1”,
It is assumed that "1" is written into the memory cell 3a using this test data.

When comparing the data of the memory cell 3a and the test data of the launch circuit 4, first, when one word line 2 (on the left in the figure) is turned on, the switching transistor B connected to that word line 2 is turned on. Then, the data in the memory cell 3a is read out, a sense amplifier (not shown) amplifies it, and outputs complementary data to the bit line 1 and the inverted bit line T.

If “1” is written in the memory cell 3a as described above, the node N2 of the inverted bit IT becomes the “1” node N.
1 becomes “θ”.

Next, raise the signal TI and switch the switching transistor ST.
By turning on , , ST (corresponding to the state in which the inversion circuit selection switch S3 in FIG. 5 is switched to the upper side),
The test data of the latch circuit 4 is output as it is to the bit line 1 and the inverted bit line T, and since the node N5 is "0'", the node N3 is "ON", and because the node N6 is "1", the node N4 is "1". become.

The match line 7 is precharged immediately before the comparison circuit 6 performs the comparison operation, and if the data read from the memory cell 3a matches the test data from the latch circuit 4, the match line 7 is set to "1" (precharged). state), and if there is a mismatch, it becomes “θ”.

That is, as described above, switching transistor ST9.
By turning on ST, node N3 becomes “0”
, the node N4 becomes "1", and as described above, the node N2 becomes "1" due to the data read from the memory cell 3a.
When the node N1 becomes "0", when the signal COMP is set to "1" in order to compare both data, the switching transistors ST, ST, ST are turned on. At this time, since the node N4 is "1", the switching transistor ST& (upper part of the figure) whose gate receives the voltage of the node N4 is turned on. Since the node N1 is "0", the node N7 becomes "O" and the transistor C is turned off, the match line 7 holds "1", the comparison result of the comparator circuit 6 shows a match, and the memory cell 3a is turned off. It will be judged as good.

On the other hand, when the data read from the memory cell 3a causes the node N2 to become "0" and the node N1 to "1",
When the signal COMP is set to "1" and the switching transistors s"r, , ST3 are turned on, the node N3 is "O" and the node N4 is "1" as described above.
Since the switching transistor 5T6 (upper part of the figure) applying the voltage of the node N4 to its gate is on, the node N7 becomes "1", the transistor C is turned on, and the match line 7 becomes '0'. As a result, the comparison result of the comparator circuit 6 shows a mismatch, and the memory cell 3a is determined to be defective.

Furthermore, when data "0" is written in the memory cell 3a, the signal T2 is set to "1" to turn on the switching transistors ST, ST, (the inverting circuit selection switch S3 is turned on as shown in FIG. 5). (equivalent to the state switched to the lower side),
Test data obtained by inverting the test data of the latch circuit 4 is applied to the focus line 1 and the inverted bit line T. As a result, the node N3 becomes "1" and the node N4 becomes "0". Then, as described above, the signal COMP is set to "1" to turn on the switching transistors ST:l and ST3, and the comparison circuit 6 compares the data read from the memory cell 3a with the test data of the launch circuit 4. In this case, since the node N3 is "1", the switching transistor ST.

(bottom of the figure) turns on. If the node N2 is "0", the node N7 becomes "O", the match line 7 holds "1", and the memory cell 3a is determined to be good.

On the other hand, if the node N2 is "1" according to the data read from the memory cell 3a, the switching transistor 5T
node N7 via sC (bottom of the diagram) and ST, (bottom of the diagram)
becomes "1", the match line 7 becomes "0", and the memory cell 3a is determined to be defective.

In this way, even when "0" is written to the memory cell 3a, it is possible to determine whether the memory cell 3a is good or bad in the same way as when "1" is written.

Each time such a comparison operation is completed, the reset signal RS
By setting the reset signal R3 to "L", the transistor D to which the reset signal R3 is applied is turned on, the node N7 is set to "0", and the transistor C, which was turned on in the case of mismatch, is turned off.

In this way, for each word line 2, the operation of comparing the test data with the data read from the plurality of memory cells 3, 3, etc. connected to the word line 2 is repeated to determine the quality of all memory cells. be done.

Therefore, one column of memory cells can be tested in one comparison operation, and the test time is significantly shortened.

[Problem to be solved by the invention]

By the way, in the semiconductor memory device described above, one column of memory cells can be tested at the same time, but the row address of a defective memory cell cannot be determined. Therefore, there is a problem in that it is not possible to perform a test that requires the row address of a defective memory cell, for example, a test that determines whether redundancy can be used.

SUMMARY OF THE INVENTION In view of this problem, it is an object of the present invention to provide a semiconductor memory device and a test method thereof that can detect the address of a defective memory cell.

[Means to solve the problem]

A semiconductor memory device according to a first aspect of the present invention has a configuration in which a register is provided for each of one or more comparison circuits to which the comparison result of the above-mentioned comparison circuit or data of a memory cell is to be given, and the registers can be sequentially accessed.

In the test method for a semiconductor memory device according to the second invention, if the comparison results of the comparison circuits do not match, the memory cell from which the data was read for data comparison is determined to be defective, and the comparison results of the comparison circuits or the memory cells are determined to be defective. After applying the read data to the corresponding register, the registers are sequentially accessed to identify a defective memory cell among a plurality of activated cells in the same column.

[Effect]

1st. In the second aspect of the invention, the comparison circuit compares the data read from the memory cell with predetermined data. If the comparison result is a mismatch, the comparison result of the comparison circuit or the data of the memory cell is written into the register.

Therefore, by sequentially accessing the registers, it is possible to specify the register to which the above-mentioned writing has occurred, and the address of the defective memory cell can be determined.

[Examples] The present invention will be described in detail below with reference to the drawings showing examples thereof.

FIG. 1 is a configuration diagram of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing one row thereof in detail.

In FIG. 1, a plurality of bit lines 1, 1.1, . A plurality of memory cells 3, 3.3, . . . are provided. Each bit line 1, 1... is connected to a comparison circuit selection switch S+, S
By the switching operation of I..., the - of the comparison circuits 6, 6...
It is selectively connected to the input terminal and the inverting circuit selection switch S3 side. The outputs of the comparison circuits 6.6, . . . are applied to the match line 7. I10 line 8 is the launch circuit selection switch Sz
, Sz, . . . are connected to the launch circuits 4, 4, . Launch circuits 4.4... are inverted circuit selection switches S3. By the switching operation of S3..., the inverting circuits 5, 5.
. . or not through the inverting circuits 5, 5, . Further, the outputs of the four comparison circuits 6, 6, . . . are inputted as one unit to the OR circuit ILIL11. OR circuit 11,1
Each output of 1.11 is given separately to a register 10.10.10, and the registers 10.1010 are connected in cascade to form a parallel manual/serial output shift register.

In FIG. 2, the bit line 1 and the inverted bit vAT each include a switching transistor ST to which a signal TR is applied, and a selection signal Y from a decoder (not shown).
, a switching transistor STt is interposed. Word line 2 is connected to the gate of transistor B. The inverted bit line T is grounded through a series circuit of a transistor B and a memory cell 3a.

Further, each of the bit line 1 and the inverted bit line T is provided in the comparator circuit 6, and the signal CO? It is connected to the gate of the transistor C and the transistor D through a switching transistor ST3 to which IP is applied and a switching transistor ST6 connected in series with it. These switching transistors ST, , ST
3 corresponds to the comparison circuit selection switch S.

The output of the transistor C, which is the output of the comparator circuit 6, is applied to a match wire 7 via a fuse F that is blown when redundant use is performed, and the match wire 7 is connected to one inverting input terminal of the NAND circuit 15. Transistor C of comparison circuit 6
The reset signal R5 for turning off the transistor D
is given to. Bi between switching transistors ST and STt.

an inverting circuit 5 connected to the bit line 1 and the inverted bit line T;
A signal T2 is applied to the switching transistor ST, and a signal T1 is applied to the switching transistor ST. These switching transistors ST4
．． STS corresponds to the inversion circuit selection switch S3. The launch circuit 4 has a power line VCC and a ground line GN.
D is connected. The bit line 1 and the inverted bit line T are connected to the I10 line 8 and the inverted I10 line. The signal at the node N7, which becomes "1" when the comparison circuit 6 detects a mismatch, can be used to determine the quality of the memory in units that can be replaced depending on the number of redundant circuits, for example, four rows of memory as one block. As shown in FIG.
is given to node N8. Further, the other inverting input terminal of the NANO circuit 5 is given a transfer inhibit signal TILT from a circuit (not shown) that is generated when sequentially accessing the register 10, that is, serially accessing the register 10 to check the row address of the defective memory. circuit 15
Transfer signal TW, which is the output of transfer signal TW, is applied to the gate terminal of transfer gate 13. The register 1o is a transistor ST7 to which a clock signal S0 is applied, an inverter section n, and a transistor S to which an inverted clock signal S+(-3o) is applied.
It is constituted by a series circuit of T and an inverter section v2.

Next, the operation of the semiconductor memory device configured as described above will be explained first with reference to FIG. This semiconductor memory device usually has a memory cell 3 selected by a bit line 1 and a word line 2.
Data is written to the memory cell 3, and the written data is read from the memory cell 3.

When testing a semiconductor memory device, first select a plurality of latch circuit selection switches S2. SZ... is closed to connect the I10 line 8 and the plurality of latch circuits 4, 4..., and the test data of, for example, "B" is transmitted from the outside via the I10 line 8 to the launch circuits 4, 4...・Give to each launch circuit 4, 4・
... launches the given test data as the expected value.

Subsequently, a plurality of comparison circuit selection switches S,,s.

...to the upper side of the diagram, and select multiple inverting circuits.

Switch S:+, Si... to the upper side of the diagram, and
When one word line 2 is turned on, the test data “bit” latched by the latch circuits 4, 4, etc. are transferred to the plurality of memory cells 3, 3, . When writing test data of "0" to the memory cells 3, 3, . . . , the inversion circuit selection switch 33.
Switch Sl... to the lower side of the diagram, and invert circuit 5.5...
・Write the inverted version.

In this way, when the writing of test data to the memory cells 3, 3, . . . connected to the respective word lines 2, 2, .

SL... is switched to the lower side of the figure, the word line 2 is raised, and the memory cells 3゜3... connected to it are switched to the lower side of the diagram.
The data is read out and applied to the comparison circuits 6, 6, . . . In addition, in order to give the same test data as the data written to the memory cells 3, 3, etc. from the latch circuits 4, 4, the data of the memory cells 3, 3, etc. is changed to, for example, “1” (“0”).
), the inversion circuit selection switch S3. By switching Sl... to the upper side (lower side) of the diagram, the memory cells 3, 3.
The same data as the data written to... is sent to the launch circuit 4,4.
... to the comparison circuit 6.6... Comparison circuit 6,
6... Each compares both data at the same time and detects a match or mismatch.

If the comparison results of all the comparison circuits 6, 6, . . . match, the match line 7 to which the output sides of the comparison circuits are connected becomes "1". Also, if the comparison results of any of the comparison circuits 6, 6, etc. do not match, the match line 7 will be set to “0”.
'', and this is used as an error signal to determine that one of the memory cells 3 connected to the current word line 2 is defective.In this way, each word line is The quality of a plurality of memory cells 3, 3, .

Next, the operation will be explained with reference to FIG. 2, which shows in detail one row of the semiconductor memory device shown in FIG. 1. Here, the memory section will be explained as dynamic access memory for convenience, but
The same applies to static memory or EPROM.

Now, the test data is sent to the launch circuit 4 connected to the power supply line VCC and the ground line GND, for example, by connecting the node N5 to "
0'', node N6 is latched as ``l'', and it is assumed that ``1'' is written in the memory cell 3a using this test data.

When comparing the data in the memory cell 3a and the test data in the latch circuit 4, first, when one word line 2 (on the left in the figure) is turned on, the switching transistor B connected to that word line 2 is turned on. Then, the data in the memory cell 3a is read out, a sense amplifier (not shown) amplifies it, and outputs complementary data to the bit line 1 and the inverted bit line T.

If "1" is written in the memory cell 3a as described above, the node N2 of the inverted bit line T becomes the "1" node N.
1 becomes “0”.

Next, raise the signal TI and switch the switching transistor ST.
5. By turning on STS (corresponding to the state in which the inversion circuit selection switch S3 in Fig. 5 is switched to the upper side),
The test data of the latch circuit 4 is output as it is to the bit line 1 and the inverted bit &iT, and since the node N5 is "0", the node N3 is "0", and because the node N6 is "1", the node N4 is "1". become.

The match line 7 is precharged immediately before the comparison circuit 6 performs the comparison operation, and if the data read from the memory cell 3a matches the test data from the launch circuit 4, the match line 7 is set to "1' (precharged). The status is held and becomes "0" if there is a mismatch.

That is, as mentioned above, the switching transistor STS
, by turning on STs, node N3 becomes “0”.
”, the node N4 becomes “1”, and as mentioned above, the node N2 becomes “1” due to the data read from the memory cell 3a.
, when the node N1 becomes "0", the switching transistors STs and ST3 are turned on when the signal COMP is set to "1" in order to compare both data. At this time, since the node N4 is "1", the switching transistor 5T6 (upper part of the figure) whose gate is supplied with the voltage of the node N4 is turned on. Since the node N1 is "0", the node N7 becomes "0" and the transistor C is turned off, the match line 7 holds "1", the comparison result of the comparator circuit 6 shows a match, and the memory cell 3a will be judged as good.

On the other hand, when the node N2 becomes "O" and the node N1 becomes "1" due to the data read from the memory cell 3a,
When the signal COMP is set to "1" to turn on the switching transistors ST, , ST, the node N3 is "0" and the node N4 is "1" as described above, so the voltage of the node N4 is applied to the gate. Since the switching transistor ST (upper part of the figure) is on, the node N7 becomes "L", transistor C is turned on, and the match line 7 becomes "0".As a result, the comparison result of the comparator circuit 6 indicates a mismatch, and the memory cell 3a is determined to be defective.

Further, when data "0" is written in the memory cell 3a, the signal T2 is set to "1" and the switching transistors ST4. ST4 is turned on (corresponding to the state in which the inversion circuit selection switch S3 is switched to the lower side in FIG. 5), and test data obtained by inverting the test data of the launch circuit 4 is applied to the bit line 1 and the inversion bit line T. As a result, the node N3 becomes "binode N4" becomes "0".Then, similarly to the above, the signal COMP is set to "1", switching transistors ST3 and STI are turned on, and the comparison circuit 6 is turned on.
The data read from the memory cell 3a and the launch circuit 4
In this case, node N
Since 3 is 1″, the switching transistor ST&(
below) is turned on. If the node N2 is "O", the node N7 becomes "0", the match line 7 holds "1", and the memory cell 3a is determined to be good.

On the other hand, if the node N2 is "1" according to the data read from the memory cell 3a, the switching transistor ST
:+ (bottom of the diagram) and ST, (bottom of the diagram) to the node N
7 becomes "1", match line 7 becomes "0", and the memory cell 3a is determined to be defective.

In this way, even when "0" is written to the memory cell 3a, the quality of the memory cell 3a can be determined in the same way as when "1" is written.

Each time such a comparison operation is completed, the reset signal RS
By setting "1" to "1", the reset signal l? Turn on the transistor D to which s is applied and set the node N7 to “0”
and turns off the transistor C that was turned on in the case of mismatch.

In this way, for each word line 2, the operation of comparing the test data with the data read from the plurality of memory cells 3, 3, etc. connected to the word line 2 is repeated to determine the quality of all memory cells. be done.

By the way, when the match line 7 becomes "O" and the transfer inhibit signal TRI is "0", the transfer signal TW output from the NAND circuit 15 becomes "1" and the transfer gate 13 is turned on. Therefore, "1" at the node N7 of the comparator circuit 6 is applied to the register 10 via the OR circuit 11, and the register 10
"1" is launched at node N8.

Next, the clock S is applied to the transistor ST of the register 10.
.

When SI is applied, transistor ST7 is turned on, and then transistor ST8 of that register 10 is turned on, and the contents of node N8 are applied to the next register 10 (upper part of the diagram), corresponding to the defective memory cell. Data is clock S. and S, the register 10 is shifted to the next register 10, and the register 10 is sequentially accessed, that is, serially accessed. This causes “1” on the output side of the register.
The row address of the defective memory cell can be determined in block units as described above based on the count value in units of 2 clocks when data is obtained, and the determination time is reduced to 2 times compared to determining each memory cell individually. . Thereby, four memory cells including a defective memory cell can be replaced with redundant memory cells in block units.

Note that during the period when the registers 10 are sequentially accessed in this way, the data in the memory cells of the next column and the launch circuit 4 are accessed sequentially.
A line test can be performed in parallel to determine the quality of the memory cell by comparing it with the test data of the memory cell. In that case, the transfer inhibit signal TRI is set to “1” when the register 10 is sequentially accessed.
'', the transfer gate 13 is turned off, and at that time, even if the data of the defective memory cell is obtained, it is not transferred to the register 10, and the register does not launch the data of the defective memory cell.

FIG. 3 is a configuration diagram of a semiconductor memory device showing another embodiment of the present invention, in which data read from a memory cell is transferred to a register, such as a 2-port RAM for image processing equipped with a serial access memory. This is an example in which the present invention is applied to a semiconductor memory device that can sequentially access the registers and output them to the serial I10 line. In this semiconductor memory device, the data read from the memory cell 3 is transferred to the transfer gate 13.
The signal is applied to the register 10 of the serial access memory 12 via the serial access memory 12. The signal on the match line 7 is applied to one inverting input terminal of the NAND circuit 15, and the transfer inhibit signal TRI is applied to the other inverting input terminal.

The output of the NAND circuit 15 is input to the 017 circuit 16 to which the transfer permission signal TRE is input. The transfer signal TW output from the OR circuit 16 is applied to the gate of the transfer gate 13. The other structure is the same as that of the semiconductor memory device shown in FIG.

FIG. 4 is a circuit diagram showing in detail three rows of the semiconductor memory device of FIG. The signals on each bit line l and each inverted bit line T are separately applied to registers 10, 10, 10 of serial access memory 12 via transfer gate 13, and transistors ST9, . ST,
are applied to the serial I10 line 14 and the inverted serial I10 line port via the serial I10 line 14 and the inverted serial I10 line port, respectively. Serial access memory 12
of each pair of transistors ST.

For example, an output signal from a serial selector 17, which is a shift register, is applied to the gate of ST. The match line 7 is connected to one inverting input terminal of the NAND circuit 15, and the transfer inhibit signal TRI is input to the other inverting input terminal. The output of the NAND circuit 15 is the transfer permission signal TR.
It is input to the OR circuit 16 to which E is input.

The transfer signal TW output from the OR circuit 16 is transferred to the transfer gate 13
is applied to the gate terminal of The other constituent parts in each row are the same as those shown in FIG. 2.

In this semiconductor memory device, normally, the transfer signal 1 is controlled by the transfer permission signal TRE, and data is transferred between the memory cell 3 and the register 10.

Further, determination of the quality of the memory cell is performed in the same manner as in the semiconductor memory device shown in FIG.

By the way, in the line test, if the comparison circuit 6 compares the data read from the memory cell 3a with the test data of the latch circuit 5, and the result is a mismatch, the match line 7 becomes "O".
". At that time, if the transfer inhibit signal TRI is "0", the transfer signal REN becomes "I", and the data of the memory cell 3a is transferred to the register 10, and the register 10 stores it. Latch bad data.

After that, when determining the address of the defective memory, the serial selector 17 selects each pair of transistors ST9,
Turn on ST9 sequentially and register 10.10゜1
Access 0 sequentially. Then, the contents of register 10 are output to serial I10 line 5 inverted serial I10 line 14°, and serial I10 line 3 inverted serial I10
Line 14. The number of accesses to the serial selector 17 when comparing the contents of the register 10 sequentially obtained from (1) with the test data of a tester (not shown) connected to the serial I10 line 14 and the inverted I10 line port and determining that they do not match indicates the failure. Determine the address of the memory cell.

Note that after the data is transferred to the register 10, the line test of the memory cells in the next column can be continued.

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device of the first invention, the quality of the memory cell is determined and each time the determination is made,
Since the pass/fail data is stored in the register, the address of the defective memory cell can be determined by accessing the register, and a semiconductor memory device suitable for redundant use can be provided. Further, according to the test method of the second invention, since the determination of the quality of the memory cell and the storage operation of the quality data of the memory access are performed in parallel, the time required to determine the quality of the memory cell and the address of the defective memory can be shortened. It has a great effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing one line of the device in detail, and FIG. 3 is a block diagram of a semiconductor memory device showing another embodiment of the present invention. , FIG. 4 is a circuit diagram showing three lines in detail, FIG. 5 is a configuration diagram of a conventional semiconductor memory device, and FIG. 6 is a circuit diagram showing one line in detail. 1...Bit line T...Inverted bit line 2...Word vA 3...Memory cell 4...Latch circuit
5... Judgment circuit 6... Comparison circuit 7... Match wire 8... T10 line)... Inverted T10 line 10...
・Register 13...Transfer gate 14...Serial T10 line Mouth...Inverted serial T10 line 15...N
AND circuit S,... Comparison circuit selection switch S2...
- Launch circuit selection switch S3... Inversion circuit selection switch Note that in the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a semiconductor memory device having memory cells arranged in a matrix and a comparison circuit that compares data read from the memory cells and predetermined data, the comparison result of the comparison circuit or the data of the memory cells should be provided. 1. A semiconductor memory device comprising a plurality of registers corresponding to one or more comparison circuits, the registers being configured to be sequentially accessible. (2) In the method for testing a semiconductor memory device according to claim 1, if the comparison results of the comparison circuit do not match, the memory cell from which the data was read to be compared is determined to be defective, and the comparison circuit 1. A method for testing a semiconductor memory device, comprising applying a comparison result or data read from the memory cell to the register, and then sequentially accessing the register to identify the memory cell.