JPH03211913A - Delay circuit - Google Patents

Abstract

PURPOSE:To independently vary the rise and the fall, to adjust the timing with high accuracy, to facilitate the timing adjustment of an apparatus, and to shorten the adjustment time by inserting an integration circuit between a first comparator and a second comparator, and varying the delay time. CONSTITUTION:Between an output of a first comparator 1 having an open emitter or open collector output, and an affirmative or negative input of a second comparator 2, a CR integration circuit constituted of capacitors C1-Cn and a resistor 4 is arranged. Also, the circuit is constituted so that its capacitors C1-Cn are connected in series to switches Sw1-Swn, and also, many pieces thereof are connected in parallel, a prescribed DC comparison voltage is applied to the other input terminal of a second comparator 2, the capacitance is varied by turning-on/off of the switches Sw1-Swn and the delay time is varied. In such a way, the circuit in which each independent selectivity of a delay to a rise and a fall of a pulse signal waveform is satisfactory, a control voltage is low, and which can be converted to a monolithic IC with the maximum variable delay time set arbitrarily can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit that can selectively change the amount of delay for one of the leading and trailing edges of a pulse waveform.

[Conventional technology]

As logic 1 path becomes faster and more accurate, timing accuracy improves]
L flea afl is becoming. By the way, the individual components used in the circuit, the wiring length, the wiring length, the wiring capacity, etc., vary, and the timing of the signal does not reach the desired value. Therefore, a delay circuit is inserted in the signal path, and the delay is Is it necessary to change the amount and adjust it to the desired timing? Furthermore, since the rise and fall characteristics of the active elements used in one circuit are different, it is necessary to adjust the timing of the leading edge and trailing edge of the pulse waveform individually.

Here, the 6th section is a circuit configuration diagram of a conventional delay circuit, and the 7th section is a circuit diagram of a conventional delay circuit.
The figure is a diagram of each waveform in the circuit, and FIG. 8 is a diagram of its delay characteristics. This circuit has 4+1 Kaisho 59-3!5
As described in Publication No. 926, a buffer circuit using a differential amplifier or having a voltage ratio function such as a comparator or a line receiver (hereinafter referred to as a first comparator)
10 input terminal IN.

A pulse is input to IN, and the output electrons are passed through a resistor 5.4 as an integrating circuit, a variable capacitance diode 5°, and
It is connected to a resistor 6.7 and a variable capacitance diode 6.

A variable reverse bias voltage Vj is applied to these variable capacitance diodes 5.8, and by changing this voltage Vj, the capacitance of the variable capacitance diodes 5 and 8 changes, resulting in one circuit. Since the time constant of changes, the waveform of the negative input 9 of the second comparator 2 rises as shown in (, <) in FIG.

! The downlink time changes as shown by the broken line.

In FIG. 7, the waveform when the capacitance of the variable capacitance diodes 5 and 8 is made small is shown in real form, and the waveform when the capacitance is made large is shown in broken lines.

Further, in this circuit, the waveform of the positive side human power 10 of the second comparator 2 is as follows.

That is, since the diode 11 is connected in parallel to the resistor 5, when the output of the first comparator 1 changes from the Lo level to the H level, the diode 11 becomes conductive, and the variable capacitance diode 5 is switched on for a short time. Charge it with

On the other hand, when the output power of the first nonimparator 1 changes from the L/H level to the L# level, the reverse bias voltage r1 is applied to the diode 11, and the electric charge charged in the variable capacitance diode 5 is It is gradually discharged by the resistor 3.4, resulting in a waveform as shown in FIG. 7 (-).

In this way, the second comparator 2 has (i
A waveform such as +, (ml) is input, and a waveform as shown in FIG. 7 is output from the second comparator 2.

If the capacitance of the variable capacitance diode is changed in this way, the amount of delay in this circuit will change.

This has a great effect on the fall of the input waveform.

That is, the amount of delay can be controlled by separating the rising and falling edges.

FIG. 8 shows the characteristics of this circuit.

That is, FIG. 8 shows the first and second;
When using an emitter-coupled logic (ECL) line receiver HD 100114 (manufactured by 8 beans), a CI SV 124 (Hitachi &) as the variable capacitance diode 5.8, and a 155165 (manufactured by Hitachi) as the diode 11.

Bias voltage r1 applied to transformer cap diode 5.8
, and the transmission delay time tpd in this circuit.

As shown in the diagram, when the bias voltage V1 is changed from 2 to 14F', the amount of change in the transmission delay time at the falling edge (hereinafter referred to as
It is called tpd-f. ) is 7.18%, as shown in Figure A.
Changes from kick to 420 awe.

The amount of change in propagation delay time at the rise at this time (hereinafter, t
pd de) has changed from 512 island kicks to 128 s kicks, as shown in Figure B.

This characteristic curve is used when trying to actively change the falling edge, and when using this delay circuit, for example, in order to match the timing of input and output for memory IC testing. It is desirable that the rise does not change.

Here, tpd-r at the rising edge and tpt at the falling edge.
・Difficulty level is 1 minute by taking the ratio of the amount of delay time to f =
If & is defined as tpd-j/tpt-r, & of this degree of separation η is large, and the characteristics of the circuit are familiar to us.

By the way, in the delay circuit shown in FIG. 6, as can be found from the characteristic curve shown in FIG.

It is 4.74.

And with this rice, if you try to change the rise,
Incidentally, the rising edge also changes, and this value of the degree of separation η is insufficient when performing timing adjustment with high precision and high speed.

In other words, this delay circuit can be said to have poor isolation, which is still insufficient, and since it uses a variable capacitance diode, a high voltage of 2 to 20 V is required as a control voltage range, and the variable capacitance What is the capacity of the diode? 300 from F order? The maximum variable delay amount is determined by the value of the variable capacitance diode and resistor used, and is fixed at a certain value. It had been. Furthermore, as a used element.

Because a variable capacitance diode and a comparator are mixed, it is a one-chip monolithic IC in the semiconductor IC process.
The disadvantage was that it was difficult to convert.

[Problem to be solved by the invention]

The purpose of the present invention is to overcome the insufficiency of the previously developed one, and to solve the insufficiency of the pulse signal 4! Good selectivity of independent delays for the rising and falling waves of the waveform.

Braking voltage is small and maximum variable! ! The purpose of the present invention is to provide a circuit in which the waiting time can be arbitrarily set and which can be made into a monolithic IC.

Means for solving the cII problem] In order to achieve the above purpose, between the output of the first comparator having an open emitter or open collector output and the affirmative or negative input of the second comparator,
A CR integration circuit is arranged with a capacitor and a resistor, the capacitor is connected in series with a switch, and a large number of them are connected in parallel, and a constant DC comparison voltage is applied to the other input terminal of the second comparator. 0N- of the switch by applying
01#, the screen is constructed so that the capacity changes and the delay time changes.

Additionally, the braking voltage was reduced by connecting and disconnecting the capacitor with a switch to vary the capacitance.

Furthermore, since the elements used are comparators, switch circuits, and capacitors, they can be manufactured using normal bipolar IC processes and can be made into a monolithic IC.

[Function] The delay circuit of the present invention is one in which a CB integration circuit is provided between the first comparator output and the second comparator negative force, and the first comparator output waveform rises. Since the output circuit of the first comparator is an open emitter, the negative input waveform of the second comparator at the time is not in a conductive state and rises at the same speed as the output rise of the first comparator. , since the first comparator output waveform or the second comparator's undefined input waveform when falling, the output circuit of the first comparator is OFI'.

It becomes non-conductive and connects to the capacitor of the CR integration circuit.

The fall time is determined by the time constant of the resistor.

At this time, the capacitor of the CR equinox circuit can change the capacitance connected to the resistor by a switch, so only the fall time of the waveform input to the negative side of the second comparator changes, and the second The DC ratio soft voltage input to the other side of the comparator causes the second comparator to be positive I
The Il output was compared and waveform shaped. A waveform in which only the rising edge is variably delayed is obtained.

Regarding this matter, by setting the input of the second comparator to a positive state, a waveform in which only the falling edge is variably delayed can be obtained from the positive output of the second comparator.

〔Example〕

Each embodiment according to the present invention will be described with reference to one drawing.

First, FIG. 1 is a delay circuit diagram according to an embodiment of the present invention.
FIG. 2 is a diagram of each waveform in the circuit, and FIG. 3 is a diagram of its delay characteristics.

In the figure, 1.2 is the first and second comparator 8 is the output part, 4 is the first resistor, 3 is the second resistor, 5 is the third resistor%10 is the negative side of the second comparator 2 input, 5,
6.7 is a resistor, and 9 is a positive input of the second comparator 2.

In the present embodiment, motucon baleta, which is related to open emitter output, is used as the first and second condenser rake.

That is, the first related to open emitter output: +7
A switch Sw+ ~ S
w B and Contin'') C+ -Cn are connected in series and are further connected in parallel, one of which is connected to the negative electrode yxx via the first resistor, and with this capacitor and resistor, CR The integration circuit is connected to the output 8 of the first comparator 1 through a second resistor, and the output 8 of the first comparator 1 and the second comparator input 1
o is connected through a third resistor 5, and a constant DC comparison voltage is applied to the positive side human power 9, which is the other input terminal of the second comparator 2. The voltage of the power supply VEX is divided by a resistor 6.7 to give an if&potential.

In this way, the configuration is configured such that Swl''-5ag is turned ON and OFF to change the capacitance connected to the first resistor 4 and change the delay time.

IN, IN are the positive S and negative inputs of the first comparator 1, OUT, 01・T are the second comparator 2
It is negation @output.

In the above delay circuit, each input IN of the first comparator 1
, IN in a differential manner, and the output thereof is also output from the output section 8.

First, the input of the first comparator 1 is from L#m level to H
When the im level changes, since the output of the first comparator 1 is an open emitter, the output transistor of the first comparator 1 becomes conductive.

Therefore, the output impedance is very small, and the input of the second comparator 2 becomes 5 (6; in FIG. 2).
The rise time is the same as the rise of the output of the first comparator 1.

In more detail, the input of the second comparator 2 is
From the voltage point where resistor 3 and resistor 4 are divided, τ” Cx
It rises with the time constant of XRsoHa, and before that it is determined by the output transistor of the first comparator 1. If the resistor 3 is too small, an infinite current will flow through the output of the first comparator 1, resulting in a large inrush current. If the resistor 5 is too large, the input rise time of the second comparator 2 will be delayed.

Next, when the input of the first comparator 1 transitions from the E@ level to the Le level, the output transistor of the first comparator 1 is close to a non-conducting state, that is, the output impedance becomes large, so the second The input of the comparator 2 is the ON/C
Is it becoming Contin? The voltage falls as shown in FIG. 2-) depending on the time constant of the sum of the capacitances of C+ to C1.

Further, by turning ON and OFF the switches S and Sw%, the capacitance changes and the time constant changes.

FIG. 2 shows the input/output waveforms at the points indicated by X marks in FIG. 1, and two capacitors C1 to C4 are connected by switches 5I111 to 5wn□. The solid line shows the waveform when the capacitance is small, and the broken line shows the waveform when five capacitors C1-C% are connected.

As mentioned above, the iEi voltage of 5 as shown in Figure 2 th+ is applied as a comparison voltage to the other input 9 of the second comparator 2, and from the output OUT, the compared and waveform-shaped voltage shown in Figure 2 ( A waveform like cl is output.

! The current ratio voltage is given by dividing the VEX voltage by 1# resistors 6 and 7, but it may be given by other methods.

However, as can be seen from FIG. 2, the level is L because it is compared with the input waveform of the second comparator 2.

The closer the DC comparison voltage is to the level, the better the separation will be, but on the other hand, it will become CS due to noise.

Normally, this DC comparison voltage is noisier than the Lm level.

In addition, in consideration of voltage fluctuations, it is better to set the potential to be approximately 100 m1F or higher and lower than the middle of the Him level L#m level.

The third resistor 5 is not necessary for basic operation, but is a resistor for preventing overshoot of the input 10 of the second comparator 2. In addition, the first resistor 4 is a capacitor C, ~C%
Establish a CR & branch circuit, and.

The emitter follower output stage of the first comparator 1 also serves as a pull-down resistor of the Kell transistor.

A and E in FIG. 3 show the characteristics of the delay circuit.

In this circuit, an emitter-coupled logic (ECL) line receiver El) 100114 (manufactured by Hitachi) and 5 sets of capacitors (1PF) are used as comparators, and the propagation delay time tpd when changing the capacitor capacity by setting Sw to ONI. It expresses the relationship between

The amount of change in rise and fall when one to five capacitors are connected is tpd-r=α0taI, tpd-f
=562 R#, and the degree of separation η is 90.5.

As mentioned above, the degree of separation of the conventional delay circuit is η=474 from FIG. 8, and the performance of this circuit is about 19 times higher than that of the conventional one.

Here, in the above-described embodiment, CRg is connected between the output of the first comparator 1 and the negative input of the second comparator 2.
A shunt circuit is provided between the output of the first comparator 1 and the positive input of the second comparator 2.
Even if a & branch circuit is provided, the same effect can be obtained.

FIG. 4 is a delay circuit diagram of another embodiment of the present invention.

In the figure, the numbers shown in Figure 1 indicate the same parts.

Tde, ~Trn are switch circuits, and TC1~rc
n is a capacitor formed of a transistor.

These operations and characteristics are similar to the circuit shown in Figure 91 of Sagi.

Furthermore, FIG. 5 is a diagram showing the construction of Sonoji for independently delaying the rise and fall. This can be realized by inverting one phase by connecting the delay circuits shown in FIG. 1 in series. Again, the N- symbols in Figure 91 indicate equivalent parts, and I-V.

These correspond to the first and second comparators 1 and 2, and the comparators I and l, the same ■ and l, the same m and ■, and the same and ■ correspond to the first comparator and the second comparator, respectively. It is paired with a comparator.

Note that the delay circuit shown in FIG. 4 can be replaced with the delay circuit shown in FIG. 5.

In the delay circuits of FIGS. 1, 4, and 5, the first and second comparators have open emitter outputs, but even if they are replaced with open collector output comparators,
It is possible to obtain 1% performance such as fFr+.

〔Effect of the invention〕

The present invention is 1 minute larger than the conventional method, and therefore the rise and fall can be changed independently, making it easy to adjust the timing of one other device that can synchronize the timing with high precision. .

ij! There is no need to open on time. Also, this control voltage is.

Since it is a normal voltage in the FCC and Fix, matching with the D/A converter is easy. By increasing C, we can obtain a maximum variable delay time up to the μ order, and ′. With a maximum variable delay time of a few percent beast,
number? Since only a capacitance of F is required, and the comparator, switch circuit, and capacitor can be manufactured using a normal bipolar IC process, it is also possible to use a monolithic IC.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the invention, FIG. 2 is a diagram of each waveform in the circuit of FIG. 1, and FIG. 3 is a delay characteristic diagram of FIG. 1.
4 and 5 are circuit diagrams of other embodiments of the present invention, and FIG. 6 is a conventional delay circuit IK. FIG. 7 is a diagram of each waveform in the circuit of FIG. 6, and FIG. 8 is a delay characteristic diagram of the circuit shown in FIG. 1・・・・・・・・・・・・・・・・・・・・・Atsu-no comparator 2・・・・・・・・・・・・・・・・・・・・・
・Second comparator 4・・・・・・・・・・・・・・・
−・・・First resistance 3・・・・・・・・・・・・・
...Second resistor 5...
・-・・Third resistor C1~C1・・・・・・・・・・
・Capacitor Sw1'Sw+%・Raw・Switch

Claims (1)

[Claims] 1. Between the affirmative or negative output of the first comparator related to the open emitter or open collector output and the negative or positive input of the second comparator, A circuit is installed that changes the capacitance of the integrating circuit by turning on and off the capacitor using switches connected in parallel.
A constant DC comparison voltage is applied to the other input terminal of the second comparator, and the switch is turned on.
A delay circuit characterized in that it is configured to be turned off to change the capacitance and to change the delay time. 2. In the device according to claim 1, the switch and the capacitor are connected in series, and they are connected in parallel, one of which is connected to a negative power supply through a first resistor, Also, the second comparator is connected to the open emitter output terminal of the first comparator through a second resistor, and the other is connected to a positive power supply, and the connection point between the positive output of the open emitter and the second resistor is connected to the second comparator. A delay circuit configured to connect negative inputs of the second comparator with a third resistor and provide a DC potential as a comparison voltage of the second comparator. 3. A delay circuit in which two or more of the circuits according to claim 1 or 2 are connected in series and the delay times of the leading edge and trailing edge of a pulse are independently set. 4. A delay circuit according to claim 1, 2, or 3, in which all the components used in the circuit are components that can be made into a monolithic IC.