JPH03211874A - Memory cell for nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain an EPROM cell which is normally operated even at low and high voltages by applying a low or high voltage to a second control gate in response to a high or low power source voltage of a semiconductor memory. CONSTITUTION:A second control gate CG2 is a diffused layer (an N-type layer in the case of a P-type substrate) formed on a substrate SUB. In the equivalent circuit of this memory cell, as shown in Fig. (d), a first control gate CG1 has a capacity CCF1 for a floating gate FG, and the gate CG2 has a capacitance CCF2 for the gate FG. When two control gates are provided and the voltages VCG1, VCG2 are applied, a voltage VFG is applied to the gate FG, the voltages VCG1, VCG2 of the gates CG1, CG2 are altered by high, low power source voltages, thereby obtaining an EPROM cell which normally operates at high and low voltages. Thus, the cell which normally operates at low and high voltages is obtained.

Description

[Detailed Description of the Invention] [Summary of the Invention] An object of the present invention is to provide an EFROM cell that operates normally at both low and high voltages with respect to a memory cell of a non-volatile semiconductor memory device, and to provide an EFROM cell that operates normally at both low and high voltages. In a memory cell of a nonvolatile semiconductor memory device in which a floating gate and a control gate are formed on a semiconductor substrate between these source and drain regions via an insulating film, a second control capacitively coupled to the floating gate is formed. A gate is provided, and a low or high voltage is applied to the second control gate depending on whether the power supply voltage of the semiconductor memory device is high or low.

[Industrial application field]

The present invention relates to a memory cell of a nonvolatile semiconductor memory device.

EFRO is a typical non-volatile semiconductor memory device.
M is widely known.

Generally, EFROM operates on a power supply of about 5V, but it requires 1V when installed in small capacity devices that operate on batteries.
．． It is desired to operate at a low voltage such as 5V. The present invention relates to an EFROM memory cell structure that can operate at normal voltages (5V) or low voltages (1.5V).

(Prior art) An EFROM memory cell is as shown in Fig. 3. 5IJB is a P-type silicon substrate, FC is a floating gate made of polycrystalline silicon, and CG is also made of polycrystalline silicon. control gate,
S and D are N-type regions formed by implanting, for example, arsenic (A s ) ions into the substrate SUB, and function as a source region and a drain region.

This memory cell has a structure in which there is another gate (floating gate) below the gate of the N-channel MOS transistor.

When ultraviolet rays are irradiated, charges escape from the floating gate FC, and the charge of FC becomes O. In this state, if an appropriate voltage is applied to the control gate CG, the transistor (
memory cell) becomes conductive. control gate C
When a high voltage is applied to G and the drain D, avalanche breakdown occurs, and some of the high-energy electrons are captured by the floating gate FC. Then, since there is a charge (electron) in the floating gate FG, the dark value increases, and even if a voltage is applied to the control gate CC, the transistor does not conduct. The presence/absence of charge in this floating gate FC is made to correspond to the data I10, thereby making it possible to store (write) and read information. Erasing is performed by ultraviolet irradiation.

EPROM stores system control programs,
It is often used to store large amounts of data. When such a device is miniaturized into a laptop type or the like and driven by a battery, it is required to operate even at that low voltage. However, in conventional EPROM cells,
The threshold value vth at the time of conduction is as high as about 1°5.

Examples of conventional cell dimensions are shown in FIGS. 4(a) and 4(b), and their equivalent circuit is shown in FIG. 4(C). In the width direction, floating gate FC and control gate CC overlap,
The width W of these is 1 μm, and the width W2 of the source and drain is 2
FC protrusion length W3 from μm, S, D is 4um, C
The interval gI between G and FG and the interval g2 between FG and SOB are both 350 people.

CG, FC, and SUB are opposed to each other via an insulating layer, so they form a capacitor, and the capacitances of CG and FG are CcF and F.
The capacitance CFS of G and SUB are connected in series as shown in FIG. 4(C). Assuming that the potential of the floating gate FC is the charge in VFC1FC and QFG is the potential of the control gate CG, and VC(i is the potential of the control gate CG), the following equation holds true.

Here, Cct/(CCF+CFS) is called the C ratio.

The larger this value, the more VF when conducting, that is, when QFc-0.
C, becomes a value close to VCG, making it easier to operate at low voltage. Therefore, for low voltage use, increase the C ratio and change VFG to VCG.
It is better to bring it closer to the voltage and lower the vth equivalently.For high voltage applications, conversely, it is better to reduce the C ratio (and increase the vth).However, when it comes to dual use for high and low voltages, changing the C ratio alone is not enough. .

In the above dimensions, Ccy=IO, IIfF, CFs=
It becomes 2.02 fP (here f = 10-15). This memory cell is a transistor that becomes conductive at Vrc=IV. When conductive, Q, , = O, and when non-conductive, 2 is applied to FG.
Suppose that 50,000 charges are stored. The threshold value vth of this transistor as seen from the control gate CG is 1.2V in the conductive state and 5.18V in the non-conductive state.Assuming that the power supply Vcc is 5μ±10%, when Vcc=5°5V, it is non-conducting. It should be conductive, but it becomes conductive, and it does not work properly.

As shown in FIG. 5, the protrusion length W of the FC from S and D is determined in order to reduce the C ratio with other dimensions being the same.

is 2 μm, which is half of the case in Figure 4, then CCF=6
．． 07fF (Crs = 2.02fF unchanged), and vth seen from the control gate CG is 1 in the conductive state.
33■, 7.93V in non-conducting state, Vcc = 5V
It works normally at ±10%, but Vcc=1.5±10%
In such a low voltage power supply, when Vcc=1.35V, there is almost no difference from the above-mentioned 1.33V, and there is a possibility that conduction will not occur.

[Problem B that the invention attempts to solve] In this way, in EPROM cells, when the C ratio is increased, conduction/
Vth in the non-conducting state decreases, causing problems in high voltage operation,
If the C ratio is made small, vth in the conducting/non-conducting state becomes "2", making it difficult to operate at low voltage.

If the power supply has low and high voltages, one method would be to manufacture EFROMs separately for high voltage and low voltage and use the one suitable for each, but in this case, two types of EFROM
M must be produced, which is uneconomical.

Therefore, an object of the present invention is to provide an EPROM cell that operates normally at both low and high voltages.

Means for Solving 1 Problem] As shown in FIG. 1, in the present invention, a second control gate CGz is provided. FIG. 1(a) is a schematic plan view, and FIG. 1(b) is a cross section taken along line AA of this figure, and FIG. 1(C) is a cross section taken along line BB. In this example, the second control gate cc is a diffusion layer (an N-type layer in the case of a PM board) formed on the substrate SUB, but this is not a wiring on the substrate as shown in Fig. 1(e). You can.

The equivalent circuit of this memory cell is as shown in Fig. 1(d), where the first control gate CG has a capacitance CCFI with respect to the floating gate FC, and the second control gate CG has a capacitance CCFI with respect to the floating gate FC. In contrast, it has a capacitance CCFZ.

[Function] Two control gates are provided, and voltage VCG1 is applied to these gates.
．． (2) When CC2 is added, the voltage VFG of the floating gate FC becomes as shown in the following equation.

This first. Second control gate voltage V CGI
, By changing V CG2 between high and low power supply voltages, EPROM can operate normally at both high and low voltages.
cell is obtained.

For example, Ccr+=8.09fF, Ccpz=2.02
fF, CFS-2,02fF, and the memory cell is Vp
Assuming that the transistor conducts at c=IV, the threshold value vt as seen from the first control gate (CG) during conduction/non-conduction
h is 1.49V in the conductive state (QFG=o) and non-conductive state (Q,) when Vcaz=OV when the power supply Vcc=5V.

= 25XlO' electrons), it becomes 6.42V, and Vcc is 1
Even if the value is increased or decreased within the 0% range, there is no problem and it operates normally.

Also, when Vcc=1.5V, Vccz=1.5
If V, then vth seen from CG1 is 1.
2V, 5.18V in non-conducting state, Vcc is 10
It works normally even if it is increased or decreased within the % range.

[Example] To give an example of the dimensions of this memory cell, W in FIG.
The width of L, FC, CG, is 1 μm, Wz, the width of source/drain is 2 μm, the protrusion length W6 of FG from S, D is 1 μm, and the distance W4 between S, D and CC is 2 J! 7 m,
The width W of CG2 is 2 am, and the protrusion length W7 of FC from CGz is 1 μm. The total length of FG is 8 μm
It is. Also, the interval g1 between CG and FG, FC and SUB
The interval g2 of both is 350 people.

FIG. 2 shows a memory device using this memory cell. 10
is a cell matrix, and the memory cells M, , , in FIG.
, M, □, ......, words MW L ,, W
L2+... and bit line B L 1. B L
They are arranged at each intersection of z,... For more information,
The drain D of the memory cell M,1 is connected to BL, and the first control gate CG is connected to the word line WL (WL and CG are integrated). Other memory cells M1□,
... also conforms to this. The second control gate CG2 of each memory cell is connected to the switching line SL (CG2
and SL are integrated), and the switching line SL is the CMOS inverter 18.
connected to the output end of the 12 are word lines WL, , WL
2+...) X decoder that performs R, 16 is a Y decoder, and bit lines BL,, BL,,...
Turns on/off Y days 1-14 for selection.

The source S of each memory cell is connected to the ground, and this is done by a ground line GND as shown in FIG. 2(b). The shaded area in FIG. 2(b) is the floating gate FC.

When operating this memory device with a high voltage power supply, the signal φ is set to H (high) level, and the P-channel transistor Q1
is turned off, the N-channel transistor G2 is turned on, and the switching line SL and therefore the second control gate CG2 are set to OV. When operating this memory device at low voltage, the signal φ is set to L, transistor Q1 is turned on, and transistor G2 is turned off.
The switching line S1 is connected to the power supply voltage Vcc (this is 5■ or],
5) Set the voltage to 1.5 V). This allows it to operate normally at both high and low voltages, as mentioned above.

This E F ROM reading is similar to the known one, and
The decoder 12 selects a word line and sets, for example, WL to VCC, and the Y decoder 16 selects a bit line and connects, for example, BL to a sense amplifier (not shown).
In this way, in this example, memory cell M1 is selected, and if charge is injected into the floating gate of this memory cell, it is turned off, and if no charge is injected, it is turned on, and the bit line B
Since current flows or does not flow through L, the stored data cannot be read. The difference from known lEPROMs is that if the power supply Vcc is a high voltage, φ is set to H1, and if the power supply Vcc is a low voltage, φ is set to L.

In addition to Vcc and 0■, the voltage applied to the switching line SL is (2)
Other voltages (such as voltages between Vcc and 0.times.) that make VFG in the equation a suitable value may be used.

C. Effects of the Invention] As described above, according to the present invention, an EFROM that operates at a low voltage even at a high voltage can be obtained. Since the wiring of the second control gate for high/low voltage operation may be common to each memory cell, the wiring does not become so complicated.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a detailed explanatory diagram of the present invention, FIG. 3 is an explanatory diagram of an EFROM, and FIGS. 4 and 5 are explanatory diagrams of dimensions, etc. of an EFROM cell. In Figure 1, SUB is the semiconductor substrate, S is the source region, D is the drain region, FG is the floating gate, CG, , C
G2 is the first and second control gates. Applicant Ir Shitsu stock% formula% Original of the present invention 11B! Figure 1 Detailed explanation of the invention Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. Source and drain regions are formed on a semiconductor substrate, and a floating gate (FG) and a control gate (CG_1) are provided on the semiconductor substrate between these source and drain regions with an insulating film interposed therebetween. In the memory cell of the nonvolatile semiconductor memory device, a second control gate (CG_2) is provided which is capacitively coupled to the floating gate, and the second control gate is provided with a low voltage depending on the high or low power supply voltage of the semiconductor memory device. A memory cell of a nonvolatile semiconductor memory device, characterized in that a high voltage is applied thereto.