JPH03211872A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve high frequency characteristic of a bipolar transistor, to improve breakdown strength of a MOS transistor and to form an accurate capacitance element by employing a nitrite film. CONSTITUTION:In order to improve high frequency characteristic of bipolar transistor, a field film between an emitter 9 and a base 8 is formed of a nitrite film 11. Then, elements of a MOS transistors are isolated by an isolating method by a combination of an element isolating oxide film (LOCOS film) 14 and the film 11, and further a capacitance element structure is formed of an MNS capacitance using the film 11. Thus, the high frequency characteristic of the bipolar transistor is improved, an element isolating breakdown strength upon high integration of the MOS transistor is improved, and a capacitance element having an MNS(Metal-Nitrite-Semiconductor) structure is obtained as a capacitance element having a high accuracy and high unit capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a bipolar transistor with excellent high frequency characteristics, an improvement in the element isolation breakdown voltage of a MOS transistor that uses a thick thermal oxide film for element isolation, and a method for achieving high accuracy. The present invention relates to a method for manufacturing a semiconductor device that also includes the formation of a capacitive element.

Background of the Invention In recent years, the so-called B r CMOS process, in which bipolar transistors and MOS transistors are formed on the same substrate, has been developed to overcome problems that had previously been considered mutually exclusive due to the combination of the high speed of bipolar transistors and the low power consumption of MOS transistors. It has attracted attention as a means of solving this problem. In particular, it is most frequently used in analog and digital mixed circuits, and recent market trends have shown a strong tendency to develop products into system-on-chip systems, which will likely be realized in the near future.

A semiconductor device formed by conventional BICMO3 technology will be described below. Figure 4 shows the conventional BICMO
FIG. 8 is a cross-sectional structural diagram of a semiconductor device formed using the No. 8 technology.

P-type silicon substrate 21. N+ type buried layer 22゜P゛ type buried layer 23. N-type Evita Kinyal layer 24, P-type well separation layer 25. Collector all layer 26 of N” type bipolar region. Base layer 27 of bipolar region. Emitter layer 28 of bipolar region. Collector contact layer 281
．． Oxide film for element isolation (LOGO3 film) 29. Polysilicon 30, gate oxide film 31. MOS region source/drain layer 32°CVD film 33. It is composed of an aluminum electrode 34.

A method for manufacturing a semiconductor device configured as described above will be briefly described. First, an N° type buried layer 22 and a P+ type buried layer 23 as shown in the figure are formed on a P type silicon substrate 21, and then epitaxial growth for special growth of a bipolar transistor is performed to form an N− type epitaxial layer 2 on the entire surface.
4 is formed, and each element is formed thereon. The bipolar transistor has an N1 collector all layer 26. Base layer 27, emitter layer 28 and collector contact layer 28
1, and element isolation is performed by PN vertical isolation using a P° type buried layer 23 and an upper P- diffusion layer 25. M.O.S.
The transistor uses an LOG OS film 29 for element isolation, the gate electrode is formed of polysilicon 30, and each source/drain region is made of P-channel type using self-line technology using LOCO8 film 29 and upper 29 silicon 30.
An N-channel type is formed. Further, as another element, a capacitive element is shown here as an example. The capacitive element in the conventional example is M O with a thermal oxide film as an insulator.
S (iletal-Oxide-3e+wicond
uctor) capacity, and the formation method is a well-known fact, so it will be omitted.

Problems to be Solved by the Invention However, although it is certainly possible to have a mixed analog and digital circuit configuration using the conventional manufacturing method, when considering recent market trends, there is a strong demand for the following improved characteristics. ing. The first is to improve the withstand voltage of the t4 Ibora transistor or to improve the high frequency characteristics. Second, the reliability of the element isolation breakdown voltage of the transistor is becoming a problem due to the increased integration of MOS transistors. In addition, in the near future (1) it is thought that one system per chip will be developed, but in that case, simply analog and digital will not be enough. These devices are indispensable in order to achieve high functionality in terms of circuit configuration.

As described above, the conventional technology has many difficult parts, which makes circuit design difficult, and also increases the chip size, making it extremely uneconomical. In order to solve the problems of the above-mentioned conventional example, the present invention is particularly aimed at
Focusing on the high functionality of the CMOS process, we are improving the high frequency characteristics of bipolar transistors, improving the element isolation withstand voltage associated with higher integration of MOS transistors, and developing MNS (Metal- N
It is an object of the present invention to provide a capacitive element having an itrite-3 semiconductor structure.

Means for Solving the Problems To achieve this goal, firstly, in order to improve the high frequency characteristics of the IBORA transistor, the field film between the emitter and the base was changed from a conventional thermal oxide film or CVD film to a night light film. Second, the element isolation of the MOS transistor was changed to an isolation method by combining a LOGO8 film and a nitrite film, and third, the capacitive element structure was changed to an MNS capacitor using a nitrite film.

Effects With the above-described structure, firstly, the rate at which holes injected from the base to the emitter on the emitter-base junction of the /Ibora transistor are trapped in the oxide film at the junction is reduced, and the injection efficiency is improved. Further, by employing the so-called self-line technology in which the emitter region is formed using the nitrite film as a mask, it is possible to reduce the emitter size and improve the finished dimensional accuracy. Therefore, it is possible to reduce the overall transistor size and reduce various junction capacitances, especially the emitter-base junction capacitance. Second, LOG is used as element isolation for MOS transistors.
By using an O8 film and a nitrite film, a self-line for forming a transistor region can be formed through the nitrite film.

Therefore, leakage such as bird's beak at the edge of the LOGO3 film is alleviated, so that the avalanche breakdown voltage of the MOS transistor can be improved. In addition, the capacitance structure is changed to LOGO3
Polysilicon is grown on the film, a nitrite film is placed on top of the polysilicon, and an aluminum electrode is attached to the top of the film.The upper electrode of the capacitor is made of aluminum, and the lower electrode is made of polysilicon, which has less voltage dependence and temperature dependence. This makes it possible to reduce stray capacitance.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. Note that the first thing. Second. In FIG. 3, it is assumed that they are formed on the same substrate.

FIG. 1 shows a cross-sectional structure of a bipolar transistor in an embodiment of the present invention, FIG. 2 shows a cross-sectional structure of a MOS transistor in an embodiment of the present invention, and FIG. 3 shows a cross-sectional structure of a capacitive element in an embodiment of the present invention. It is a structural diagram. In FIG. 1, first, an N1-type buried layer (hereinafter referred to as N+ buried layer) 2 and a P°-type buried layer (hereinafter referred to as P° buried layer) are thermally diffused onto a P-type silicon substrate 1 and a P°-type buried layer (hereinafter referred to as P° buried layer) ) form 3. This P+ type buried layer is generally used to separate the upper and lower PN of a bipolar transistor. Next, an N-type epitaxial layer is formed. However, as is generally known, in the BICMOS process, variations in the impurity concentration of this epitaxial layer (especially near the silicon surface) directly contribute to variations in the characteristics of the P-channel MO8 transistor. Use vacuum epitaxial equipment to minimize variation. Next, in order to reduce the parasitic resistance of the collector of the bipolar transistor, we formed a highly concentrated collector all layer 6 in the collector region and made full use of the element isolation technology (LOCO8 method) commonly used in MOS processes, as shown in Figure 2. A LOCO8 film 14 as shown is formed.

At this time, as shown in Figure 2, the source of the MOS transistor
Since the drain region 17 is formed inside the LOCO3 film 14, the LOCO8 film 14 is previously formed to be larger on the outside. Further, in this case, since the bipolar transistor region is entirely covered with the nitrite film, the film length 4 of the LOGO8 film 14 is not increased. However, as shown in FIG. 3, the LOGO3 film 14 has a film length of 4 in the high-precision capacitor formation region. Furthermore, LOC
It is a well-known fact that the channel stopper 18 is formed in the film length 4 of the O5 film 14 by injection, so detailed explanation is omitted. Next, a gate oxide film 15 is formed to form a gate electrode of a MOS transistor, and then a polysilicon film 16 is grown. This polysilicon film is used not only for gate electrodes but also for wiring. Further, in order to reduce the resistance component of the polysilicon film, a high concentration of impurity is doped. Next, in this state, a gate electrode pattern is formed by making full use of lithography technology and dry etching technology. At this time, the polysilicon film 16 and gate oxide film 15 have been removed from all locations other than the MOS transistor region in FIG. 2 and the high-precision capacitor region and polysilicon wiring in FIG. 3, and the surface of the bipolar transistor region is The silicone is exposed.

After forming the gate electrode, P+ ions are implanted only into the bipolar transistor region to form the active base layer 7 shown in FIG.

Note that this formation is performed using only lithography technology, and a resist mask is used as the implantation mask.

Next, a nitrite film 11 is grown on the entire surface with a uniform thickness, and the contact portion of the bipolar transistor region and the M
The element region of the oS transistor region and the contact portion of the polysilicon wiring are anisotropically etched using 02RIH. Note that the nitrite film 11 is grown on the polysilicon film 16 on the high-precision capacitive element, and in order to use this film to form a capacitance, the film thickness is uniform except for the contact area to the polysilicon film 16. It is necessary that the nitrite film 11 remains. Also, as shown in Figure 2, the element area of the MOS transistor is
Etch so that there is a gap of just the same amount. By etching only the contact portion of the bipolar transistor as described in (2) above, the external base layer 8 and the emitter layer 9 and collector contact layer can be formed by self-line.

Next, the external base layer 9 of the bipolar transistor region and the source/drain region of the P-channel type MO5 are formed, and both layers are simultaneously formed by implantation in a self-aligned line. Similarly, the emitter layer 9 and collector contact layer 91 of the bipolar transistor region and the source/drain region 17 of the N-channel MOS are simultaneously formed. Next, after covering the entire surface with a CVD film 12, contact windows for each element are etched by dry etching. For etching at this time, the nitrite film 11
Etching is performed under etching conditions that have a high selectivity for the CVD film 12, so that the nitrite film does not burrow and remains approximately the same thickness as when grown.

In this etching, windows are formed in the entire device except for the isolation region of the bipolar transistor, the contact portion of the MOS transistor, and the contact portion of the capacitive element. In this open state, aluminum electrodes 13 are formed on each element using sputtering, lithography, and dry etching techniques. Thereafter, the entire surface is covered with a CVD film, plasma nitrite film, etc. as a surface protection film.

Effects of the Invention As described above, the present invention provides the following effects by using a nitrite film.

First, since the base and emitter of bipolar transistors are formed using the self-line method, the element size can be reduced (
In particular, the high-frequency characteristics can be improved by changing the emitter size), and by using a nitrite film as the field film on the emitter-base junction, the efficiency of base current injection into the emitter can be greatly improved.

Second, it is possible to improve the avalanche breakdown voltage at the end of the LOGO3 film of the MOS transistor and to eliminate the influence on the transistor caused by the bird's beak of the LOGO5 film.

Thirdly, by using the capacitive structure of borinlicon film-nitrite film-metal, it is possible to form a highly accurate capacitive element with excellent temperature dependence and voltage dependence.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a bipolar transistor according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a high-precision capacitive element according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of an OS transistor and a bipolar transistor formed by a conventional technique.
FIG. 3 is a cross-sectional view of an O8I transistor and a capacitive element. 1...P-type silicon substrate, 2...N+
Type embedding layer, 3...P''' type embedding layer, 4
...N-type epitaxial layer, 5...
P-type separation layer, well layer 6...N° collector all layer, 7...P'' active base layer, 8...
...P+external base layer, 9...N"emitter m, 91--collector contact layer, 10-...-
Thermal oxide film, 11...Nitrite film, 12...
...CVD film, 13...aluminum electrode, 14...
...LOCO5 film, 15...gate oxide film,
16...Polysilicon film, 17...N
+ Source/Drain 1.18...Channel stopper.

Claims (1)

[Claims] In the so-called BICMOS process in which bipolar transistors and MOS transistors are simultaneously formed on the same substrate, the edges of the oxide film for element isolation of MOS transistors are covered with a nitrite film with a certain amount of overlap. a step of forming an element region of a MOS transistor by ion implantation using the nitrite film as a mask; and a step of selectively applying the nitrite film only to a base contact window region and an emitter formation region after forming an active base region of a bipolar transistor. a step of removing and leaving it on the junction between the emitter and base; a step of forming the base and emitter of the bipolar transistor by self-alignment using the nitrite film as a mask; and a step of forming the base and emitter of the bipolar transistor on the oxide film for element isolation of the MOS transistor. A polysilicon film similar to the gate electrode material is grown, a nitrite film similar to that used in the bipolar transistor and MOS transistor is grown on the polysilicon film, and a metal electrode is further grown on the nitrite film. A method for manufacturing a semiconductor device comprising the steps of forming a metal electrode on a polysilicon film on an oxide film for element isolation of a MOS transistor in the same manner as on the nitrite film.