JPH0321153A - Signal device - Google Patents

Abstract

PURPOSE:To prevent a processor from loosing its processing capacity by storing only a necessary fill-in signal(FISU) in a buffer memory even when a terminating node is constituted so as to continuously send plural FISUs. CONSTITUTION:At the time of receiving a signal sent from a line 1, a transmitting/receiving circuit 2 converts the received data into parallel data by serial/parallel converter and outputs the parallel data in each octet. The circuit 2 starts a timing formation circuit 31 and a counter 32 included in a peripheral control circuit 3 and the data are stored by a timing signal formed by the circuit 31 included in the circuit 3 in the order of respective byte registers 6a, 6b, 6c. At the time of counting the signal reception three times, a start signal for a DMA circuit 4 is inputted to the circuit 4. When the contents of the byte register 6a buffering an LI field are not '0', i.e. when the contents are a signal other the fill-in signal (FISU), the signal is transferred to a matching old register and all the contents are stored in a buffer memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a data transmission protocol between two or more nodes based on the international standard CCITT No. The present invention relates to a data transmission device that adopts a transmission method based on the No. 7 common line signaling method, and particularly relates to the Shingetsu device.

[Conventional technology]

In order to carry out switching connections, it is necessary to carry out various types of control + * information between terminals and exchanges, and between exchanges and exchanges. Regarding this signal transmission and reception, the signal method (Signall
ing system) is defined.

The 5th M is No. 7 common line signaling system (cornmon)
channelSignalling system
) is a diagram showing an example of the configuration. In the electronic exchanges 41 and 42, the control devices 43 and 44 of both stations are directly connected by the Nα7 signal line 48 via the signal devices 45 and 46. All control signals for each communication line 47 are transmitted via this common signal line 48, and exchange processing is performed. In this Seed 7 signal system, a fill-in signal (FISU) is used. This FISU is always sent in the sense that it fills the line when there is no message signal (MSU) to be sent. The CCITT recommendation does not specify any FISU transmission cycle. In reality, depending on the capacity of the buffer memory provided in the signal device on the receiving side and the processing capacity of the processor, an arrangement is made between the nodes to transmit data at a certain fixed period.

[Problem to be solved by the invention]

FISU-related transmission and reception processing is normally performed by hardware (firmware), so depending on the processing capacity of the processor, if
If the ISU is constantly transmitted and received, the buffer memory on the receiving side will quickly overflow, causing congestion.

Therefore, if two exchanges with different implementations of signaling equipment are connected using a signaling ring using the A7 signaling system, one side will
If ISU transmission is always performed, while the other is assumed to be transmitted and received at a fixed cycle, the capacity of the receive buffer memory must be made larger than necessary, which increases the overhead of processing and slows down signal processing. There are problems such as a significant downgrade.

[Means to solve the problem]

In order to solve these problems, the signaling device of the present invention uses a link layer protocol that connects two or more nodes via a line. 7 signal system, and includes a reception detection means that detects the received signal (data) and outputs it in octet units, a buffer memory that stores it in octet units in direct memory access mode, and processing means for the above-mentioned positive 7 signal system. Before storing the output data from the reception detection means in the buffer memory, it distinguishes between a fill-in signal (FISU) and other signals (data), and when the fill-in signal is detected, its sequence number and status display bit are determined. It is determined whether the fill-in signal has further changed from the last change, and only the changed fill-in signal is stored in the buffer memory.

[Effect]

Therefore, according to the present invention, only the FISUs that need to be processed can be stored in the 3 x 7 memory without storing all of the received fill-in signals or 9 FISUs in the buffer memory.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signaling device according to the present invention. Here, 1 is a line connecting nodes, 2 is a transmitting/receiving circuit (URT) connected to this line 1 and having the function of serial/parallel converting the received signal (data) and outputting it in 1-octet units, and 3 is a transmitting/receiving circuit. This peripheral control circuit is connected to the circuit 2 and is composed of a timing control circuit 31, a counter 32, and an AND circuit 33. Reference numeral 4 denotes a peripheral control circuit 3 and a DMA (direct memory access) circuit connected thereto, which is composed of an address generation circuit 41, a write control circuit 42, and an AND circuit 43.

Reference numeral 5 denotes a buffer memory for storing signals detected by the transmitter/receiver circuit 2 in units of one octet depending on the DMA mode of the DMA circuit 4. 1 and N6al6b and 6c are byte registers that sequentially hold signals detected by the transmitter/receiver circuit 2;
Reference numerals 7a and 7b are match circuits that compare the contents held in each byte register 6b and 46C with the contents held in each register 8al8b, respectively. The display bits retain the last change. Reference numeral 9 indicates a memory read line for data of the host CPU, and reference numeral 10 indicates a control signal line during memory read.

Then, before storing the received data from the transmitting/receiving circuit 2 in the buffer memory 5, it is determined whether the FISU and the previous signal are the same, and when the FISU is detected, its sequence number and status display bit have changed last. Each match circuit 7a, 7b determines whether the contents have changed further, and only the FISU that has changed is stored in the buffer memory 5. In addition, each terminal in Figure 1, ■
~■ are connected to terminals with the same number.

Next, the operation of the above embodiment will be explained with reference to FIG. 2 and FIGS. 3 and 4. Here, FIG. 2 is an operation time chart of the embodiment, FIG. 3 is its flowchart, and FIG.
The figure shows the format of the received signal, and in Figure 4, symbol F
is the flag, and BSN is the backward sequence number.
BIB indicates backward status indication bits, respectively. Also,
FSN indicates a forward sequence number, FIB indicates a forward status indication bit, and LI indicates a signal length. When LI of [,■=oJ, FISU is obtained. However, P
RI indicates a priority display field. The signals shown in FIGS. 2(g) to 2(g) are represented by symbols a to g, which are attached to each part of FIG. 1.

Then, when the button shown in FIG. 3 is pressed and the transmitting/receiving circuit 2 receives the signal (data) sent from the line 1 (step 2
0), this transmitter/receiver circuit 2 converts the received data into serial/parallel and outputs it in l octet units, starts the timing generation circuit 31 and counter 32 in the peripheral control circuit 3, and the data is converted into The timing signals generated by the timing generation circuit 31 in the peripheral control circuit 3 are stored in each byte register 5a, 5b and 6c in this order (see 21 and FIGS. 2(-) and 2(b)). After counting the number of signal receptions three times, the activation signal for the DMA circuit 4 (FIG. 2(g)) is input to the circuit 4. At this time, if the content of the byte register 6a where the LI field is buffered is not "0" (22), that is, F
If it is a signal other than ISU, the signal is transferred to the old match register (see Section 28 and Figure 2 (d)) and stored in the buffer memory 5 (see Section 28 and Figure 2 (e)). (f) ). When LI=0, the sequence number (FSN, BSN) at the time of FISU detection
, the status display bits (FIB, BIB) are compared with the last changed contents (FIG. 23-26 and FIG. 2(C)).

In other words, the received FSN and F I are stored in the byte register 6b.
B is buffered and the last changed BS is stored in register 8b.
N, BIB are held, and match circuits γa, 7 are held, respectively.
A match is made in step b (Fig. 2 (d)), and if they are not equal, an instruction is given to the DMA circuit 4 (Fig. 2 (g)) to store it in the bathophore memory 5 (11). ■ Signal, 2nd
1a (g) QAND signal) and simultaneously transfer its contents to byte register 6b→register 13a, byte register 6C→register 8l). If they are equal to 1, the FISU is unnecessary and the operation is not stored in the buffer memory 5. The data stored in the buffer memory 5 is read out by the control device or Hcpv (processor) shown in FIG. 5, and then processed as control information.

In this way, according to this embodiment, instead of storing all received FISUs in the buffer memory 5, only the FISUs that require acknowledgment processing are stored in the buffer memory, so that the first three otates of the received signal are stored in the buffer memory 5. By comparing only the FISU with the content that changed at the end of the previously received signal and storing only the changed FISU in the puffer memory 5, it is possible to use a certain amount of puffer memory capacity regardless of the FISO transmission period of the other node. It has the advantage of being able to respond.

〔Effect of the invention〕

As explained above↓, the present invention allows the necessary FISU to be
By storing only U in the buffer memory and discarding the others, there is an effect that the capacity of the buffer memory 8 can be reduced without any reduction in the processing capacity of the processor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of its operation, FIG. 3 is a flowchart explaining the operation of the second embodiment, and FIG. 4 is a diagram of the received signal. A diagram showing the format, FIG. 7 is a specific configuration diagram of a 7-signal system. 1... Line, 2... Transmitting/receiving circuit (URT), 3
...Peripheral control circuit, 4...DMA circuit, 5●...
...Buffer memory L 5a, 5b, 5c...-Byte register, 7a, 7b●●●●Match circuit, 3a, g
b...Register, 9...Nomolylide wire, 10...
...Memory control line.

Claims (1)

[Claims] CCITT No. 1 is a link layer protocol that connects two or more nodes via a line. 7 signal system, a reception detection means that detects the received signal (data) and outputs it in octet units, a buffer memory that stores it in octet units in direct memory access mode, and the above-mentioned No. 7 signal system. 7 signal system processing means, which processes a fill-in signal and other signals (data) before storing the output data from the reception detection means in the buffer memory.
When the fill-in signal is detected, it is determined whether the sequence number and status display bit have changed further from the last change, and only the changed fill-in signal is stored in the buffer memory. A signaling device characterized by: