JPH0321123U - - Google Patents
Info
- Publication number
- JPH0321123U JPH0321123U JP7871989U JP7871989U JPH0321123U JP H0321123 U JPH0321123 U JP H0321123U JP 7871989 U JP7871989 U JP 7871989U JP 7871989 U JP7871989 U JP 7871989U JP H0321123 U JPH0321123 U JP H0321123U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signal line
- signal processor
- resistor
- protection device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Emergency Protection Circuit Devices (AREA)
- Power Sources (AREA)
Description
図面は本考案装置の一実施例を示す概略構成図
である。
１ａ，１ｂ……信号処理器本体（本体）、２ａ
，２ｂ……通信回路、３ａ，３ｂ……ヒユーズ、
ｌ０……基準信号線。
The drawing is a schematic diagram showing an embodiment of the device of the present invention. 1a, 1b...Signal processor main body (main body), 2a
, 2b... communication circuit, 3a, 3b... fuse,
l 0 ...Reference signal line.
Claims (1)
信号処理器の保護装置であつて、 前記信号線のうちの基準信号線に、抵抗体を直
列に接続するとともに、その抵抗体に前記両信号
処理器間に電位差が発生したときにその基準信号
線に流れる電流によつて切断されるヒユーズを並
列に接続したことを特徴とする信号処理器の保護
装置。[Claims for Utility Model Registration] A protection device for a signal processor connected to an external signal processor by a signal line, wherein a resistor is connected in series to a reference signal line among the signal lines. A protection device for a signal processor, characterized in that the resistor is connected in parallel with a fuse that is disconnected by a current flowing through the reference signal line when a potential difference occurs between the two signal processors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989078719U JPH0620183Y2 (en) | 1989-07-05 | 1989-07-05 | Signal processor protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989078719U JPH0620183Y2 (en) | 1989-07-05 | 1989-07-05 | Signal processor protector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0321123U true JPH0321123U (en) | 1991-03-01 |
| JPH0620183Y2 JPH0620183Y2 (en) | 1994-05-25 |
Family
ID=31622237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989078719U Expired - Lifetime JPH0620183Y2 (en) | 1989-07-05 | 1989-07-05 | Signal processor protector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620183Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5313324A (en) * | 1976-07-22 | 1978-02-06 | Mitsubishi Electric Corp | Input/output device |
| JPS61208137A (en) * | 1985-03-12 | 1986-09-16 | Fujitsu Ltd | Automatic fault recovery bus control system |
-
1989
- 1989-07-05 JP JP1989078719U patent/JPH0620183Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5313324A (en) * | 1976-07-22 | 1978-02-06 | Mitsubishi Electric Corp | Input/output device |
| JPS61208137A (en) * | 1985-03-12 | 1986-09-16 | Fujitsu Ltd | Automatic fault recovery bus control system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0620183Y2 (en) | 1994-05-25 |