JPH03209874A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To sharply increase a semiconductor integrated circuit device in number of thermal without enhancing a chip in size by a method wherein a conductor pad is formed on the rear of a low resistive region, and the pad concerned is used as an input-output terminal. CONSTITUTION:A high concentration semiconductor region 11 is provided penetrating through a semiconductor chip, a conductive layer (pad) 12 is formed on the surface of the high concentration semiconductor region 11 on the rear side of the chip to serve as a terminal, and the through high-concentration semiconductor region 11 is brought into direct contact with the collector region of a bipolar transistor or indirectly connected to the source, the drain or the gate electrode of a MOSFET through the intermediary of a conductive layer 6 formed on the surface of the chip. By this setup, a large number of input- output terminals can be led out from not only the front side but also the rear side of the semiconductor chip, so that a semiconductor integrated circuit device of this design can be sharply increased in number of terminals without increasing it in size.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit technology and a technology that is particularly effective when applied to electrode structures in semiconductor chips, such as a method for taking out input/output terminals of bipolar LSIs. Regarding effective techniques.

[Prior Art] Conventionally, in planar semiconductor integrated circuit devices, it has been common practice to provide pads only on the chip surface on the side where elements are formed, and to take out power supply voltage terminals and signal input/output terminals from one side of the chip. . Therefore, even in the LSI class, the maximum number of terminals is 200 using the wire bonding method;
CB (Controlled Co11apse
There were approximately 500 pieces using the bonding method.

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit device, terminals are taken out from only one side of the chip, so the number of terminals is limited to about 600. However, as LSIs become more highly integrated in the future, there is a trend toward smaller chip sizes and larger circuits, and the conventional method of bringing out terminals from only one side cannot meet the demand for multi-terminals. This problem has arisen.

In addition, a proposal has also been made for a method of taking out terminals from the back side of a semiconductor chip (IEEE).

15SCC32 (1989) pp182-183).

However, the above proposal concerns the power supply voltage terminal, and involves forming a back metal layer over the entire back surface of the chip, supplying the power supply voltage Vee from the back surface of the chip, and creating a buried layer formed to penetrate through the chip. The power supply voltage Vee is taken out to the chip surface side through the capacitor. Therefore, although it is useful for stabilizing the substrate potential, it is not a technology that can contribute much to increasing the number of terminals.

The purpose of the present invention is to
An object of the present invention is to provide a semiconductor integrated circuit technology that can dramatically increase the number of terminals of a semiconductor integrated circuit device.

The above-mentioned and other objects and novel features of the present invention will become apparent from the description of the present specification and the attached drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a high concentration semiconductor region is provided that penetrates the semiconductor chip, a conductive layer (pad) is formed on the surface of the back side of the chip to form a terminal, and this through high concentration semiconductor region is The MOSFET can be connected directly to the collector region of the bipolar transistor, or indirectly through a conductive layer formed on the chip surface.
The device is connected to the source, drain or gate electrode of the device.

[Function] According to the above-described means, it becomes possible to take out a large number of exposed horn terminals not only from the front side of the semiconductor chip but also from the back side, so the number of terminals can be dramatically increased without increasing the chip size. The above purpose can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to an output terminal of a bipolar LSI.

In the figure, 1 is a P-type semiconductor substrate such as single-crystal silicon, 2 is an epitaxial layer grown on the substrate 1 in a vapor phase, 3 is a P-type base region formed on this epitaxial layer 2, and 4 is a P-type base region formed on the epitaxial layer 2. This is an N-type emitter region formed on base region 3.

Further, 5 is a field oxide film for element isolation formed so as to incorporate the epitaxial layer 2 in the element forming region;
is an N-type buried layer 6 as a collector region formed in advance below the element formation region, and this N-type buried layer 6 is doped with N-type impurities by ion implantation or diffusion before the growth of the epitaxial layer 2. It is formed by

Furthermore, 7 is an N-type semiconductor region formed to reach the N-type buried layer 6 from the substrate surface as a collector pull-up port, and 8 is for preventing leakage current due to a parasitic MOS transistor between the buried layers of adjacent bipolar transistors. P-type semiconductor regions 9a, 9b, and 9c are a base electrode, an emitter electrode, and a collector electrode, respectively, made of an aluminum layer or the like.

The structure up to this point is the same as one of the known vertical bipolar transistors, but it is also the same as other known transistor structures such as a self-aligned bipolar transistor whose emitter region is formed by diffusion of impurities from polysilicon. You can.

In the transistor of the embodiment shown in FIG. 1, a low resistance region, that is, a high concentration N A type semiconductor region 11 is formed, and a pad 12 having a relatively large area and made of a conductor such as aluminum is formed so as to be in contact with the surface (lower surface) of this N-type semiconductor region 11.

Therefore, by connecting one end of the bonding wire to this pad 12 or placing a CCB solder ball on it,
Can be used as an output terminal.

Note that, since the collector terminal of the transistor of this embodiment is connected to the output terminal, it is suitable for use as a transistor on the pull-down side of a totem ball type output circuit.

The N-type semiconductor region 11 is formed by forming an insulating film 13 such as a silicon oxide film or a silicon nitride film on the back surface of the substrate l, forming an opening in the insulating film 13, and using the insulating film 13 as a mask to inject N from below the substrate. It may be formed by implanting type impurities by ion implantation and heat-treating. However, since the semiconductor substrate 1 is relatively thick, it may be difficult to form a deep N-type semiconductor region 11 that reaches the N-type buried layer 6 by ion implantation.

FIG. 2 shows an example of the structure of an output bipolar transistor in which it is easy to form an N-type semiconductor region 11 that almost penetrates the substrate. That is, in the transistor of this embodiment, the groove 14 is formed from the bottom surface of the substrate 1 below the N-type buried layer 6, so that the substantial thickness of the substrate is thinned so that the N-type semiconductor region 11 becomes shallow. is formed.

In this case, since the area of the groove 14 is relatively small, the pad 1
It is best to extend 2 to one side and perform bonding on the smooth part.

Note that the trench 14 may be formed by anisotropic dry etching or the like using the insulating film 13 as a mask before the formation of the N-type buried layer 6 or immediately before or after the growth of the epitaxial layer 2.

Figures 3(A) to 3(F) show modified examples of the above-mentioned grooved type collector terminal extraction type transistor, in which the grooves are filled with polysilicon to improve the smoothness of the back surface. be.

In this embodiment, an insulating film 13 made of a silicon oxide film or a silicon nitride film is first formed on the back surface of a P-type semiconductor substrate 1, and openings 13 are formed in this insulating film 13 corresponding to the element forming regions.
form a. Then, using the insulating film 13 as a mask, a groove 14 having a depth of several 10 to several 100 .mu.m is formed on the back surface of the substrate 1 by anisotropic dry etching (FIG. 3(A)).

Next, using the insulating film 13 as an ion implantation mask, N-type impurities are implanted from the back surface of the substrate and subjected to heat treatment to form a high concentration N-type semiconductor region 11 that reaches near the surface of the substrate (FIG. 3(B)). .

Then, polysilicon containing N-type impurities is deposited on the back surface of the substrate, etched back, the trench 14 is filled with polysilicon 15, and the surface is oxidized (see Fig. 3).
C)).

Thereafter, an insulating film 16 is formed on the surface of the substrate 1, and an opening 16a is formed in the insulating film 16 corresponding to the element formation region.

Then, using the insulating film 16 as an ion implantation mask, N-type impurities are implanted and heat-treated to form the N-type semiconductor region 1.
Form an N-type buried layer 6 that partially overlaps 1 (FIG. 3(D))
).

Next, after removing the insulating film 16, a low concentration N-type epitaxial layer 2 is grown in a vapor phase on the surface of the substrate 1 (FIG. 3(E)).

Thereafter, a field oxide film 5 for element isolation, base, emitter, and collector pull-up regions 3, 4.7 of bipolar transistors, and their electrodes 9a to 9C are formed around the element formation region by a known bipolar LSI process. At the same time, after forming an opening 13b in the insulating film 13 on the back surface of the substrate 1 with the same thickness as that used for trenching or a slightly smaller opening 13b in an arbitrary step, the polysilicon 16 is exposed by etching, and then the entire back surface of the substrate is etched. An aluminum layer is deposited on the pad and patterned to form the pad 12 (
Figure 3 (F)).

FIG. 4 shows another configuration example of the output bipolar transistor in which the N-type semiconductor region 11 penetrating the substrate 1 can be easily formed.

This embodiment uses a substrate having an S○■ (silicon-on-insulator) structure.

In this embodiment, before joining the two substrates, an insulating film 18 such as a thermal oxide film is formed on the back surface of the upper silicon substrate 1, and openings are formed in this insulating film 18 corresponding to the element forming regions. 18a is formed, and an N-type semiconductor region that will become the N-type buried layer 6 is formed by ion implantation from this opening 18a. On the other hand, the lower silicon substrate 20 has a -
A through hole 21 with a large circumference is formed. Then, after bonding the substrate 20 to the back surface of the substrate 1, a conductor such as polysilicon or a high melting point metal is deposited on the back surface of the substrate 2o, and etched back to fill the through hole 21 with the conductor. In addition to forming the lead-out area 22, the entire lower surface of the substrate 20 is made smooth.

Then, the upper silicon substrate 1 is polished from above using a single-side polishing device with the lower surface of the substrate 2o as a reference to a thickness such that the buried layer 6 is exposed, and then an epitaxial layer is grown in a vapor phase. Thereafter, the base, emitter, and collector lifting regions 3, 4.7 and their electrodes 9a are
~9c etc. are formed, and an aluminum pad 2 is formed on the back surface of the substrate 20 to contact the surface of the conductor in the through hole 21.
4 is formed.

In this embodiment, even if the back surface extraction region 22 (N-type semiconductor region 11 in FIG. 1) is formed larger than the N-type buried layer 6, it will be insulated by the insulating film 18 and will not be short-circuited with other elements. Since there are no holes, the resistance of the back surface extraction region 22 can be lowered without reducing the degree of integration.

FIG. 5 shows an embodiment in which the present invention is applied to the output J terminal of an 0MO8LSI.

In this embodiment, source and drain regions 31a of an N-channel MO8FET Q are formed on the surface of a P-type silicon substrate 1.
, 31b are also N-well regions 3 formed on the substrate surface.
2, source and drain regions 33a and 33b of a P-channel MO8FET Q are formed.

In addition, near the output MO8FETs Q, ,Q,
N-type semiconductor region 34 formed by ion implantation from the substrate surface
and N-type semiconductor region 3 by ion implantation from the back side of the substrate.
5 are formed so as to be in contact with each other and to penetrate through the substrate 1. The aluminum pad 12 is in contact with the lower surface of the lower N-type semiconductor region 35 .

On the other hand, on the surface of the upper N-type semiconductor region 34, an output M
Drain regions 31b and 33 of O8FET Q and Q2
The aluminum wiring 36 extending to b is in contact with the aluminum wiring 36 . This allows the output signal to pass through the N-type semiconductor region 34.
．． 35 and the aluminum pad 12, it can be taken out from the back surface of the board.

In this embodiment, the other end of the aluminum wiring 36 is connected to M
Drain regions 31b and 33 of OSFETs Q, ,Q,
By contacting the gate electrodes 30a and 30b instead of the gate electrodes 30a and 30b, the aluminum pad 12 is used as an input terminal, and input signals from the outside are passed through the N-type semiconductor region 34, 35 and the aluminum wiring 36 to the MO3FET for input. It can be configured such that it is input to the gate terminal of.

Furthermore, by applying the structure shown in FIG. 5 to a bipolar LSI substrate and bringing the other end of the aluminum wiring 36 into contact with the base electrode, it is also possible to take out the input terminal of the bipolar LSI from the back surface of the substrate.

Furthermore, it is also possible to apply the output terminal extraction method using the SOI structure substrate as shown in FIG. 4 to the input terminal extraction method of the 0MO8LSI shown in FIG.

As explained above, in the above embodiment, a high-concentration semiconductor region is provided that penetrates the semiconductor chip, and pads are formed on the surface of the through-hole high-concentration semiconductor region on the back side of the chip to serve as terminals. This penetrating high-concentration semiconductor region is brought into direct contact with the collector region of the bipolar transistor, or indirectly connected to the source, drain electrode, or gate electrode of the MOSFET via a conductive layer formed on the chip surface. By allowing a large number of input/output terminals to be taken out not only from the front side of the semiconductor chip but also from the back side, there is an effect that the number of terminals can be dramatically increased without increasing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the method applied to take out input/output terminals was explained, but instead of providing the aluminum pad 12 on the back of the board, aluminum wiring can be formed and used for transmitting signals between internal circuits. It is.

In the above explanation, the invention made by the present inventor was mainly applied to bipolar LSI or 0MO3LSI, which is the background field of application, but this invention is not limited thereto;
It can also be used for SI or Bi-0MO8LSI.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, the number of terminals of a semiconductor integrated circuit device can be dramatically increased without increasing the chip size.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing an embodiment of the present invention applied to a bipolar LSI, Fig. 2 is a sectional view showing a second embodiment of the invention applied to a bipolar LSI, and Fig. 3 ( A) to (F) are cross-sectional views showing the third embodiment of the present invention in the order of manufacturing steps.
FIG. 5 is a cross-sectional view showing an example in which the present invention is applied to a 0MO8LSI. 1... Semiconductor substrate, 6... Buried layer, 11...
-Low resistance region (high concentration semiconductor region), 12...pad. /IC+su□

Claims (1)

[Claims] 1. A low resistance region is formed in a part of a semiconductor substrate so as to penetrate the substrate, and the surface of this low resistance region is directly or indirectly connected to the elements formed on the substrate surface. A semiconductor integrated circuit device, characterized in that a pad made of a conductor is formed on the back surface of the low resistance region and connected to an active region, and the pad is used as an input/output terminal. 2. The semiconductor integrated circuit device according to claim 1, wherein an upper portion of the low resistance region is in contact with a collector region of an output bipolar transistor formed on the surface of the substrate. 3. The low resistance region is characterized in that a semiconductor region formed by introducing impurities from the front surface of the substrate and a semiconductor region formed by introducing impurities from the back surface of the substrate are in contact with each other. A semiconductor integrated circuit device according to claim 1 or 2.