JPH03209655A - Magnetic tape reproducing device - Google Patents

Abstract

PURPOSE:To prevent the generation of crosstalk by a simplified circuit by entering a pilot signal as a digital value of an A/D converter and detecting the peak level of a pilot signal from an adjacent track to find out a tracking error. CONSTITUTION:The pilot signal selected by a BPF 16 is synchronized with the pulse of a pilot conversion clock generator 17a and converted into a digital value by an A/D converter 17b. A peak level detector 18 detects the peak level of a digital pilot signal obtained from the adjacent track and sends the detected value to a storage circuit 19 by the output pulse of a pulse generator 15. A subtractor 20 subtracts the output signal of the circuit 18 from the output of the circuit 19 and sends the subtracted result to a storage circuit 21. The output of the circuit 21 is added to a value obtained by subtracting the values of a period calculator 4 and a reference value generator 10 by a subtractor 11 and controlled by a D/A converter 22 and a driver 13 so that the output data of the circuit 21 are turned to zero. Consequently, the heads 2a, 2b can travel on the center of a track to be recorded and crosstalk is not generated between tracks.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a magnetic tape playback device that can be used in digital audio tape recorders, video tape recorders, and the like.

Conventional technology A magnetic recording and reproducing device that performs recording and reproducing using a rotating head,
For example, in a digital audio tape recorder, a signal (called a tracking detection signal) for detecting the positional relationship between the head and the recorded track is recorded at a predetermined location on the track formed on the magnetic tape. A method is used in which this tracking detection signal is used to correctly move the head on the track.
3-177342).

An example of the above-mentioned conventional magnetic recording/reproducing device will be described below with reference to the drawings.

FIG. 7 shows a magnetic tape track pattern on which tracking detection signals are recorded, FIG. 8 shows a recording pattern of tracking signals, and FIG. 6 shows a block diagram of a conventional magnetic recording/reproducing device.

The tracking detection signal in a conventional magnetic recording/reproducing device consists of a pilot signal (hatched area in FIG. 8, 303, 304) that detects the degree of overlap between the head and adjacent tracks from crosstalk, and a synchronization signal (hatched area in FIG. 8) that synchronizes the detection. It consists of the hatched areas 301°, 302, and 302a in the figure.

In FIG. 6, 2a and 2b are a pair of heads that sequentially record and reproduce tracks, 3 is a rotary cylinder to which heads 2a+2b are attached, 1 is a magnetic tape, and 16 is a filter for filtering a pilot signal for tracking from the output of heads 2a+2b. 17 is a rectifier, 14 is a sync signal detection circuit that detects a sync signal from the output of the head 2 al 2 b, 15 is a pulse SPI immediately after the sync signal detection circuit 14 detects the sync signal, and a pulse SPI after a certain period of time. A pulse generation circuit outputs the pulse SP2 twice; 18 is a sample hold circuit that samples and holds the output of the rectifier 17 at the timing of the pulse SP1;
9 is a subtracter that takes the difference between the output signal of the sample and hold circuit 18 and the output signal of the rectifier 17; 20 is a sample and hold circuit that samples and holds the output of the subtracter 19 at the timing of the pulse SP2 output from the pulse generation circuit 15; 9a;
9b is a reel around which the magnetic tape 1 is wound; 8a and 8b are bosses forming a running path for the magnetic tape 1), 5as5b
are a capstan motor and a capstan shaft for running the magnetic tape 1, 6 is a pinch roller, 7 is an FGl that outputs a signal with a frequency proportional to the rotation speed of the capstan motor 5a, and 41 is an F/V converter; 110
is a reference value generator that generates a voltage corresponding to the desired capstan rotation speed, and 11 is the output of the reference voltage generator 110 and F
12 is an adder that adds the output of the sample-and-hold circuit 20 and the output of the subtracter 11, and 13 drives the capstan motor 5a based on the output of the adder 12. This is a drive circuit.

In the figure, FGl, F/V converter 41° reference voltage generator 110. In the drive circuit 13, the output frequency of FGl becomes a value corresponding to the voltage generated by the reference voltage generator 110 and becomes stable, so the capstan motor 5a rotates at a substantially constant rotation. The pinch roller 6 and the capstan shaft 5b apply the rotational force of the capstan motor 5a, which rotates at a constant rotation, to the magnetic tape 1, causing the magnetic tape 1 to run at a substantially constant speed.

Regarding the tracking method in this conventional example,
This will be explained next.

In FIG. 2, 201 is a truck, 202 as 202
b is the recording position of the tracking detection signal; 203 is a vector indicating the direction of movement of the head; and 204 is a vector indicating the direction of movement of the magnetic tape 1.

Figure 8 shows 202a and 202b in Figure 7.
This is an enlarged view of one of the areas. 303 and 304 are pilot signals, and signals with the same frequency with less azimuth loss are recorded, and the same diagonal lines are recorded by heads with the same azimuth angle (in the case of the same figure, signals with two azimuth angles are recorded). recorded in ). 3
01, 302. 302a are synchronization signals for detecting signals from adjacent tracks of the pilot signal, and those with the same diagonal lines are recorded by heads with the same azimuth angle.

In the head gap 305 of the head pair 2at2b, the head width is set wider than the track width in order to reliably detect the pilot signal.

A bandpass filter 16 selects a pilot signal, and a synchronization signal detection circuit 14 detects a synchronization signal on the track. The pilot signal filtered by the bandpass filter 16 is rectified and detected by the rectifier 17. The synchronization signal detection circuit 14 can be configured with a bandpass filter and a comparator, or can be configured to digitally detect the reproduced signal frequency. For example, when the head gap passes through the position shown in FIG. 3 305, the synchronization signal 302a in that track is detected by the head gap 305. The pulse generating circuit 15 generates a pulse SPI at the moment when the head detects a synchronization signal, and generates a pulse S after a certain period of time.
P2 is pulsed twice in total. first pulse SP
I is supplied to the sample hold 18, and the second pulse 8P2 is supplied to the sample hold 20. When the SPI is generated, the head gap 305 is reproducing the pilot signal of the adjacent track on the right side in the direction of travel, and the SF
3 is generated when the head gap 305 is reproducing the pilot signal of the adjacent track on the left side in the traveling direction.

Therefore, the pilot signal amplitude voltage from the truck on the right side in the traveling direction is sampled and held in the sample hold 18. Also, in the subtracter 19, the sample hold 18
The difference between the output of the rectifier 17 and the output of the rectifier 17 is taken. When SF3 occurs, the head gap 305 is reproducing the pilot signal of the adjacent track on the left side in the traveling direction, and the sample and hold 20 samples and holds the difference in the amplitude voltage of the pilot signal from both adjacent tracks.

Since the crosstalk signal from the adjacent track is proportional to the amount of head protrusion to the corresponding track, the sample hold 20 detects the difference in the amount of head protrusion from both adjacent tracks, that is, the position of the center of the track and the center of the spacing gap. A voltage proportional to the difference is held.

In the conventional example shown in FIG.
The head 2a is detected as an output signal and added to the difference between the outputs of the F/V converter 41 and the reference voltage generator 110 via the adder 12, and is controlled to make the output signal of the sample hold 20 zero. , 2b is rotated so that the capstan motor 5a runs in the center of the track on which the tracks 2b and 2b are recorded.

Problems to be Solved by the Invention These conventional techniques require actual analog circuits such as a rectifier and a sample-and-hold circuit, and have problems such as the difficulty of eliminating the offset of the sample-and-hold circuit.

The present invention has been made in view of this point, and the rectifier is configured digitally, and the sample hold and adder/subtractor are also configured digitally, and a digital LSI or
The purpose of the present invention is to provide a magnetic recording and reproducing device that can be configured using a microprocessor and the like, thereby simplifying the hardware and improving performance.

Means for Solving the Problems In order to achieve the above objects, the magnetic recording and reproducing apparatus of the present invention comprises:
A magnetic tape is used in which a pilot signal for detecting a tracking position by crosstalk from an adjacent track and a synchronization signal for obtaining timing of detecting the pilot signal are recorded on a track formed on the magnetic tape. a synchronous signal detection circuit for detecting a synchronous signal recorded on a track on the magnetic tape from a reproduction signal of the reproduction head; a pulse generation circuit that generates a pulse twice in total: a first pulse and a second pulse after a certain period of time; a pilot conversion clock generator that generates a signal with a cycle sufficiently smaller than the signal cycle of the pilot signal; an analog-to-digital converter that converts the reproduced signal into a digital value at a signal period generated by the pilot conversion clock generator;
a peak level detector that detects and holds the maximum data of the output of the analog-digital converter; and a first storage circuit that stores the output of the peak level detector as a first pulse generated by the pulse generation circuit. and a subtracter that takes the difference between the data stored in the first storage circuit and the output data of the peak level detector, and the output of the subtracter is stored as a second pulse generated by the pulse generation circuit. a second storage circuit that generates a signal corresponding to the running speed of the magnetic tape in the drive means; a speed detector that generates a signal corresponding to the running speed of the magnetic tape in the drive means; and a period or frequency of the output signal of the speed detector that corresponds to the desired tape speed. a speed error calculator that outputs the difference between the speed error calculator and the second storage circuit; an adder that adds the outputs of the second storage circuit and the speed error calculator; and a digital-to-analog converter that converts the output of the adder into an analog voltage. and is configured to use the output of the digital-to-analog converter as a drive signal to the drive means.

According to the above-described configuration, the amplitude of the pilot signal for detecting the tracking position is digitally detected by the peak level detector, and the sample and hold at the output pulse of the pulse generation circuit is performed by the digital storage circuit. be exposed.

Example Below, regarding a magnetic recording and reproducing device according to an example of the present invention,
This will be explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, FIG. 2 is an operational waveform diagram of the embodiment of FIG. 1, and FIG. 3 is a block diagram showing an example of the structure of the period counter in FIG. 1.

In the example shown in Fig. 8, the tracking detection signal includes a pilot signal (hatched areas 303 and 304 in the figure) that detects the degree of overlap between the head and adjacent tracks from crosstalk, and a synchronization signal (hatched areas 303 and 304 in the figure) that synchronizes the detection. Figure 301
, 302, 302a (hatched areas).

In FIG. 1, 2a and 2b are a pair of heads that sequentially record and reproduce tracks, and 3 is a head 2a.

2b is a rotating cylinder attached, 1 is a magnetic tape,
16 is a bandpass filter that filters a pilot signal for tracking from the output of the heads 2a+2b;
17a is a pilot conversion clock generator that generates a pulse with a frequency about 10 times higher than the frequency of the signal extracted by the bandpass filter 16! , 17b converts the signal extracted by the bandpass filter 16 into a digital value at the time of the pulse generated by the pilot conversion clock generator.
D converter 18 is an A/D converter 17b that changes every moment.
a peak level detector for detecting the maximum data of the output of 1;
4 is a synchronization signal detection circuit that detects a synchronization signal for detecting a pilot signal from the output of the head 2 al 2 b, and 15 is a pulse SPI immediately after the synchronization signal detection circuit 14 detects the synchronization signal, and a pulse SP2 after a certain period of time. 19 is a memory circuit that stores the output of the peak level detector 18 at the timing of the pulse SP1 output by the pulse generator 15; 20 is the output of the memory circuit 19 and the peak level detector; 18 is a subtracter that takes the difference between the output signals; 21 is a storage circuit 9a that stores the output of the subtracter 20 at the timing of the pulse SP2 output from the pulse generating circuit 15;

9b is a reel 8a around which the magnetic tape 1 is wound.

8b is a post forming a running path for the magnetic tape 1; 5a;
, 5b is a capstan motor and a capstan shaft for running the magnetic tape 1, 6 is a pinch roller,
7 is a period counter that outputs a signal with a frequency proportional to the rotational speed of the capstan motor 5a; FG14 is a period counter that counts the period of the output signal of FG7 and outputs it as a digital value; 10 corresponds to the desired capstan rotational speed. A reference value generator generates digital data; 11 is a subtracter that takes the difference between the output data of the reference value generator 10 and the output data of the period counter 4; 12 is a subtracter that adds the output data of the storage circuit 21 and the subtracter 11; an adder; 22 is a D/A converter that converts the output data of the adder 12 into an analog voltage; 13 is a D/A converter 2;
This is a drive circuit that drives the capstan motor 5a based on the output of No. 3.

In FIG. 1, FG7 operates as a speed detector for magnetic tape 1, and period counter 4. Reference value generator 10.
The subtracter 11 constitutes a speed error calculator. Also,
Drive circuit 13. The capstan motor 5 al, the capstan shaft 5b, and the pinch roller 6 operate as driving means for the magnetic tape 1.

Next, the operation of this embodiment will be explained.

In FIG. 1, FG7. Period counter4. Reference value generator 10. D/A converter 22. The feedback loop consisting of the drive circuit 13 operates so that the output frequency of the FG 7 becomes a value corresponding to the data generated by the reference value generator 10 and becomes stable. Therefore, the capstan motor 5a rotates at a substantially constant rotation, and the pinch roller 6 and the capstan shaft 5
b applies the rotational force of the capstan motor 5a, which rotates at a constant rotation, to the magnetic tape 1, causing the magnetic tape 1 to run at a substantially constant speed.

FIG. 3 shows an example of the structure of the period counter 4. As shown in FIG.

401 is a limiter that shapes the output of FG7 into a rectangular wave;
02 is a delay circuit, 403 is a clock generator 1404 is a counter that counts the output of the clock generator 40B, 405
is a latch circuit. At the rising edge of FG7, the latch 405 latches the count data of the counter 404. Further, the counter 404 is cleared immediately after the data is latched into the latch 405 via the delay circuit 402. Therefore, the number of clock pulses generated by the clock generator 403 during the period of the output signal of FG7 is held in the latch 406. As described above, the period counter 4 is F
The output signal period of G7 is counted and output as a digital value.

In FIG. 7, 201 is a truck, 202a1202
b is the recording position of the tracking detection signal; 203 is a vector indicating the direction of movement of the head; and 204 is a vector indicating the direction of movement of the magnetic tape 1.

FIG. 8 shows an enlarged view of one of the areas 202a and 202b in FIG. 303 and 304 are pilot signals, and signals with the same frequency with less azimuth loss are recorded, and the same diagonal lines are recorded by heads with the same azimuth angle (in the case of the same figure, signals with two azimuth angles are recorded). recorded in ). 301.
302. 302a is a synchronization signal for detecting a signal from a track adjacent to the pilot signal, and those with the same diagonal lines are recorded by heads having the same azimuth angle.

Furthermore, the example shown in the figure shows an example in which the recording length of the synchronization signal is different so that it can be distinguished from adjacent tracks on which azimuthal recording is performed.

The tracking detection signal consists of the above pilot signal and synchronization signal. 305 indicates a head gap, and 306 indicates a moving direction of the helad gap 305.

The head gap 305 of the head pair 2a, 2b is set so that the head width is wider than the track width in order to reliably detect the pilot signal.

In FIG. 1, a bandpass filter 16 selectively filters a pilot signal, and a synchronization signal detection circuit 14 detects a synchronization signal on a track. Further, the pilot conversion clock generator 17a generates a pulse having a frequency about 10 times higher than the frequency of the pilot signal selectively filtered by the bandpass filter 16. The pilot signal selectively filtered by the bandpass filter 16 is converted into a digital value by the A/D converter 17b in synchronization with the pulses generated by the pilot conversion clock generator 17a. The number of times the data is converted into a digital value is approximately 10 times per period of the pilot signal, and the maximum value of these data is detected by the peak level detector 18.

Therefore, the maximum value envelope of the pilot signal is detected by the peak level detector 18.

If this peak level detector is reset at an appropriate time, the maximum value after reset can be detected.

FIG. 2(a) shows the synchronization signal detected, FIG. 2(b) shows the pilot signal, and FIG. 2(C) shows the amplitude signal data of the pilot signal detected by the peak level detector 18. It is shown after converting it to an analog value.

The synchronization signal detection circuit can be configured with a bandpass filter and a comparator, or can be configured to digitally detect the reproduced signal frequency. FIG. 2(a) shows a waveform in the case of extraction using a bandpass filter. The pulse generating circuit 15 generates pulse SP1 at the moment when the head detects the synchronization signal, and generates pulse SP2 after a certain period of time.
, a total of two pulses are generated. These two pulses are shown as (d) and (e), respectively, in FIG.

Output data of peak level detector 18 (Figure 2 (C))
is the pulse 5P1 (second
(d)) is stored in the storage circuit 19. The subtracter 20 subtracts the output data of the peak level detector 18 from the output data of the storage circuit 19 and outputs it. The memory circuit 21 stores the output data of the subtracter 20 using the pulse SP2 (FIG. 2(e)) output from the pulse generating circuit 15.

In FIG. 8, when the head gap 305 advances as shown in the figure, when the synchronization signal detection circuit detects the synchronization signal, that is, when SPl is generated, the head gap 305 is the pilot of the adjacent track on the right side in the direction of travel. The crosstalk portion of the signal is regenerated, and SF3 generated after a certain period of time is generated at the time when the Herad gap 305 is reproducing the crosstalk portion of the pilot signal of the adjacent track on the left side in the direction of travel. .

Therefore, data corresponding to the pilot signal amplitude voltage from the right track in the traveling direction is stored in the storage circuit 19. Also, when SF3 occurs, head gap 3
05 is reproducing the pilot signal of the adjacent track on the left side in the direction of travel, and when SF3 occurs, the subtracter 2
The output of 0 is data corresponding to the difference in amplitude voltage of the pilot signal signals from both adjacent tracks reproduced by the head. Therefore, data corresponding to the difference in amplitude voltage of pilot signals from both adjacent tracks reproduced by the head is stored in the storage circuit 21.

Since the crosstalk signal from the adjacent track is proportional to the amount of head protrusion to the corresponding track, the storage circuit 21 detects the difference in the amount of protrusion of the head to both adjacent tracks, that is, the difference between the positions of the track center and the center of the spacing gap. Data proportional to is held.

F G 7. Period counter4. Reference value generator 10. D
/A converter 22. The feedback loop consisting of the drive circuit 13 operates so that the output frequency of the FG 7 becomes stable at a value corresponding to the data generated by the reference value generator 10, and the capstan motor 5a rotates at an almost constant rotation. , the pinch roller 6 and the capstan shaft 5b transfer the rotational force of the capstan motor 5a, which rotates at a constant rotation, to the magnetic tape 1.
In addition, the magnetic tape 1 is run at a substantially constant speed.

The output of the memory circuit 21, which is the relative position between the running position of the head 2 al 2 b and the recorded track, is sent to a period counter 4. The control system is configured so that the difference of the reference value generator 1o is added to the output of the subtracter 11, and the output data of the storage circuit 21 is made zero.

Therefore, the rotation of the capstan motor 5a is controlled so that the output data of the storage circuit 21, which is data proportional to the difference between the positions of the track center and the head gap center, becomes zero, and the heads 2a and 2b move toward the recorded track. Run in the center of the top.

In the above description, the pilot conversion clock generator 17
a, A/D converter 17b, peak level detector 18. Memory circuits 19, 21. Subtractor 20° period counter 4.
Reference value generator 10. Adder 12゜D/A converter 23 is 1
It can be configured as one IC, and can also be configured as a microcomputer. Especially period counter 4. The peak level detector 18° can also be configured using microcomputer software. By constructing these circuits on one LSI and processing them digitally,
Circuit simplification is achieved.

Furthermore, since all signals are processed digitally, there are no offsets that occur in analog circuits, making it extremely easy to design the device.

Next, configuration examples in other embodiments of the present invention will be described. FIG. 4 is a block diagram showing an example of the configuration of the peak level detector 18 in the second embodiment of the present invention. In the figure, the configuration other than the peak level detector 18 is completely the same as the embodiment of FIG. 1, and is not shown.

In FIG. 4, 1801 is a memory that stores digital data, and 1802 is a comparator that compares the magnitude relationship between the output of the memory 1801 and the output of the A/D converter 17b.
The peak level detector 18 includes a memory 1801 and a comparator 18
Consists of 02.

The operation of the peak level detector having such a configuration will be briefly explained.

The output of the A/D converter 17b, which changes with each conversion operation of the A/D converter 17b that occurs in synchronization with the pulse generated by the pilot conversion clock generator shown in FIG. In 1802, the magnitude relationship is compared. Comparator 1802 outputs a pulse when the output of A/D converter 17b is greater than the output of memory 1801.

When the comparator 1802 outputs a pulse, the memory 180
1 stores output data of the A/D converter 17b.

Therefore, memory 1801 stores and outputs the maximum value of the output of A/D converter 17b. The output of this memory 1801 becomes the output of the peak level detector 18.

By using the peak level detector 18 shown in FIG. 4, the same operation as the embodiment shown in FIG. 1 can be realized and the same effects can be obtained.

Next, a configuration example of still another embodiment of the present invention will be described. FIG. 5 is a block diagram showing an example of the configuration of the peak level detector 18 in the third embodiment of the present invention. In the figure, a peak level detector 18
The other configurations are completely the same as the embodiment shown in FIG. 1, and are not illustrated.

In FIG. 5, 1803 is a memory that can be cleared and stores digital data using an external manual pulse;
1804 compares the output data of the memory 1803 and the A/D converter 17b, and compares the output data of the memory 1803 with the A/D converter 17b.
A comparator that outputs a pulse when the output data of the D converter 17b becomes large. 1805 is a timer that is reset when the comparator 1804 outputs a pulse and outputs a pulse after a certain period of time. 1807 is the output of the timer 1806. Memory 1 for storing output data of the memory 1803 in pulses
80B is a delay circuit that delays the output pulse of the timer 1805 to generate a signal for clearing the memory 1803, and the peak level detector 18 is connected to the memory 1803.18.
07, comparator 1804, timer 1805, delay circuit 18
06, and the output of the memory 1807 becomes the output of the peak level detection circuit.

The operation of the peak level detector having such a configuration will be briefly explained.

The output of the A/D converter 17b, which changes with each conversion operation of the A/D converter 17b that occurs in synchronization with the pulse generated by the pilot conversion clock generator shown in FIG. In 1804, the magnitude relationship is compared. Comparator 1804 outputs a pulse when the output of A/D converter 17b is greater than the output of memory 1803.

When the comparator 1804 outputs a pulse, the memory 180
3 stores output data of the A/D converter 17b.

Also, the output of the comparator 1804 is input to the timer 1805, and the timer 1805 is reset to stop counting the time.
Start with The timer 1805 is set to count the time corresponding to 1/2 cycle of the pilot signal input to the A/D converter 17b. If A/D converter 1
If the signal input to 7b is increasing, the output of A/D converter 17b changes to be larger than the output data of memory 1803, so a reset pulse is applied from the comparator before timer 1805 finishes counting. timer 18
05 does not output an output pulse. On the other hand, A/D converter 17
When the signal input to b starts to decrease, A/D converter 1
Since the output of 7b changes to be smaller than the output data of memory 1803, comparator 1804 no longer outputs a pulse. Therefore, the timer 1805 counts until the end of the count, and outputs a pulse 172 cycles after the memory 1803 stores the maximum data of the pilot signal. The memory 1807 uses this pulse output to store the memory IJ.
The maximum value stored in 1803 is stored. Further, the output pulse of the timer 1805 is delayed by a delay circuit 1806, and the memory 1803 is cleared to O. The memory 1807 holds that value until the next peak level of the pilot signal arrives, and the peak level detection circuit 18 repeats the above operation.

Therefore, the memory 1807 holds and outputs the peak level in each cycle of the pilot signal input to the A/D converter 17b.

Therefore, memory 1807 stores and outputs the maximum value of the output of A/D converter 17b. The output of this memory 1807 becomes the output of the peak level detector 18.

By using the peak level detector 18 shown in FIG. 5, an operation similar to the embodiment shown in FIG. 1 is realized.

Furthermore, in the above description, all the components shown in FIG. 5 can be configured as digital IC circuits, and furthermore, can be configured as microcomputer software. By configuring these circuits on one LSI and processing them digitally, the circuits can be simplified.

Furthermore, since all signals are processed digitally, there are no offsets that occur in analog circuits, making it extremely easy to design the device.

Effects of the Invention As described above, according to the present invention, the pilot signal is directly
The digital IC circuit captures the digital value with a /D converter, detects the peak level of the pilot signal from the adjacent track, performs sample and hold in a digital storage circuit, and calculates the amount of tracking error as a digital value. By implementing this internally, the sample-and-hold circuit required in conventional technology is not needed, simplifying the circuit, and eliminating problems such as offset that occur in analog circuits such as sample-and-hold circuits. This can produce great practical effects, such as making it possible to solve the problem.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the magnetic recording/reproducing device of the present invention, FIG. 2 is an operational waveform diagram of the embodiment of FIG. 1, and FIG. 3 is a block diagram of a period counter used in the present invention. , FIG. 4 is a block diagram of the second embodiment of the present invention, FIG. 5 is a block diagram of the third embodiment of the present invention, and FIG. 6 is a block diagram of the conventional example. 1...Magnetic tape; 2a, 2b... Playback head, 3... Rotating cylinder, 5a, 5b, 6
．． 13... Drive means, 14... Synchronization signal detection circuit, 15... Pulse generation circuit, 17a...
Pilot conversion clock generator, 17b... Analog-digital converter, 18... Peak level detector, 19... First storage circuit, 20...
・Subtractor, 21...second memory circuit, 7.
...Speed detector, 4. 10. 11... Speed error calculator, 12... Adder, 23... Digital-to-analog converter.

Claims (3)

[Claims] (1) Reproducing a magnetic tape recorded on a track in which a pilot signal for detecting a tracking position by crosstalk from an adjacent track and a synchronization signal for obtaining timing of detecting the pilot signal are formed on the magnetic tape. The apparatus comprises: a drive means for running the magnetic tape; a synchronization signal detection circuit for detecting a synchronization signal recorded on a track on the magnetic tape from a reproduction signal of the reproduction head; a pulse generation circuit that generates a pulse twice in total, a first pulse when a synchronization signal is detected and a second pulse after a certain period of time; and a pilot conversion clock that generates a signal with a cycle sufficiently smaller than the signal cycle of the pilot signal. a generator; an analog-to-digital converter that converts the reproduced signal of the pilot signal into a digital value at a signal period generated by the pilot conversion clock generator; and detecting and holding maximum data of the output of the analog-to-digital converter. a first storage circuit that stores the output of the peak level detector as a first pulse generated by the pulse generation circuit; and a first storage circuit that stores the output of the peak level detector as a first pulse generated by the pulse generation circuit; a subtracter that takes the difference from the output data of the peak level detector; a second storage circuit that stores the output of the subtracter as a second pulse generated by the pulse generation circuit; and the magnetic tape in the drive means. a speed detector that generates a signal corresponding to the running speed of the tape; and a speed error calculator that outputs a difference between the period or frequency of the output signal of the speed detector and a value corresponding to the desired tape speed; an adder that adds the output of the speed error calculator and the output of the speed error calculator; and a digital-to-analog converter that converts the output of the adder to an analog voltage; A magnetic tape reproducing device characterized in that it is configured to send a drive signal to a drive means. (2) The peak level detector includes: a first memory that stores data converted into digital values in the analog-to-digital converter at a signal period generated by the pilot conversion clock generator; Compare the output data of the analog-to-digital converter with the output data of the analog-to-digital converter, and output a signal to store the output data of the analog-to-digital converter in the first memory only when the output value of the analog-to-digital converter is large. 2. The magnetic tape reproducing apparatus according to claim 1, further comprising: a comparator that performs the following steps. (3) The peak level detector includes: a second memory that stores data converted into digital values in the analog-to-digital converter at a signal period generated by the pilot conversion clock generator; Compare the data with the output data of the analog-to-digital converter, and output a signal to store the output data of the analog-to-digital converter in the second memory only when the output value of the analog-to-digital converter is large. a timer circuit that is reset by the first comparator and outputs a pulse after a certain period of time after the reset; and a third timer circuit that stores the output data of the second memory based on the output of the timer circuit.
2. The magnetic tape reproducing apparatus according to claim 1, further comprising: a memory, and a delay circuit that generates a pulse that clears the second memory after a predetermined period of time after the pulse output from the timer circuit.