JPH0320941B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pseudo-reference burst generator for testing time division multiple access equipment for satellite communications. In particular, the present invention relates to a pseudo-reference burst generator that enables efficient and economical testing and maintenance of a single time division multiple access device.

In the time division multiple access (hereinafter referred to as TDMA) communication system, each slave station sends out a burst-like signal at a specified timing based on a TDMA frame determined by a reference synchronization burst sent out by a reference station, and the bursts overlap with each other. This is a method to control communication so that it does not occur.

[Conventional technology]

In the operation of TDMA communication equipment, it is necessary to periodically confirm that there is no deterioration of the transmit signal system and the receive signal system. Conventionally, this test uses a pseudo reference station device that generates a signal with the same shape as the reference burst. was. This pseudo reference station device uses a synchronization signal (REF UW, Reference Unique) that indicates the reference station.
A reference burst including a word) is sent out at TDMA frame intervals, and the contents of a read-only memory (ROM, Read Only Memoy) in which several types of control codes, such as acquisition permission and transmission stop, are written, are selected using a switch and sent out. It was something to do.

[Problem that the invention seeks to solve]

However, recently, TDMA communication systems consist of a small number of base stations (usually 1 to 3) and a large number of slave stations, so even if the base station equipment becomes slightly complex, if the slave station equipment can be simplified, TDMA communication Taking advantage of the feature that improves the overall economic efficiency of the system, switching between working and standby stations and transmission synchronization control for each slave station is now performed by individually selecting the slave stations to be controlled using the control channel set in the reference burst. It's here.

For this reason, with conventional pseudo reference station devices that only have the function of selecting and transmitting a control code prepared in advance using a switch, a problem has arisen in that only a small portion of the operation of the slave station device can be tested.

FIG. 8 is a block diagram of a conventional test method for a time division multiple access device. For the above problem,
As shown in FIG. 8, the transmitting signal system of the station performing maintenance work is separated from the antenna 50, and only the receiving signal system is connected to the antenna 50, and the transmitting signal of the own station is combined with this received signal to generate the TDMA device 35. A method can be adopted in which the reference station actually controls this station by supplying it to the reception signal system and confirms its operation.

However, with this method, the work must be done in collaboration with the reference station, which increases the number of workers and requires multiple slave stations to work in parallel.If a failure occurs in a slave station, it is difficult to carry out tests to determine the cause of the problem. Therefore, there are problems that affect the maintenance work of other slave stations.

In addition, if the slave station equipment has a working backup configuration, in order to test only the backup equipment, it is necessary to use a test control code to distinguish between the working equipment, so it is not necessary to use the There is a problem in that the operation cannot be completely guaranteed with respect to the control signal.

When tests are conducted via satellite in this way, it is necessary to station workers at both the pseudo reference station and the slave station, and there is also a problem in that the pseudo reference station equipment cannot be rewritten internally.

The present invention solves the above-mentioned problems, and allows tests to be performed only by the slave station without using a satellite, and allows for easy rewriting using a write control circuit, selection circuit, memory circuit, etc. for various tests. An object of the present invention is to provide a pseudo-reference burst generator capable of performing the following steps.

[Means for solving problems]

A first invention includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. In the pseudo-reference burst generation device, the reference burst generation circuit includes means for independently synchronizing and generating a frame pulse signal corresponding to a time division multiple access frame period, and a burst gate having a reference burst length by means of the frame pulse signal. a reference burst synthesis means for outputting a signal to the modulation circuit and outputting a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel portion, and a symbol address signal for the control channel portion; A plurality of storage means for storing partial patterns, a write control means for changing the contents of the storage means, and an integral multiple of the time division multiple access frame period (provided that it is 1 or more) by the frame pulse signal. ), the control channel gate signal and the symbol address signal are applied to the read address input of one of the plurality of storage means, and the other storage means is supplied with the control channel gate signal and the symbol address signal. selection means for selecting the one storage means and the other storage means in accordance with the synchronization signal so as to connect the write input and write address of the means to the write control means; The present invention is characterized in that it includes means for inhibiting output transmission of the means and outputting a logical sum of the output of the one storage means, the carrier timing recovery code, and the unique word to the modulation circuit.

A second invention includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. A pseudo reference burst generator comprising: means for generating a frame pulse signal corresponding to a time division multiple access frame period in independent synchronization for the reference burst generation; and a frequency dividing means for dividing the frequency of the frame pulse signal. Based on the frame pulse signal, a burst gate signal having a reference burst length is output to the modulation circuit, and a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel portion, and a symbol address signal for the control channel portion are output. , a plurality of storage means for storing patterns and transmission orders of the control channel portions, a write control means for changing the contents of the storage means, and an output signal of the frequency division means. , a synchronization signal generation means for outputting a synchronization signal synchronized with a cycle that is an integral multiple (but not less than 1) of the time division multiple access frame cycle; The control channel gate signal and the symbol address signal are applied to the read address input of one of the storage means, and the synchronization signal is connected to the write input and write address of the other storage means to the write control means. Therefore, a selection means for selecting the one storage means and the other storage means, a control means for controlling the output of the one storage means based on the output signal of the frequency division means, and the other storage means further comprising means for inhibiting output transmission of the one storage means and outputting the logical sum of the output of the one storage means controlled by the control means and the carrier timing recovery code and the unique word to the modulation circuit. do.

[Effect]

The present invention generates a frame pulse signal corresponding to a TDMA frame period with a frame counter,
Based on this frame pulse signal, a burst gate signal having a reference burst length is applied to a modulation circuit by a reference burst synthesizing means. This frame counter is independent of the control of other stations, is asynchronous with the synchronization of other stations, and is used only during testing. A synchronization signal synchronized with a period that is an integral number (1 or more) times the TDMA frame period from the synchronization signal generation means is used to select one of the plurality of storage means for storing the pattern of the control channel portion by switching with the selection means. , inputs the control channel gate signal and symbol address signal from the reference burst synthesis means, and outputs the logical sum of the output of this one storage means and the carrier timing recovery code and unique word from the reference burst synthesis means to the modulation circuit. . Further, the selection means connects another storage means to the write control means so that the contents can be changed. As described above, a desired control signal can be sent to the slave station device without control from the reference station, and all functions of the slave station device can be confirmed.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a pseudo-reference burst generator according to an embodiment of the present invention. In Figure 1,
A system clock signal 10 from a system clock oscillator 1, which is an oscillator with a frequency at the symbol rate.
1 is connected to the clock input CLK of the frame counter 2, reference burst synthesis circuit 3, and modulation circuit 32. A frame pulse signal 102 corresponding to the TDMA frame period is obtained by frequency-dividing the system clock signal 101 from the output TC of the frame counter 2.
is connected to the frame pulse input of the reference burst synthesis circuit 3. A burst gate signal 103 corresponding to the reference burst length is sent from the reference burst synthesis circuit 3.
is connected to the modulation circuit 32. Further, a control channel gate signal 105 indicating the control channel portion and a symbol address signal 106 of the control channel portion from the reference burst synthesis circuit 3 are respectively connected to the input A of the selection circuit 4. The output X of the selection circuit 4 is connected to the input of the memory circuit 5, and the output Y is connected to the input of the memory circuit 6. The output of the write control circuit 7 is connected to the input B of the selection circuit 4. The outputs of memory circuits 5 and 6 are connected to one input of AND gates 8 and 9. One terminal of the changeover switch 12 is grounded, and the other terminal is connected to the flip-flop 13.
is connected to the input C of the resistor and one terminal of the resistor. The input D of flip-flop 13 is connected to the output, and the output is connected to the input D of flip-flop 14. A frame pulse signal 102 is branched from the output TC of the frame counter 2 and connected to the input C of the flip-flop 14. An output signal 108 from the output Q of the flip-flop 14 is input to the input SEL of the selection circuit 4, the other input of the AND gate 9, and the inverter 10, and the output of the inverter 10 is connected to the other input of the AND gate 8. A data signal 104 corresponding to a carrier timing recovery code and a unique word is sent from the reference burst synthesis circuit 3 and a control channel data signal 107 is sent from the AND gate 8 or 9 to the OR gate 1, respectively.
1 input.

Here, the output signal 10 of the flip-flop 14 is
When 8 is "0", the selection circuit 4 connects input A and output X, and connects input B and output Y.
Therefore, the reference burst synthesis circuit 3 is added to the storage circuit 5.
Control channel gate signal 105 and symbol address signal 106 indicating the control channel portion from
is connected, and the pattern written in the memory circuit 5 is connected to the input of the OR gate via the AND gate 8 as a control channel data signal 107.
The memory circuit 6 is connected to the write control circuit 7 and its contents can be rewritten. When the output signal 108 is "1", the selection circuit 4 connects the input A and the output Y, and connects the input B and the output X. Therefore, storage circuit 5 and storage circuit 6 are switched. The transmission data signal 109 is transmitted from the OR gate 11 to the modulation circuit 3
2 and receives the reference burst from the modulation circuit 32.
The RB is connected to a time division multiple access device (not shown).

The operation of the pseudo reference burst generator having such a configuration will be explained.

FIG. 2 is a block diagram of a test method using the pseudo-reference burst generator of the present invention. In FIG. 2, 31 is a pseudo reference burst pattern generation circuit, 32 is a modulation circuit, 33 is a pseudo reference burst generator, 34 is a hybrid circuit, and 35 is a pseudo reference burst pattern generation circuit.
In the TDMA device, 36 is a demodulation circuit, 37 is a reception logic circuit, 38 is a control circuit, 39 is a transmission logic circuit, and 40 is a modulation circuit.

FIG. 3 shows the structure of a TDMA frame when a test is performed using the test method shown in FIG. In FIG. 3, RB indicates a reference burst and LB indicates a slave burst.

FIG. 4 is a configuration diagram of the reference burst RB shown in FIG. 3. In FIG. 2, a pseudo reference burst generator 33 generates a reference burst RB shown in FIG. 3, and a TDMA device 35 synchronized with this on the receiving side controls the reference burst RB shown in FIG. Decodes the contents of channel CS and transmits slave burst LB. For example, when synchronizing transmission using this method, the TDMA device 35 receives the reference burst RB shown in FIG. 4, regenerates the carrier wave and reception clock using the carrier timing recovery code CT shown in FIG. The unique word UW shown in FIG. 4 is detected, and the control channel CS is decoded using this detection timing as a reference for the received frame. The pseudo-reference burst generator 33 sends transmission permission to the control channel CS and a delay amount D that defines the difference between the transmitted frame and the received frame, so that the TDMA device 35 is positioned D symbols behind the beginning of the received frame. The beginning of the transmission frame is defined, and the slave burst LB is sent out at a timing delayed by the number of symbols specified by the line pattern. In the test method shown in Fig. 2, the value of the delay amount D is D = N frame length - D', where D' is the signal delay time from transmission to reception of the TDMA device 35, and the slave burst LB depends on the line pattern. It will be sent to a predetermined location. However, N is 1
Must be an integer greater than or equal to

FIG. 5 is a time chart of signals of the pseudo reference burst generator of the present invention. In Figure 5,
Numbers that are the same as those shown in FIG. 1 indicate the same signals.

In FIG. 1, a system clock oscillator 1 is a symbol rate oscillator and distributes a system clock signal 101 to a frame counter 2, a reference burst synthesis circuit 3, and a modulation circuit 32.

Frame counter 2 divides the frequency of system clock signal 101 to generate frame pulse signal 102 corresponding to the TDMA frame period.

Using this frame pulse signal 102 as a trigger, the reference burst synthesis circuit 3 generates a burst gate signal 103 corresponding to the reference burst length, a carrier timing recovery code CT, and a unique word UW.
A data signal 104 corresponding to , a control channel gate signal 105 indicating a control channel portion, and a symbol address signal 106 for this portion are output.

When the input SEL is "0", the selection circuit 4 connects the input A signal to the output X, and connects the input B signal to the output Y. Further, when the input SEL is "1", the signal of the input A is connected to the output Y, and the signal of the input B is connected to the output X.

Therefore, when the output signal 108 of the flip-flop 14 is "0", the control channel gate signal 105 and symbol address signal 106 indicating the control channel portion output by the reference burst synthesis circuit 3 are supplied to the storage circuit 5. The pattern written in memory circuit 5 is outputted as control channel data signal 107 through AND gate 8. Control channel data signal 107 and carrier timing recovery code CT and unique word
Data signal 104 corresponding to UW is OR gate 1
1 and supplied to the modulation circuit 32 as a transmission data signal 109.

The modulation circuit 32 performs modulation corresponding to the transmission data signal 109 only during the period when the burst gate signal 103 is "1" and outputs the reference burst RB.

The memory circuit 6 is connected to the write control circuit 7 and its contents can be rewritten when the output signal 108 of the flip-flop 14 is "0".

Therefore, when the next control code to be output is written through the write control circuit 7 and the changeover switch 12 is momentarily turned on, this pulse is input to the flip-flop 13 as a clock signal, and the output of the flip-flop 13 is inverted. This signal is retimed with the frame pulse signal 102 and supplied as a selection signal to the memory circuits 5 and 6.

As described above, by switching the memory circuits 5 and 6 in synchronization with the frame timing, the memory circuits 5 and 6 are not switched while the reference burst is being transmitted, so that meaningless control codes are not transmitted. You can prevent this from happening.

In order to avoid the influence of errors in the transmission path, the control channel CS may be transmitted at a cycle that is an integral multiple of a frame, such as when it is repeatedly transmitted. In this case, in order to define the timing multiplied by this integer (1 or more), a circuit is added to divide the frame pulse signal 102, and the output of this frequency dividing circuit is input to the clock input of the flip-flop 14 and to the selection circuit 4. It is sufficient to supply the memory circuit 5 and the memory circuit 6 through the memory circuit 5 and the memory circuit 6. 3 memory circuits
If there are more than one set, the number of bits of the output signal 108 of the flip-flop 14, which is the memory circuit selection signal, may be increased.

FIG. 6 is a block diagram of a pseudo-reference burst generator according to another embodiment of the present invention. In FIG. 6, the same numbers as those shown in FIG. 1 indicate the same circuits and signals. 20 is input by the change point detection circuit
A short “1” when the signal applied to IN changes from “0” to “1” or from “1” to “0”
Outputs the pulse to the output OUT. 21 is a frequency dividing circuit that divides the frequency of the frame pulse signal 102;
22 is a frequency dividing circuit that further divides the frequency of this frequency-divided pulse.

In the case of the embodiment shown in FIG. 6, the pattern to be transmitted to the control channel, the number of times this pattern is to be repeatedly transmitted, and a repetition control code are written in the memory circuit 5 and the memory circuit 6.

FIG. 7 is a diagram showing the contents of the memory circuit.
In FIG. 7, reference numeral 301 denotes a control channel pulse, which constitutes one word with N bits. The N-bit control channel pulse may be sent out in one frame or in an integral number (2 or more) times one frame. 302 is a repetition control code, and 303 is the number of repetitions. In this case, the contents of the memory circuit constitute one block of N+1 words as shown in FIG. Repeat control code 30
When 2 is "00", it indicates that the control channel pulse 301 is a control channel pattern, and when it is "01", the N-bit control channel pattern following this word is repeatedly sent out the number of times specified in the repetition number 303. After that, move on to processing the next block,
When the value is ``10'', processing of the first block is started after completing the processing of that block, and when it is ``11'', the processing of that block is defined to continue until it is reset.

In this way, the repeat control code 302 writes "01", "10" or "11" at the beginning of the N+1 word,
The processing of this block is defined, and a control channel pattern to be transmitted is written in the control channel pattern 301 with the following N-word repetition control code 302 set to "00". To repeatedly send out the same control channel pattern, the repeat count 303 is set in the frequency divider circuit 22 by the repeat count set signal shown in FIG. When the content becomes "0" after each subtraction, the block transfer signal 124 shown in FIG. 6 is used to notify the storage circuit 5 or 6, and the process moves on to the next block.

The above explanation assumes that only one reference burst is sent out, but a pulse separated by an appropriate amount of time is output from the frame counter, and this pulse drives the reference burst synthesis circuit to send out multiple reference bursts. It can also be implemented in such a way that it occurs.

Further, the memory circuit can be equivalently implemented as a plurality of memory circuits by using only one piece of hardware and assigning different addresses.

The present invention allows the device to be miniaturized by applying a microprocessor.

〔Effect of the invention〕

As described above, in the present invention, by connecting the reference burst generator of the present invention to a slave station, it is possible to independently test a pseudo reference station without using a satellite.

Therefore, there is no need to place test workers at both the pseudo reference station and the slave station, and it is possible to increase the number of test items. Therefore, it has a very large effect on improving the reliability of TDMA satellite communications. Furthermore, since the equipment to be tested can be tested completely separated from the satellite system, the current communication system will not be affected by erroneous operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pseudo-reference burst generator according to an embodiment of the present invention. FIG. 2 is a block diagram of a test method using the pseudo-reference burst generator of the present invention. FIG. 3 is a diagram showing the configuration of the time division multiple access frame. FIG. 4 is a configuration diagram of the reference burst. FIG. 5 is a time chart of each signal of the pseudo reference burst generator of the present invention. FIG. 6 is a block diagram of a pseudo-reference burst generator according to another embodiment of the present invention.
FIG. 7 is a diagram showing the contents of the memory circuit. FIG. 8 is a block diagram of a conventional test method for a time division multiple access device. 1...System clock oscillator, 2...Frame counter, 3...Reference burst synthesis circuit, 4...
...Selection circuit, 5, 6... Memory circuit, 7... Write control circuit, 8, 8', 9, 9'... AND gate, 1
0...Inverter, 11...Or gate, 12...
...Changing switch, 13, 14...D type flip-flop, 20...Changing point detection circuit, 21,
22... Frequency divider circuit, 31... Pseudo reference burst pattern generation circuit, 32... Modulation circuit, 33... Pseudo reference burst generator, 34... Hybrid circuit, 35... TDMA device, 36... Demodulation circuit ,
37... Reception logic circuit, 38... Control circuit, 39
...Transmission logic circuit, 40...Modulation circuit, 50...
Antenna, 101...System clock signal, 1
02...Frame pulse signal, 103...Burst gate signal, 104...Data signal corresponding to carrier timing recovery code and unique word,
105... Control channel gate signal indicating the control channel part, 106... Symbol address signal of the control channel part, 107... Control channel data signal, 108... Output signal of flip-flop 14, 109... Transmission data signal, 120... ... Change point detection signal, 121, 122 ... Frequency division signal, 1
23...Repetition count set signal, 124...Block transition signal, CS...Control channel, CT...Carrier timing recovery code, LB...Slave station burst,
RB...Reference burst, UW...Unique word.

Claims (1)

[Claims] 1. Includes a reference burst generation circuit 31 that generates a reference burst, and a modulation circuit 32 that modulates and outputs the reference burst, and transmits the output signal of the modulation circuit to a time division multiple access device as a test signal. In the pseudo reference burst generation device, the reference burst generation circuit 31 is provided with means 1 and 2 for independently synchronizing and generating a frame pulse signal corresponding to a time division multiple access frame period.
and outputs a burst gate signal of a reference burst length to the modulation circuit according to the frame pulse signal, and outputs a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel part, and a symbol address of the control channel part. a reference burst synthesis means 3 for outputting a signal; a plurality of storage means 5, 6 for storing patterns of the control channel portion; and a write control means 7 for changing the contents of the storage means.
and synchronization signal generating means 12, 13, 14 for outputting a synchronization signal 108 synchronized with a cycle that is an integral multiple (but not less than 1) of the time division multiple access frame cycle using the frame pulse signal; applying the control channel gate signal and the symbol address signal to one of the plurality of storage means in accordance with a synchronization signal;
selection means 4 for selecting the one storage means and the other storage means in accordance with the synchronization signal so as to connect the write input and write address of the other storage means to the write control means; Means 8 to 11 for inhibiting output transmission of the other storage means and outputting the logical sum 109 of the output of the one storage means, the carrier timing recovery code, and the unique word to the modulation circuit.
A pseudo-reference burst generator comprising: and . 2. A pseudo-standard that includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs this reference burst, and that is equipped with means for supplying the output signal of the modulation circuit as a test signal to a time division multiple access device. In the burst generation device, the reference burst generation circuit includes means for independently synchronizing and generating a frame pulse signal corresponding to a time division multiple access frame period, frequency dividing means for dividing the frequency of the frame pulse signal, and the frame pulse signal. A standard for outputting a burst gate signal having a reference burst length to the modulation circuit, and outputting a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel portion, and a symbol address signal for the control channel portion. burst synthesis means; a plurality of storage means for storing patterns and transmission orders of the control channel portions; write control means for changing the contents of the storage means; synchronization signal generation means for outputting a synchronization signal synchronized with a cycle that is an integral multiple of the multiple access frame cycle (provided that it is 1 or more); said one storage means and said other storage means in accordance with said synchronization signal so as to provide said control channel gate signal and said symbol address signal and connect the write input and write address of said other storage means to said write control means. a selection means for selecting one of the storage means; a control means for controlling the output of the one storage means according to the output signal of the frequency dividing means; A pseudo-reference burst generation device comprising means for outputting a logical sum of the controlled output of the one storage means, the carrier timing recovery code and the unique word to the modulation circuit.