JPH03208368A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid the erroneous operation and the decrease in operation rate by a method wherein a resistance element is laid between a gate of NMOS transistor and a high tension power supply likewise a capacitor element is laid between said gate and a low tension power supply to make an inner step- down circuit. CONSTITUTION:The tension of an outer power supply Vcc (a) is lowered by an inner tension lowering circuit 10 provided between outer power supply Vcc and an inner circuit 2 so as to be fed to the inner circuit 2. The inner step-down circuit 10 is composed of a resistance element 12 laid between the gate of an NMOS transistor 11 and the outer power supply Vcc as a high tension power supply as well as a capacitor element 13 laid between said gate and a low tension power supply together with said elements. Accordingly, the gate potential VGS can not follow after the fluctuation of the outer power supply Vcc but only fluctuate slightly due to the resistance element 12. Through these procedures, the inner circuit 2 can be supplied with stable power thereby enabling the erroneous operation and the decrease in operation rate to be avoided.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit device, the present invention suppresses fluctuations in an internal power supply in response to fluctuations in an external power supply, and supplies stable power to an internal circuit to prevent malfunction of the internal circuit and decrease in operating speed. In order to provide a semiconductor integrated circuit device that can protect the external power supply, an internal step-down circuit is provided between an external power supply and an integrated internal circuit that performs predetermined signal processing. The internal step-down circuit is configured with an NMOS transistor and is activated by applying a predetermined potential to the gate of the NMOS transistor to step down the external power supply and supply it to the internal circuit. In the semiconductor integrated circuit device to be supplied, a resistive element is inserted between the gate of the NMO3 transistor and an external power source which is a high potential power source, and a capacitive element is inserted between the gate and a low potential power source. , these elements are included to form an internal voltage down converter.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that uses a power supply voltage that is internally stepped down.

In recent years, as semiconductor integrated circuits have become highly integrated, the true carrier effect has become more prominent as elements become smaller. especially,
When the channel length of the NMOS transistor becomes submicron while the power supply voltage remains at 5■, a high electric field is generated near the train, and the hot carriers that are accelerated there and obtain a high energy efficiency are The so-called true carrier problem, which causes fluctuations and changes over time, is a major obstacle to constant voltage scaling.

One solution to the above problem is that the external supply voltage is 5
There is a system that operates internally at 5V or less (for example, 3V) by preparing an internal step-down circuit that steps down the power supply voltage on-chip.

[Prior Art] As a conventional semiconductor integrated circuit device having an internal voltage step-down circuit, the one shown in FIG. 6, for example, is known. In the figure, an external power supply Vcc (for example, 5V) is stepped down to an internal power supply VaNt (for example, 4V) by an NMOS transistor 1B constituting an internal voltage step-down circuit, and is supplied to an internal circuit 2. The gate of NMOS transistor 1 is connected to the drain, and external power supply VCC passes through NMOS transistor 1, so that (Vcc −V thn
) is stepped down to Lehel VINT. Note that V thn is the threshold voltage of the NMOS transistor 1. The internal circuit 2 includes various logic circuits within a chip, such as memory cells and sense amplifiers when applied to a semiconductor memory as a semiconductor integrated circuit device.

[Problem to be solved by the invention]

However, in such a conventional O semiconductor integrated circuit device, as shown in FIG.
Since the gate potential of VINT fluctuates accordingly, the internal power supply VINT increases (fluctuations (fluctuation width is dV+at)), making it impossible to supply stable power to the internal circuits, causing malfunctions of the internal circuits, and reductions in operating speed. There was a problem in that it invited

SUMMARY OF THE INVENTION Therefore, the present invention provides a semiconductor integrated circuit device that suppresses fluctuations in the internal power supply in response to fluctuations in the external power supply, supplies stable power to the internal circuit, and prevents malfunction of the internal circuit and reduction in operating speed. It is intended to.

Means for Solving the 3 Problems] In order to achieve the above object, the semiconductor integrated circuit device according to the present invention has an external type fiX' as shown in FIG.
An internal step-down circuit 10 is provided between the integrated internal circuit 2, which performs predetermined signal processing, and the internal step-down circuit 1.
0C: In addition to lowering the voltage of the external type 1lvcC and supplying it to the internal circuit 2, the internal step-down circuit]O is configured with an NMOS transistor 11, and a predetermined potential is applied to the gate of the NMOS transistor 11. In this semiconductor integrated circuit device, a resistive element 12 is inserted between the gate of the NMO54 transistor 11 and the external power source VCC, which is a high potential power source, in a semiconductor integrated circuit device that operates at , the gate and the low potential power supply (
For example, a capacitive element 13 is inserted between the capacitive element 13 and the ground potential (Vss), and the internal step-down circuit 10 is configured including each of these elements 12 and 13.

[Effect]

In the present invention, as shown in the operational waveform diagram in FIG.
Since the resistive element 12 and the capacitive element 13 are connected to the gate of the resistive element 12, the gate potential VGS cannot follow the fluctuation of the external type avcc due to the resistive element 12, and the capacitive element 13
The charge stored in the gate does not change dramatically, but only fluctuates slowly.

Therefore, the gate potential VGS changes only slightly, and the fluctuation dvINA of the internal NaV I NT can be kept small.

Therefore, stable power is supplied to the internal circuit 2, and malfunction of the internal circuit 2 and reduction in operating speed are prevented.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 3 is a diagram showing a first embodiment of a semiconductor integrated circuit device (corresponding to an integrated circuit chip; the same applies hereinafter) according to the present invention. In describing this embodiment, the same components as those in the circuit of FIG. 1 are designated by the same reference numerals, and redundant explanation will be omitted.

In Fig. 3, this device uses PMO3I as a resistance element.
- A run transistor 21 is provided, and a capacitor 22 of a predetermined capacity is provided in addition to the capacitive element. Then, p:x
The gate of the ost run star 21 is grounded. PM
O5) Transistor 2], capacitor 22 and Otsu1\MO
The S transistor 11 constitutes an internal voltage circuit 23. The internal circuit 2 includes, for example, a memory cell, a sense amplifier, etc. when applied to a semiconductor memory as a semiconductor integrated circuit device.

In the above configuration, in this embodiment, the PMOS transistor 21 is in the on state and works as a resistance element, so the operating principle accompanying fluctuations in the external power supply Vcc is the same as the explanation of the operation of the present invention described above, and the NMOS transistor 11 Internal power supply VIN by suppressing fluctuations in gate potential VGS
T fluctuations dV and NA can be suppressed. As a result, stable power can be supplied to the internal circuit 2, and malfunctions and reductions in operating speed of the internal circuit 2 can be prevented.

Note that if the PM○S transistor 21 is used as the resistance element as in this embodiment, the impedance is high, so there is an advantage that the area of the layout pattern can be reduced.

Next, FIG. 4 shows a second diagram of the semiconductor integrated circuit device according to the present invention.
This is a diagram showing an example, and this example is a capacitive element! '
This circuit uses a capacitor C6 of Nin7Costa11, and is otherwise the same as the circuit shown in FIG. In this embodiment, the PMOS including the gate capacitance C6
Transistor 21 and NMOS transistor 11 constitute internal voltage down converter 24 .

Therefore, there is an advantage that there is no need to newly provide a capacitor, and the area of the layout pattern can be reduced.

FIG. 5 is a diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, a resistor 25 is provided instead of the PMOS transistor as a resistor element, and the circuit of FIG. 4 is used as a capacitor element. Similarly, the gate capacitance C0 of the NMOS transistor 11 is used. It goes without saying that the same effects as described above can be obtained in this embodiment as well.

Although each of the embodiments described above is an example in which the present invention is applied to a semiconductor memory, the present invention is not limited thereto, and can be applied to any other semiconductor integrated circuit device.

Effects of the Invention: According to the present invention, fluctuations in the internal power supply can be suppressed compared to fluctuations in the external power supply, and stable power can be supplied to the internal circuit. Therefore, malfunction of internal circuits,
This can prevent a decrease in operating speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram explaining the present invention in detail, FIG. 2 is a waveform diagram explaining the present invention in detail, and FIG. 3 is a circuit diagram showing a first embodiment of the semiconductor integrated circuit device according to the present invention. 4 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention, FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 6.7 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention. It is a figure which shows the conventional semiconductor integrated circuit device, 6th is its circuit diagram, and 7th is a waveform diagram explaining its operation|movement. 2...Internal circuit, 10, 23.24.26...Internal step-down circuit, 1
1......NMOS transistor, 1
2... Resistance element, 13... Capacitive element, 21... PMOS) transistor (resistance element) 2
2... Capacitor (capacitive element), 25...
...Resistance (resistance element). Circuit diagram of the first embodiment Fig. 3 A circuit diagram explaining the present invention in detail Fig. 1 Waveform diagram explaining the present invention in detail Fig. 1 A circuit diagram of the conventional example

Claims (1)

[Claims] An internal step-down circuit is provided between an external power source and an integrated internal circuit that performs predetermined signal processing, and the internal step-down circuit steps down the external power source and supplies it to the internal circuit. In a semiconductor integrated circuit device, the internal step-down circuit is configured with an NMOS transistor and is activated by applying a predetermined potential to the gate of the NMOS transistor to step down the external power supply and supply it to the internal circuit. A resistive element is inserted between the gate and an external high-potential power source, and a capacitive element is inserted between the gate and a low-potential power source, and an internal step-down circuit is constructed by including each of these elements. A semiconductor integrated circuit device characterized by: