JPH0320745A - Resist pattern forming method - Google Patents

Resist pattern forming method

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Publication number
JPH0320745A
JPH0320745A JP15514289A JP15514289A JPH0320745A JP H0320745 A JPH0320745 A JP H0320745A JP 15514289 A JP15514289 A JP 15514289A JP 15514289 A JP15514289 A JP 15514289A JP H0320745 A JPH0320745 A JP H0320745A
Authority
JP
Japan
Prior art keywords
resist
substrate
pattern
silicon
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15514289A
Other languages
Japanese (ja)
Other versions
JP2504832B2 (en
Inventor
Ryohei Kawabata
川端 良平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1155142A priority Critical patent/JP2504832B2/en
Publication of JPH0320745A publication Critical patent/JPH0320745A/en
Application granted granted Critical
Publication of JP2504832B2 publication Critical patent/JP2504832B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE:To reduce ruggedness of the ends of a resist and to enable fine working on a substrate having high level differences by adding a Si compound into the gas to be used for the reactive ion etching. CONSTITUTION:The resist 4 is applied on the substrate having high level differences 5 formed by laminating SiO2 2 and Al 3 on the Si substrate 1 so as to almost flatten the surface, and a desired pattern is printed through a photomask 6. Then, the surface is exposed to gaseous hexamethyldisilazane (HMDS) and like, while heating the substrate 1, to form a sililated layer 7 on the exposed parts of the resist 4. The resist 4 is dry developed by the reactive ion etching using oxygen having a desired amount of HMDS added, to form a resist pattern 8, and an Al printed circuit pattern 9 is formed by treating it by the dry etching process.

Description

【発明の詳細な説明】 く産業上の利用分野〉 本発明は、超LSI製造プロセスに釦ける微細加工技術
、なかでもレジストパターンの形成技術KWAする。
DETAILED DESCRIPTION OF THE INVENTION Industrial Application Fields The present invention relates to microfabrication technology used in the VLSI manufacturing process, particularly resist pattern formation technology.

〈従来の技術〉 超LSIの微細加工は、主として縮小投影露光装置を用
いたいわいるフォ} IJングラフィ技術(写真製版技
術)を用いて行なわれている。超LSIの高集積7ヒに
伴って、縮小投影露光装置の解像度限界ぎりぎりのサプ
ミクロン以下のパターンを形成する必要性が生1れてい
る。曾た、最近のLSIは集積度の向上のために3次元
化が進み、その結果、高段差(1μmレベル)の基板上
に微細パターンを形戊する必要性が生じている。
<Prior Art> Microfabrication of VLSIs is mainly performed using a so-called IJ lithography technique (photolithography technique) using a reduction projection exposure apparatus. With the increasing integration of VLSIs, there is a need to form submicron patterns, which is at the very limit of the resolution of reduction projection exposure apparatuses. Recently, LSIs have become three-dimensional in order to improve the degree of integration, and as a result, it has become necessary to form fine patterns on substrates with high height differences (1 μm level).

高段差上に微細パターンを形成する方法として3層レジ
ストプロセスが知られているが、プロセスが複雑である
という欠点がある。これを解決するために、シリル化レ
ジストプロセスが開発され、サ−y”ミクロンレベルの
加工に有効であることが示笛れている。
A three-layer resist process is known as a method for forming fine patterns on high-level differences, but it has the disadvantage that the process is complicated. To solve this problem, a silylated resist process has been developed and has been shown to be effective for processing at the 3000-inch micron level.

く発明が解決しようとする課題〉 一方、ンリル化レジストプロセスの欠点ハ、パターン端
邪の凹凸が大きい点にあり、このプロセスを0、5μ瓜
やそれ以下のバクーン形成に応用する場合の問題点とな
ってきた。バクーン端部の凹凸の発生のメカニズムは、
未だ明確でなく、過去、レジストの組或の改良や、シリ
コン化合物の選択拡散条件の改良が行なわれてきた。本
発明は、シリル化レジストプロセスにかけるノくクーン
端部の凹凸の問題を、ドライ現像方法の改良により解決
するものである。すなわち、本発明は、ドライ現像方法
の改良により、パターン端部の凹凸の少ないシリル化レ
ジストプロセスを実現し、高段差基板上でのO.S ミ
クロン以下の加工を可能にするものである。
Problems to be Solved by the Invention On the other hand, the disadvantage of the untreated resist process is that the edges of the pattern have large irregularities, which is a problem when this process is applied to the formation of 0.5μ melons or smaller. It has become. The mechanism of occurrence of unevenness at the edge of Bakun is as follows.
It is still not clear, and in the past, improvements have been made to the composition of resists and the conditions for selective diffusion of silicon compounds. The present invention solves the problem of unevenness at the edge of a resist film subjected to a silylated resist process by improving a dry development method. That is, the present invention realizes a silylated resist process with less unevenness at the edge of a pattern by improving the dry development method, and improves O.I. S It enables processing of microns or less.

く課題を解決するための手段〉 本発明のレジストパターンの形成方法は、基板上にフォ
トレジストを塗布する工程と、露光装置ヲ用いマスクパ
ターンをフォトレジスト上に焼き付ける工程と、レジス
トの露光部分に少なくとも分子中にシリコンを含む化合
物を選択拡散させる工程と、主として酸素を用いた反応
性イオンエッチングにより未露光部分のレジストを選択
的に除去しドライ現偉する工程とを含む、レジストパタ
ーンの形成方法において、反応性イオンエッチングによ
るドライ現像のガス中に少なくとも分子中にシリコンを
含む化合物を添加することを特徴とするものである。
Means for Solving the Problems> The method for forming a resist pattern of the present invention includes a step of applying a photoresist on a substrate, a step of printing a mask pattern onto the photoresist using an exposure device, and a step of printing a mask pattern on the exposed portion of the resist. A method for forming a resist pattern, comprising the steps of selectively diffusing a compound containing at least silicon in its molecules, and selectively removing unexposed portions of the resist by reactive ion etching mainly using oxygen and dry-developing the resist. The method is characterized in that a compound containing at least silicon in its molecules is added to the gas for dry development by reactive ion etching.

く実施例〉 以下,HMDS(ヘキサメチルジシラザン(CHs)3
Si(NH)Si(CH3 )a )をシリコン拡散源
として用いたシリル化レジストプロセスを例にとって、
本発明の詳細を説明する。
Examples> Hereinafter, HMDS (hexamethyldisilazane (CHs)
Taking as an example a silylated resist process using Si(NH)Si(CH3)a ) as a silicon diffusion source,
The details of the present invention will be explained.

第1図はシリル化レジストプロセスの工程断面図である
FIG. 1 is a cross-sectional view of the silylated resist process.

ここでは、高段差基板上のアルミニウム上のレジストパ
ターン形成プロセスを(1.0μ汎の段差上にアルミニ
ウムを1.0μ扉厚形成している)例に説明する。1ず
、基板上にレジストを塗布し、溶剤を除去する程度にベ
ーキングする。アルミニウムのドライエッチングを精度
良く行なうためには1.0μ扉以上のレジスト厚が必要
である。段差上のレジストは、ほぼ平坦に塗布されるた
め、第1図(a)に示すように、凹部のレジスト膜厚は
2.0μ私凸部のレジスト膜厚は1.0μ扉となる。な
か、第1図0)に於いて、1ぱSi基板、2はSi02
、3はアルミニウム、4はレジストである。1た、5は
段差部である。
Here, a process for forming a resist pattern on aluminum on a high-step substrate will be described as an example (aluminum is formed to a thickness of 1.0 μm on a step of 1.0 μm wide). First, a resist is applied onto the substrate and baked to remove the solvent. In order to perform dry etching of aluminum with high precision, a resist thickness of 1.0 μm or more is required. Since the resist on the step is applied almost flat, as shown in FIG. 1(a), the resist film thickness on the concave portion is 2.0 μm, and the resist film thickness on the convex portion is 1.0 μm. Among them, in Fig. 1 0), 1 is a Si substrate, 2 is a Si02
, 3 is aluminum, and 4 is resist. 1 and 5 are step portions.

このレジスト上に縮小投影露光装置を用いてマスクパタ
ーンを焼き付ける。露光の結果、第1図(b)に示すよ
うに、レジストパターンに対応シた部分の感光基が分解
される。感光基の分解の度合は、光強度の強いレジスト
表面でより大きい。なか、第1図(b)に於いて、6は
フォトマスクである。
A mask pattern is printed onto this resist using a reduction projection exposure device. As a result of the exposure, the photosensitive groups in the portions corresponding to the resist pattern are decomposed, as shown in FIG. 1(b). The degree of decomposition of photosensitive groups is greater on the resist surface where the light intensity is high. Among them, 6 in FIG. 1(b) is a photomask.

次に、第1図(C)に示すように、基板を150から2
00度程度の温度に保ちながら、ガス状のHMDS中に
さらし、I{MDS中のシリコンを感光基の分解された
領域に選択的に拡散させる(シリル化)。露光量と拡散
条件を最適化することで、感光基の分解の割合の大きい
レジスト表面から約0.2μmの部分にシリコンを拡散
することかで1る。
Next, as shown in FIG. 1(C), the substrate is
It is exposed to gaseous HMDS while maintaining the temperature at about 0.000C, and silicon in I{MDS is selectively diffused into the region where the photosensitive group has been decomposed (silylation). By optimizing the exposure amount and diffusion conditions, it is possible to diffuse silicon into a portion approximately 0.2 μm from the resist surface where the rate of photosensitive group decomposition is large.

なか、WIJI図(C)に於いて、7はシリル化層であ
る。
In the WIJI diagram (C), 7 is a silylated layer.

続いて、酸素ガスを用いた反応性イオンエッチングで基
板を処理する。シリコンが拡散された領域は、酸素プラ
ズマにより酸化され、シリコン酸化物を形成し、耐エッ
チングマスクとなる。一方、シリコンが拡散されていな
い領域は、通常のレジストと同様に酸素ラジカルや酸素
イオンと反応してエソチングされる。以上の反応の結果
、レジストパターンはドライ現像され、高段差基板上に
レジストパターン8が形威される(第1図(d))。こ
のレジストパターンを用いて従来技術のアルミニウムの
ドライエッチング法を適用することで、所望のアルミ配
線パターン9が形成できる(第1図(e), (f))
Subsequently, the substrate is processed by reactive ion etching using oxygen gas. The region where silicon is diffused is oxidized by oxygen plasma to form silicon oxide, which serves as an etching-resistant mask. On the other hand, regions where silicon is not diffused are etched by reacting with oxygen radicals and oxygen ions, similar to a normal resist. As a result of the above reaction, the resist pattern is dry developed and a resist pattern 8 is formed on the high-step substrate (FIG. 1(d)). By applying the conventional aluminum dry etching method using this resist pattern, the desired aluminum wiring pattern 9 can be formed (Fig. 1 (e), (f)).
.

本プロセスを適用した場合の、レジスト端面の凹凸は、
片側最大0.1μ扉程度である。この凹凸がアルミニウ
ムの加工形状に反映され、アルミニウム配線の側面が凸
凹になる。このような配線側面の凹凸は、局所的な電流
密度の増加を招き、配線信頼性の低下をもたらす。
When this process is applied, the unevenness of the resist end face is
The maximum door size on one side is about 0.1μ. This unevenness is reflected in the processed shape of the aluminum, and the side surfaces of the aluminum wiring become uneven. Such unevenness on the side surface of the wiring causes a local increase in current density, resulting in a decrease in wiring reliability.

本発明者は、ドライ現像後のレジスト側面を詳細に観察
・分析することにより、レジスト端面の凹凸の発生のメ
カニズムを調べた。その結果、ドライ現像時にレジスト
の側面に皺が形成され、この皺がレジスト端面の凹凸の
主原因であることを見い出した。1た、レジスト側面の
皺を分析すると、シリコンが観察されること、及びフッ
酸を含む水溶液で皺がほとんど除去できること、が明ら
かになった。これらの結果から、本発明者は、側面の皺
にはシリコンの酸化物が含玄れていると推定した。実験
例のシリル化プロセスの条件から判断して、エソチング
前にシリコンがレジスト深くに寸で浸透しているとは考
えられない。したがって、シリコン酸化物はエンチング
中に側面に付着したものと考えられる。以上の結果に基
づいて、本発明者は、側壁の皺の発生のメカニズムを次
のように推定した。
The present inventor investigated the mechanism of occurrence of unevenness on the end face of the resist by observing and analyzing in detail the side surface of the resist after dry development. As a result, it has been found that wrinkles are formed on the side surfaces of the resist during dry development, and that these wrinkles are the main cause of unevenness on the end faces of the resist. Furthermore, analysis of wrinkles on the side surface of the resist revealed that silicon was observed and that most of the wrinkles could be removed with an aqueous solution containing hydrofluoric acid. From these results, the inventor estimated that the wrinkles on the side surface contained silicon oxide. Judging from the conditions of the silylation process in the experimental example, it is unlikely that the silicon penetrates deeply into the resist before ethoching. Therefore, it is considered that silicon oxide was attached to the side surfaces during etching. Based on the above results, the present inventor estimated the mechanism of generation of wrinkles on the sidewall as follows.

側壁に形成されるシリコン酸化物の供給源は露光領域に
拡散ざれたシリコンであり、ドライ現像中に、イオン衝
撃により気相中にたたき出され側壁に付着する。底面に
付着したシリコン酸化物は、イオン衝撃によりたたき出
されるので、結果的に側面にシリコン酸化物が集!ジや
すい。このシリコン酸化物が、なんらかのメカニズムで
側面に不均一に付着すると考える。シリコン酸化物が付
着しない領域は酸素ラジカルにより横方向にエッチング
されるが、シリコン酸化物が付着した領域は横方向にエ
ッチングされないので、その結果、レジスト側面に皺が
形成される。
The source of silicon oxide formed on the sidewalls is silicon diffused into the exposed area, which is ejected into the gas phase by ion bombardment during dry development and adheres to the sidewalls. Silicon oxide adhering to the bottom surface is knocked out by ion bombardment, resulting in silicon oxide gathering on the sides! It's easy to do. It is believed that this silicon oxide adheres non-uniformly to the side surfaces by some mechanism. The regions to which silicon oxide is not attached are laterally etched by oxygen radicals, but the regions to which silicon oxide is attached are not etched laterally, and as a result, wrinkles are formed on the side surfaces of the resist.

上記モデルに基づき、本発明者は、側壁を保護するシリ
コンを気相中から連続的に十分に供給することによD1
側壁にシリコン酸化物による横方向のエッチングに対す
る保護膜を均一に形成させるという着想を得た。側壁保
護膜を均一に形成させることによb1側面の皺を低減で
き、その結果、レジストパターン端部の凹凸を低減でき
ることになる。
Based on the above model, the inventor of the present invention has developed D1 by continuously supplying sufficient silicon to protect the sidewalls from the gas phase.
The idea was to uniformly form a protective film against lateral etching using silicon oxide on the sidewalls. By uniformly forming the sidewall protective film, wrinkles on the b1 side surface can be reduced, and as a result, unevenness at the end of the resist pattern can be reduced.

ドライ現像中にシリコンを気相で供給するための供給源
としては、少なくとも分子中にシリコンを含む化合物を
気相で供給することが考えられる。
As a supply source for supplying silicon in a vapor phase during dry development, it is conceivable to supply a compound containing at least silicon in its molecule in a vapor phase.

具体的な化合物としては、HMDS(ヘキサメチルジシ
ラザ7(cHa)asr(NH)Si(CH8)3)、
SiH4、SiCl4、SiF4などが考えられる。表
1に、酸素にHMDSを添加して、ドライ現像を行なっ
た場合の結果を示す。予想された通う、レジスト側面の
皺が消滅し、それに伴ってレジスト端面の凹凸も低減さ
れた。同様の効果が、分子中に少なくともシリコンを含
む化合物を気相で供給することで実現できることが容易
に推察される。
Specific compounds include HMDS (hexamethyldisilaza7(cHa)asr(NH)Si(CH8)3),
Possible materials include SiH4, SiCl4, and SiF4. Table 1 shows the results when dry development was performed by adding HMDS to oxygen. The expected wrinkles on the sides of the resist disappeared, and the unevenness on the end faces of the resist was also reduced. It is easily inferred that a similar effect can be achieved by supplying a compound containing at least silicon in the molecule in the gas phase.

く発明の効果〉 本発明のドライ現像方法を用いることにより、レジスト
端部の凹凸の少ない、高品質のレジストパターンを形成
できた。その結果、信頼性の高い微細なメタル配線を精
度良く形成できるようになった0
Effects of the Invention> By using the dry development method of the present invention, a high-quality resist pattern with less unevenness at the edges of the resist could be formed. As a result, it has become possible to form highly reliable fine metal wiring with high precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はシリル化レジストプロセスの工程断面図である
。 符号の説明 1sSi基板、2 : S i 02、3:アルミニウ
ム、4:レジスト、5:段差部、6:フォトマスク、7
:シリル化層、8:レジストパターン、9:アルミニウ
ム配線。 その他の条件
FIG. 1 is a cross-sectional view of the silylated resist process. Explanation of symbols 1sSi substrate, 2: Si02, 3: Aluminum, 4: Resist, 5: Step portion, 6: Photomask, 7
: silylated layer, 8: resist pattern, 9: aluminum wiring. Other conditions

Claims (1)

【特許請求の範囲】[Claims] 1、基板上にフォトレジストを塗布する工程と、露光装
置を用いマスクパターンをフォトレジスト上に焼き付け
る工程と、レジストの露光部分に少なくとも分子中にシ
リコンを含む化合物を選択拡散させる工程と、主として
酸素を用いた反応性イオンエッチングにより未露光部分
のレジストを選択的に除去しドライ現像する工程とを含
む、レジストパターンの形成方法において、反応性イオ
ンエッチングによるドライ現像のガス中に少なくとも分
子中にシリコンを含む化合物を添加することを特徴とす
るレジストパターンの形成方法。
1. A step of applying a photoresist onto a substrate, a step of baking a mask pattern onto the photoresist using an exposure device, a step of selectively diffusing a compound containing at least silicon in its molecules into the exposed part of the resist, and a step of mainly using oxygen. A method for forming a resist pattern includes a step of selectively removing unexposed portions of the resist by reactive ion etching using reactive ion etching and dry development. A method for forming a resist pattern, the method comprising adding a compound containing.
JP1155142A 1989-06-16 1989-06-16 Method of forming resist pattern Expired - Fee Related JP2504832B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1155142A JP2504832B2 (en) 1989-06-16 1989-06-16 Method of forming resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1155142A JP2504832B2 (en) 1989-06-16 1989-06-16 Method of forming resist pattern

Publications (2)

Publication Number Publication Date
JPH0320745A true JPH0320745A (en) 1991-01-29
JP2504832B2 JP2504832B2 (en) 1996-06-05

Family

ID=15599463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1155142A Expired - Fee Related JP2504832B2 (en) 1989-06-16 1989-06-16 Method of forming resist pattern

Country Status (1)

Country Link
JP (1) JP2504832B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294465B1 (en) * 1999-10-29 2001-09-25 Agere Systems Guardian Corp. Method for making integrated circuits having features with reduced critical dimensions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57202533A (en) * 1981-06-09 1982-12-11 Fujitsu Ltd Formation of pattern
JPS5912433A (en) * 1982-07-13 1984-01-23 Fujitsu Ltd Dry developable positive type resist composition
JPS62273528A (en) * 1986-05-21 1987-11-27 Nippon Telegr & Teleph Corp <Ntt> Method for silylating surface of polymer film and pattern forming method using same
JPS63253356A (en) * 1987-02-20 1988-10-20 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57202533A (en) * 1981-06-09 1982-12-11 Fujitsu Ltd Formation of pattern
JPS5912433A (en) * 1982-07-13 1984-01-23 Fujitsu Ltd Dry developable positive type resist composition
JPS62273528A (en) * 1986-05-21 1987-11-27 Nippon Telegr & Teleph Corp <Ntt> Method for silylating surface of polymer film and pattern forming method using same
JPS63253356A (en) * 1987-02-20 1988-10-20 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294465B1 (en) * 1999-10-29 2001-09-25 Agere Systems Guardian Corp. Method for making integrated circuits having features with reduced critical dimensions

Also Published As

Publication number Publication date
JP2504832B2 (en) 1996-06-05

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